dml_wrapper_translation.c (7169B)
1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#ifdef DML_WRAPPER_TRANSLATION_ 27 28static void gfx10array_mode_to_dml_params( 29 enum array_mode_values array_mode, 30 enum legacy_tiling_compat_level compat_level, 31 unsigned int *sw_mode) 32{ 33 switch (array_mode) { 34 case DC_ARRAY_LINEAR_ALLIGNED: 35 case DC_ARRAY_LINEAR_GENERAL: 36 *sw_mode = dm_sw_linear; 37 break; 38 case DC_ARRAY_2D_TILED_THIN1: 39// DC_LEGACY_TILING_ADDR_GEN_ZERO - undefined as per current code hence removed 40#if 0 41 if (compat_level == DC_LEGACY_TILING_ADDR_GEN_ZERO) 42 *sw_mode = dm_sw_gfx7_2d_thin_l_vp; 43 else 44 *sw_mode = dm_sw_gfx7_2d_thin_gl; 45#endif 46 break; 47 default: 48 ASSERT(0); /* Not supported */ 49 break; 50 } 51} 52 53static void swizzle_to_dml_params( 54 enum swizzle_mode_values swizzle, 55 unsigned int *sw_mode) 56{ 57 switch (swizzle) { 58 case DC_SW_LINEAR: 59 *sw_mode = dm_sw_linear; 60 break; 61 case DC_SW_4KB_S: 62 *sw_mode = dm_sw_4kb_s; 63 break; 64 case DC_SW_4KB_S_X: 65 *sw_mode = dm_sw_4kb_s_x; 66 break; 67 case DC_SW_4KB_D: 68 *sw_mode = dm_sw_4kb_d; 69 break; 70 case DC_SW_4KB_D_X: 71 *sw_mode = dm_sw_4kb_d_x; 72 break; 73 case DC_SW_64KB_S: 74 *sw_mode = dm_sw_64kb_s; 75 break; 76 case DC_SW_64KB_S_X: 77 *sw_mode = dm_sw_64kb_s_x; 78 break; 79 case DC_SW_64KB_S_T: 80 *sw_mode = dm_sw_64kb_s_t; 81 break; 82 case DC_SW_64KB_D: 83 *sw_mode = dm_sw_64kb_d; 84 break; 85 case DC_SW_64KB_D_X: 86 *sw_mode = dm_sw_64kb_d_x; 87 break; 88 case DC_SW_64KB_D_T: 89 *sw_mode = dm_sw_64kb_d_t; 90 break; 91 case DC_SW_64KB_R_X: 92 *sw_mode = dm_sw_64kb_r_x; 93 break; 94 case DC_SW_VAR_S: 95 *sw_mode = dm_sw_var_s; 96 break; 97 case DC_SW_VAR_S_X: 98 *sw_mode = dm_sw_var_s_x; 99 break; 100 case DC_SW_VAR_D: 101 *sw_mode = dm_sw_var_d; 102 break; 103 case DC_SW_VAR_D_X: 104 *sw_mode = dm_sw_var_d_x; 105 break; 106 107 default: 108 ASSERT(0); /* Not supported */ 109 break; 110 } 111} 112 113static void dc_timing_to_dml_timing(const struct dc_crtc_timing *timing, struct _vcs_dpi_display_pipe_dest_params_st *dest) 114{ 115 dest->hblank_start = timing->h_total - timing->h_front_porch; 116 dest->hblank_end = dest->hblank_start 117 - timing->h_addressable 118 - timing->h_border_left 119 - timing->h_border_right; 120 dest->vblank_start = timing->v_total - timing->v_front_porch; 121 dest->vblank_end = dest->vblank_start 122 - timing->v_addressable 123 - timing->v_border_top 124 - timing->v_border_bottom; 125 dest->htotal = timing->h_total; 126 dest->vtotal = timing->v_total; 127 dest->hactive = timing->h_addressable; 128 dest->vactive = timing->v_addressable; 129 dest->interlaced = timing->flags.INTERLACE; 130 dest->pixel_rate_mhz = timing->pix_clk_100hz/10000.0; 131 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 132 dest->pixel_rate_mhz *= 2; 133} 134 135static enum odm_combine_mode get_dml_odm_combine(const struct pipe_ctx *pipe) 136{ 137 int odm_split_count = 0; 138 enum odm_combine_mode combine_mode = dm_odm_combine_mode_disabled; 139 struct pipe_ctx *next_pipe = pipe->next_odm_pipe; 140 141 // Traverse pipe tree to determine odm split count 142 while (next_pipe) { 143 odm_split_count++; 144 next_pipe = next_pipe->next_odm_pipe; 145 } 146 pipe = pipe->prev_odm_pipe; 147 while (pipe) { 148 odm_split_count++; 149 pipe = pipe->prev_odm_pipe; 150 } 151 152 // Translate split to DML odm combine factor 153 switch (odm_split_count) { 154 case 1: 155 combine_mode = dm_odm_combine_mode_2to1; 156 break; 157 case 3: 158 combine_mode = dm_odm_combine_mode_4to1; 159 break; 160 default: 161 combine_mode = dm_odm_combine_mode_disabled; 162 } 163 164 return combine_mode; 165} 166 167static int get_dml_output_type(enum signal_type dc_signal) 168{ 169 int dml_output_type = -1; 170 171 switch (dc_signal) { 172 case SIGNAL_TYPE_DISPLAY_PORT_MST: 173 case SIGNAL_TYPE_DISPLAY_PORT: 174 dml_output_type = dm_dp; 175 break; 176 case SIGNAL_TYPE_EDP: 177 dml_output_type = dm_edp; 178 break; 179 case SIGNAL_TYPE_HDMI_TYPE_A: 180 case SIGNAL_TYPE_DVI_SINGLE_LINK: 181 case SIGNAL_TYPE_DVI_DUAL_LINK: 182 dml_output_type = dm_hdmi; 183 break; 184 default: 185 break; 186 } 187 188 return dml_output_type; 189} 190 191static void populate_color_depth_and_encoding_from_timing(const struct dc_crtc_timing *timing, struct _vcs_dpi_display_output_params_st *dout) 192{ 193 int output_bpc = 0; 194 195 switch (timing->display_color_depth) { 196 case COLOR_DEPTH_666: 197 output_bpc = 6; 198 break; 199 case COLOR_DEPTH_888: 200 output_bpc = 8; 201 break; 202 case COLOR_DEPTH_101010: 203 output_bpc = 10; 204 break; 205 case COLOR_DEPTH_121212: 206 output_bpc = 12; 207 break; 208 case COLOR_DEPTH_141414: 209 output_bpc = 14; 210 break; 211 case COLOR_DEPTH_161616: 212 output_bpc = 16; 213 break; 214 case COLOR_DEPTH_999: 215 output_bpc = 9; 216 break; 217 case COLOR_DEPTH_111111: 218 output_bpc = 11; 219 break; 220 default: 221 output_bpc = 8; 222 break; 223 } 224 225 switch (timing->pixel_encoding) { 226 case PIXEL_ENCODING_RGB: 227 case PIXEL_ENCODING_YCBCR444: 228 dout->output_format = dm_444; 229 dout->output_bpp = output_bpc * 3; 230 break; 231 case PIXEL_ENCODING_YCBCR420: 232 dout->output_format = dm_420; 233 dout->output_bpp = (output_bpc * 3.0) / 2; 234 break; 235 case PIXEL_ENCODING_YCBCR422: 236 if (timing->flags.DSC && !timing->dsc_cfg.ycbcr422_simple) 237 dout->output_format = dm_n422; 238 else 239 dout->output_format = dm_s422; 240 dout->output_bpp = output_bpc * 2; 241 break; 242 default: 243 dout->output_format = dm_444; 244 dout->output_bpp = output_bpc * 3; 245 } 246} 247 248static enum source_format_class dc_source_format_to_dml_source_format(enum surface_pixel_format dc_format) 249{ 250 enum source_format_class dml_format = dm_444_32; 251 252 switch (dc_format) { 253 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 254 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 255 dml_format = dm_420_8; 256 break; 257 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 258 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 259 dml_format = dm_420_10; 260 break; 261 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 262 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 263 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 264 dml_format = dm_444_64; 265 break; 266 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 267 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 268 dml_format = dm_444_16; 269 break; 270 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: 271 dml_format = dm_444_8; 272 break; 273 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 274 dml_format = dm_rgbe_alpha; 275 break; 276 default: 277 dml_format = dm_444_32; 278 break; 279 } 280 281 return dml_format; 282} 283 284#endif