cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

dccg.h (3972B)

      1/*
      2 * Copyright 2018 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: AMD
     23 *
     24 */
     25
     26#ifndef __DAL_DCCG_H__
     27#define __DAL_DCCG_H__
     28
     29#include "dc_types.h"
     30#include "hw_shared.h"
     31
     32enum phyd32clk_clock_source {
     33	PHYD32CLKA,
     34	PHYD32CLKB,
     35	PHYD32CLKC,
     36	PHYD32CLKD,
     37	PHYD32CLKE,
     38	PHYD32CLKF,
     39	PHYD32CLKG,
     40};
     41
     42enum physymclk_clock_source {
     43	PHYSYMCLK_FORCE_SRC_SYMCLK,    // Select symclk as source of clock which is output to PHY through DCIO.
     44	PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DCIO.
     45	PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO.
     46};
     47
     48enum hdmistreamclk_source {
     49	REFCLK,                   // Selects REFCLK as source for hdmistreamclk.
     50	DTBCLK0,                  // Selects DTBCLK0 as source for hdmistreamclk.
     51};
     52
     53enum dentist_dispclk_change_mode {
     54	DISPCLK_CHANGE_MODE_IMMEDIATE,
     55	DISPCLK_CHANGE_MODE_RAMPING,
     56};
     57
     58struct dccg {
     59	struct dc_context *ctx;
     60	const struct dccg_funcs *funcs;
     61	int pipe_dppclk_khz[MAX_PIPES];
     62	int ref_dppclk;
     63	//int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
     64	//int audio_dtbclk_khz;/* TODO needs to be removed */
     65	int ref_dtbclk_khz;/* TODO needs to be removed */
     66};
     67
     68struct dtbclk_dto_params {
     69	const struct dc_crtc_timing *timing;
     70	int otg_inst;
     71	int pixclk_khz;
     72	int req_audio_dtbclk_khz;
     73	int num_odm_segments;
     74	int ref_dtbclk_khz;
     75};
     76
     77struct dccg_funcs {
     78	void (*update_dpp_dto)(struct dccg *dccg,
     79			int dpp_inst,
     80			int req_dppclk);
     81	void (*get_dccg_ref_freq)(struct dccg *dccg,
     82			unsigned int xtalin_freq_inKhz,
     83			unsigned int *dccg_ref_freq_inKhz);
     84	void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
     85			bool en);
     86	void (*otg_add_pixel)(struct dccg *dccg,
     87			uint32_t otg_inst);
     88	void (*otg_drop_pixel)(struct dccg *dccg,
     89			uint32_t otg_inst);
     90	void (*dccg_init)(struct dccg *dccg);
     91
     92	void (*set_dpstreamclk)(
     93			struct dccg *dccg,
     94			enum hdmistreamclk_source src,
     95			int otg_inst);
     96
     97	void (*enable_symclk32_se)(
     98			struct dccg *dccg,
     99			int hpo_se_inst,
    100			enum phyd32clk_clock_source phyd32clk);
    101
    102	void (*disable_symclk32_se)(
    103			struct dccg *dccg,
    104			int hpo_se_inst);
    105
    106	void (*enable_symclk32_le)(
    107			struct dccg *dccg,
    108			int hpo_le_inst,
    109			enum phyd32clk_clock_source phyd32clk);
    110
    111	void (*disable_symclk32_le)(
    112			struct dccg *dccg,
    113			int hpo_le_inst);
    114
    115	void (*set_physymclk)(
    116			struct dccg *dccg,
    117			int phy_inst,
    118			enum physymclk_clock_source clk_src,
    119			bool force_enable);
    120
    121	void (*set_dtbclk_dto)(
    122			struct dccg *dccg,
    123			struct dtbclk_dto_params *dto_params);
    124
    125	void (*set_audio_dtbclk_dto)(
    126			struct dccg *dccg,
    127			uint32_t req_audio_dtbclk_khz);
    128
    129	void (*set_dispclk_change_mode)(
    130			struct dccg *dccg,
    131			enum dentist_dispclk_change_mode change_mode);
    132
    133	void (*disable_dsc)(
    134		struct dccg *dccg,
    135		int inst);
    136
    137	void (*enable_dsc)(
    138		struct dccg *dccg,
    139		int inst);
    140
    141};
    142
    143#endif //__DAL_DCCG_H__