hw_sequencer.h (9630B)
1/* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#ifndef __DC_HW_SEQUENCER_H__ 27#define __DC_HW_SEQUENCER_H__ 28#include "dc_types.h" 29#include "clock_source.h" 30#include "inc/hw/timing_generator.h" 31#include "inc/hw/opp.h" 32#include "inc/hw/link_encoder.h" 33#include "core_status.h" 34 35enum vline_select { 36 VLINE0, 37 VLINE1 38}; 39 40struct pipe_ctx; 41struct dc_state; 42struct dc_stream_status; 43struct dc_writeback_info; 44struct dchub_init_data; 45struct dc_static_screen_params; 46struct resource_pool; 47struct dc_phy_addr_space_config; 48struct dc_virtual_addr_space_config; 49struct dpp; 50struct dce_hwseq; 51 52struct hw_sequencer_funcs { 53 void (*hardware_release)(struct dc *dc); 54 /* Embedded Display Related */ 55 void (*edp_power_control)(struct dc_link *link, bool enable); 56 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 57 void (*edp_wait_for_T12)(struct dc_link *link); 58 59 /* Pipe Programming Related */ 60 void (*init_hw)(struct dc *dc); 61 void (*power_down_on_boot)(struct dc *dc); 62 void (*enable_accelerated_mode)(struct dc *dc, 63 struct dc_state *context); 64 enum dc_status (*apply_ctx_to_hw)(struct dc *dc, 65 struct dc_state *context); 66 void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx); 67 void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank); 68 void (*apply_ctx_for_surface)(struct dc *dc, 69 const struct dc_stream_state *stream, 70 int num_planes, struct dc_state *context); 71 void (*program_front_end_for_ctx)(struct dc *dc, 72 struct dc_state *context); 73 void (*wait_for_pending_cleared)(struct dc *dc, 74 struct dc_state *context); 75 void (*post_unlock_program_front_end)(struct dc *dc, 76 struct dc_state *context); 77 void (*update_plane_addr)(const struct dc *dc, 78 struct pipe_ctx *pipe_ctx); 79 void (*update_dchub)(struct dce_hwseq *hws, 80 struct dchub_init_data *dh_data); 81 void (*wait_for_mpcc_disconnect)(struct dc *dc, 82 struct resource_pool *res_pool, 83 struct pipe_ctx *pipe_ctx); 84 void (*edp_backlight_control)( 85 struct dc_link *link, 86 bool enable); 87 void (*program_triplebuffer)(const struct dc *dc, 88 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 89 void (*update_pending_status)(struct pipe_ctx *pipe_ctx); 90 void (*power_down)(struct dc *dc); 91 92 /* Pipe Lock Related */ 93 void (*pipe_control_lock)(struct dc *dc, 94 struct pipe_ctx *pipe, bool lock); 95 void (*interdependent_update_lock)(struct dc *dc, 96 struct dc_state *context, bool lock); 97 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx, 98 bool flip_immediate); 99 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock); 100 101 /* Timing Related */ 102 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 103 struct crtc_position *position); 104 int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); 105 void (*calc_vupdate_position)( 106 struct dc *dc, 107 struct pipe_ctx *pipe_ctx, 108 uint32_t *start_line, 109 uint32_t *end_line); 110 void (*enable_per_frame_crtc_position_reset)(struct dc *dc, 111 int group_size, struct pipe_ctx *grouped_pipes[]); 112 void (*enable_timing_synchronization)(struct dc *dc, 113 int group_index, int group_size, 114 struct pipe_ctx *grouped_pipes[]); 115 void (*enable_vblanks_synchronization)(struct dc *dc, 116 int group_index, int group_size, 117 struct pipe_ctx *grouped_pipes[]); 118 void (*setup_periodic_interrupt)(struct dc *dc, 119 struct pipe_ctx *pipe_ctx, 120 enum vline_select vline); 121 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 122 struct dc_crtc_timing_adjust adjust); 123 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 124 int num_pipes, 125 const struct dc_static_screen_params *events); 126#ifndef TRIM_FSFT 127 bool (*optimize_timing_for_fsft)(struct dc *dc, 128 struct dc_crtc_timing *timing, 129 unsigned int max_input_rate_in_khz); 130#endif 131 132 /* Stream Related */ 133 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 134 void (*disable_stream)(struct pipe_ctx *pipe_ctx); 135 void (*blank_stream)(struct pipe_ctx *pipe_ctx); 136 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 137 struct dc_link_settings *link_settings); 138 139 /* Bandwidth Related */ 140 void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context); 141 bool (*update_bandwidth)(struct dc *dc, struct dc_state *context); 142 void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context); 143 144 /* Infopacket Related */ 145 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 146 void (*send_immediate_sdp_message)( 147 struct pipe_ctx *pipe_ctx, 148 const uint8_t *custom_sdp_message, 149 unsigned int sdp_message_size); 150 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 151 void (*set_dmdata_attributes)(struct pipe_ctx *pipe); 152 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); 153 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); 154 155 /* Cursor Related */ 156 void (*set_cursor_position)(struct pipe_ctx *pipe); 157 void (*set_cursor_attribute)(struct pipe_ctx *pipe); 158 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); 159 160 /* Colour Related */ 161 void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); 162 void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, 163 enum dc_color_space colorspace, 164 uint16_t *matrix, int opp_id); 165 166 /* VM Related */ 167 int (*init_sys_ctx)(struct dce_hwseq *hws, 168 struct dc *dc, 169 struct dc_phy_addr_space_config *pa_config); 170 void (*init_vm_ctx)(struct dce_hwseq *hws, 171 struct dc *dc, 172 struct dc_virtual_addr_space_config *va_config, 173 int vmid); 174 175 /* Writeback Related */ 176 void (*update_writeback)(struct dc *dc, 177 struct dc_writeback_info *wb_info, 178 struct dc_state *context); 179 void (*enable_writeback)(struct dc *dc, 180 struct dc_writeback_info *wb_info, 181 struct dc_state *context); 182 void (*disable_writeback)(struct dc *dc, 183 unsigned int dwb_pipe_inst); 184 185 bool (*mmhubbub_warmup)(struct dc *dc, 186 unsigned int num_dwb, 187 struct dc_writeback_info *wb_info); 188 189 /* Clock Related */ 190 enum dc_status (*set_clock)(struct dc *dc, 191 enum dc_clock_type clock_type, 192 uint32_t clk_khz, uint32_t stepping); 193 void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type, 194 struct dc_clock_config *clock_cfg); 195 void (*optimize_pwr_state)(const struct dc *dc, 196 struct dc_state *context); 197 void (*exit_optimized_pwr_state)(const struct dc *dc, 198 struct dc_state *context); 199 200 /* Audio Related */ 201 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); 202 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); 203 204 /* Stereo 3D Related */ 205 void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc); 206 207 /* HW State Logging Related */ 208 void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx); 209 void (*get_hw_state)(struct dc *dc, char *pBuf, 210 unsigned int bufSize, unsigned int mask); 211 void (*clear_status_bits)(struct dc *dc, unsigned int mask); 212 213 bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx, 214 uint32_t backlight_pwm_u16_16, 215 uint32_t frame_ramp); 216 217 void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx); 218 219 void (*set_pipe)(struct pipe_ctx *pipe_ctx); 220 221 void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits); 222 223 /* Idle Optimization Related */ 224 bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable); 225 226 bool (*does_plane_fit_in_mall)(struct dc *dc, struct dc_plane_state *plane, 227 struct dc_cursor_attributes *cursor_attr); 228 229 bool (*is_abm_supported)(struct dc *dc, 230 struct dc_state *context, struct dc_stream_state *stream); 231 232 void (*set_disp_pattern_generator)(const struct dc *dc, 233 struct pipe_ctx *pipe_ctx, 234 enum controller_dp_test_pattern test_pattern, 235 enum controller_dp_color_space color_space, 236 enum dc_color_depth color_depth, 237 const struct tg_color *solid_color, 238 int width, int height, int offset); 239 240 void (*z10_restore)(const struct dc *dc); 241 void (*z10_save_init)(struct dc *dc); 242 243 void (*update_visual_confirm_color)(struct dc *dc, 244 struct pipe_ctx *pipe_ctx, 245 struct tg_color *color, 246 int mpcc_id); 247}; 248 249void color_space_to_black_color( 250 const struct dc *dc, 251 enum dc_color_space colorspace, 252 struct tg_color *black_color); 253 254bool hwss_wait_for_blank_complete( 255 struct timing_generator *tg); 256 257const uint16_t *find_color_matrix( 258 enum dc_color_space color_space, 259 uint32_t *array_size); 260 261void get_surface_visual_confirm_color( 262 const struct pipe_ctx *pipe_ctx, 263 struct tg_color *color); 264 265void get_hdr_visual_confirm_color( 266 struct pipe_ctx *pipe_ctx, 267 struct tg_color *color); 268void get_mpctree_visual_confirm_color( 269 struct pipe_ctx *pipe_ctx, 270 struct tg_color *color); 271void get_surface_tile_visual_confirm_color( 272 struct pipe_ctx *pipe_ctx, 273 struct tg_color *color); 274#endif /* __DC_HW_SEQUENCER_H__ */