irq_service_dce110.c (13010B)
1/* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#include <linux/slab.h> 27 28#include "dm_services.h" 29 30#include "include/logger_interface.h" 31 32#include "irq_service_dce110.h" 33 34#include "dce/dce_11_0_d.h" 35#include "dce/dce_11_0_sh_mask.h" 36 37#include "ivsrcid/ivsrcid_vislands30.h" 38 39#include "dc.h" 40#include "core_types.h" 41#define DC_LOGGER \ 42 irq_service->ctx->logger 43 44static bool hpd_ack(struct irq_service *irq_service, 45 const struct irq_source_info *info) 46{ 47 uint32_t addr = info->status_reg; 48 uint32_t value = dm_read_reg(irq_service->ctx, addr); 49 uint32_t current_status = get_reg_field_value(value, 50 DC_HPD_INT_STATUS, 51 DC_HPD_SENSE_DELAYED); 52 53 dal_irq_service_ack_generic(irq_service, info); 54 55 value = dm_read_reg(irq_service->ctx, info->enable_reg); 56 57 set_reg_field_value(value, current_status ? 0 : 1, 58 DC_HPD_INT_CONTROL, 59 DC_HPD_INT_POLARITY); 60 61 dm_write_reg(irq_service->ctx, info->enable_reg, value); 62 63 return true; 64} 65 66static const struct irq_source_info_funcs hpd_irq_info_funcs = { 67 .set = NULL, 68 .ack = hpd_ack 69}; 70 71static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { 72 .set = NULL, 73 .ack = NULL 74}; 75 76static const struct irq_source_info_funcs pflip_irq_info_funcs = { 77 .set = NULL, 78 .ack = NULL 79}; 80 81static const struct irq_source_info_funcs vblank_irq_info_funcs = { 82 .set = dce110_vblank_set, 83 .ack = NULL 84}; 85 86static const struct irq_source_info_funcs vupdate_irq_info_funcs = { 87 .set = NULL, 88 .ack = NULL 89}; 90 91#define hpd_int_entry(reg_num)\ 92 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ 93 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\ 94 .enable_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\ 95 .enable_value = {\ 96 DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\ 97 ~DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK\ 98 },\ 99 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\ 100 .ack_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\ 101 .ack_value = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\ 102 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\ 103 .funcs = &hpd_irq_info_funcs\ 104 } 105 106#define hpd_rx_int_entry(reg_num)\ 107 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ 108 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\ 109 .enable_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\ 110 .enable_value = {\ 111 DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\ 112 ~DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK },\ 113 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\ 114 .ack_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\ 115 .ack_value = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\ 116 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\ 117 .funcs = &hpd_rx_irq_info_funcs\ 118 } 119#define pflip_int_entry(reg_num)\ 120 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 121 .enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\ 122 .enable_mask =\ 123 GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\ 124 .enable_value = {\ 125 GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\ 126 ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\ 127 .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\ 128 .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\ 129 .ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\ 130 .status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\ 131 .funcs = &pflip_irq_info_funcs\ 132 } 133 134#define vupdate_int_entry(reg_num)\ 135 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 136 .enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\ 137 .enable_mask =\ 138 CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\ 139 .enable_value = {\ 140 CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\ 141 ~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\ 142 .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\ 143 .ack_mask =\ 144 CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\ 145 .ack_value =\ 146 CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\ 147 .funcs = &vupdate_irq_info_funcs\ 148 } 149 150#define vblank_int_entry(reg_num)\ 151 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ 152 .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\ 153 .enable_mask =\ 154 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\ 155 .enable_value = {\ 156 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\ 157 ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\ 158 .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\ 159 .ack_mask =\ 160 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\ 161 .ack_value =\ 162 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\ 163 .funcs = &vblank_irq_info_funcs,\ 164 .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\ 165 } 166 167#define dummy_irq_entry() \ 168 {\ 169 .funcs = &dummy_irq_info_funcs\ 170 } 171 172#define i2c_int_entry(reg_num) \ 173 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() 174 175#define dp_sink_int_entry(reg_num) \ 176 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() 177 178#define gpio_pad_int_entry(reg_num) \ 179 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() 180 181#define dc_underflow_int_entry(reg_num) \ 182 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() 183 184bool dal_irq_service_dummy_set(struct irq_service *irq_service, 185 const struct irq_source_info *info, 186 bool enable) 187{ 188 DC_LOG_ERROR("%s: called for non-implemented irq source, src_id=%u, ext_id=%u\n", 189 __func__, info->src_id, info->ext_id); 190 191 return false; 192} 193 194bool dal_irq_service_dummy_ack(struct irq_service *irq_service, 195 const struct irq_source_info *info) 196{ 197 DC_LOG_ERROR("%s: called for non-implemented irq source, src_id=%u, ext_id=%u\n", 198 __func__, info->src_id, info->ext_id); 199 200 return false; 201} 202 203 204bool dce110_vblank_set(struct irq_service *irq_service, 205 const struct irq_source_info *info, 206 bool enable) 207{ 208 struct dc_context *dc_ctx = irq_service->ctx; 209 struct dc *dc = irq_service->ctx->dc; 210 enum dc_irq_source dal_irq_src = 211 dc_interrupt_to_irq_source(irq_service->ctx->dc, 212 info->src_id, 213 info->ext_id); 214 uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; 215 216 struct timing_generator *tg = 217 dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; 218 219 if (enable) { 220 if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) { 221 DC_ERROR("Failed to get VBLANK!\n"); 222 return false; 223 } 224 } 225 226 dal_irq_service_set_generic(irq_service, info, enable); 227 return true; 228} 229 230static const struct irq_source_info_funcs dummy_irq_info_funcs = { 231 .set = dal_irq_service_dummy_set, 232 .ack = dal_irq_service_dummy_ack 233}; 234 235static const struct irq_source_info 236irq_source_info_dce110[DAL_IRQ_SOURCES_NUMBER] = { 237 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), 238 hpd_int_entry(0), 239 hpd_int_entry(1), 240 hpd_int_entry(2), 241 hpd_int_entry(3), 242 hpd_int_entry(4), 243 hpd_int_entry(5), 244 hpd_rx_int_entry(0), 245 hpd_rx_int_entry(1), 246 hpd_rx_int_entry(2), 247 hpd_rx_int_entry(3), 248 hpd_rx_int_entry(4), 249 hpd_rx_int_entry(5), 250 i2c_int_entry(1), 251 i2c_int_entry(2), 252 i2c_int_entry(3), 253 i2c_int_entry(4), 254 i2c_int_entry(5), 255 i2c_int_entry(6), 256 dp_sink_int_entry(1), 257 dp_sink_int_entry(2), 258 dp_sink_int_entry(3), 259 dp_sink_int_entry(4), 260 dp_sink_int_entry(5), 261 dp_sink_int_entry(6), 262 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), 263 pflip_int_entry(0), 264 pflip_int_entry(1), 265 pflip_int_entry(2), 266 pflip_int_entry(3), 267 pflip_int_entry(4), 268 pflip_int_entry(5), 269 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), 270 gpio_pad_int_entry(0), 271 gpio_pad_int_entry(1), 272 gpio_pad_int_entry(2), 273 gpio_pad_int_entry(3), 274 gpio_pad_int_entry(4), 275 gpio_pad_int_entry(5), 276 gpio_pad_int_entry(6), 277 gpio_pad_int_entry(7), 278 gpio_pad_int_entry(8), 279 gpio_pad_int_entry(9), 280 gpio_pad_int_entry(10), 281 gpio_pad_int_entry(11), 282 gpio_pad_int_entry(12), 283 gpio_pad_int_entry(13), 284 gpio_pad_int_entry(14), 285 gpio_pad_int_entry(15), 286 gpio_pad_int_entry(16), 287 gpio_pad_int_entry(17), 288 gpio_pad_int_entry(18), 289 gpio_pad_int_entry(19), 290 gpio_pad_int_entry(20), 291 gpio_pad_int_entry(21), 292 gpio_pad_int_entry(22), 293 gpio_pad_int_entry(23), 294 gpio_pad_int_entry(24), 295 gpio_pad_int_entry(25), 296 gpio_pad_int_entry(26), 297 gpio_pad_int_entry(27), 298 gpio_pad_int_entry(28), 299 gpio_pad_int_entry(29), 300 gpio_pad_int_entry(30), 301 dc_underflow_int_entry(1), 302 dc_underflow_int_entry(2), 303 dc_underflow_int_entry(3), 304 dc_underflow_int_entry(4), 305 dc_underflow_int_entry(5), 306 dc_underflow_int_entry(6), 307 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), 308 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), 309 vupdate_int_entry(0), 310 vupdate_int_entry(1), 311 vupdate_int_entry(2), 312 vupdate_int_entry(3), 313 vupdate_int_entry(4), 314 vupdate_int_entry(5), 315 vblank_int_entry(0), 316 vblank_int_entry(1), 317 vblank_int_entry(2), 318 vblank_int_entry(3), 319 vblank_int_entry(4), 320 vblank_int_entry(5), 321 322}; 323 324enum dc_irq_source to_dal_irq_source_dce110( 325 struct irq_service *irq_service, 326 uint32_t src_id, 327 uint32_t ext_id) 328{ 329 switch (src_id) { 330 case VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0: 331 return DC_IRQ_SOURCE_VBLANK1; 332 case VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0: 333 return DC_IRQ_SOURCE_VBLANK2; 334 case VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0: 335 return DC_IRQ_SOURCE_VBLANK3; 336 case VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0: 337 return DC_IRQ_SOURCE_VBLANK4; 338 case VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0: 339 return DC_IRQ_SOURCE_VBLANK5; 340 case VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0: 341 return DC_IRQ_SOURCE_VBLANK6; 342 case VISLANDS30_IV_SRCID_D1_V_UPDATE_INT: 343 return DC_IRQ_SOURCE_VUPDATE1; 344 case VISLANDS30_IV_SRCID_D2_V_UPDATE_INT: 345 return DC_IRQ_SOURCE_VUPDATE2; 346 case VISLANDS30_IV_SRCID_D3_V_UPDATE_INT: 347 return DC_IRQ_SOURCE_VUPDATE3; 348 case VISLANDS30_IV_SRCID_D4_V_UPDATE_INT: 349 return DC_IRQ_SOURCE_VUPDATE4; 350 case VISLANDS30_IV_SRCID_D5_V_UPDATE_INT: 351 return DC_IRQ_SOURCE_VUPDATE5; 352 case VISLANDS30_IV_SRCID_D6_V_UPDATE_INT: 353 return DC_IRQ_SOURCE_VUPDATE6; 354 case VISLANDS30_IV_SRCID_D1_GRPH_PFLIP: 355 return DC_IRQ_SOURCE_PFLIP1; 356 case VISLANDS30_IV_SRCID_D2_GRPH_PFLIP: 357 return DC_IRQ_SOURCE_PFLIP2; 358 case VISLANDS30_IV_SRCID_D3_GRPH_PFLIP: 359 return DC_IRQ_SOURCE_PFLIP3; 360 case VISLANDS30_IV_SRCID_D4_GRPH_PFLIP: 361 return DC_IRQ_SOURCE_PFLIP4; 362 case VISLANDS30_IV_SRCID_D5_GRPH_PFLIP: 363 return DC_IRQ_SOURCE_PFLIP5; 364 case VISLANDS30_IV_SRCID_D6_GRPH_PFLIP: 365 return DC_IRQ_SOURCE_PFLIP6; 366 367 case VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A: 368 /* generic src_id for all HPD and HPDRX interrupts */ 369 switch (ext_id) { 370 case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A: 371 return DC_IRQ_SOURCE_HPD1; 372 case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B: 373 return DC_IRQ_SOURCE_HPD2; 374 case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C: 375 return DC_IRQ_SOURCE_HPD3; 376 case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D: 377 return DC_IRQ_SOURCE_HPD4; 378 case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E: 379 return DC_IRQ_SOURCE_HPD5; 380 case VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F: 381 return DC_IRQ_SOURCE_HPD6; 382 case VISLANDS30_IV_EXTID_HPD_RX_A: 383 return DC_IRQ_SOURCE_HPD1RX; 384 case VISLANDS30_IV_EXTID_HPD_RX_B: 385 return DC_IRQ_SOURCE_HPD2RX; 386 case VISLANDS30_IV_EXTID_HPD_RX_C: 387 return DC_IRQ_SOURCE_HPD3RX; 388 case VISLANDS30_IV_EXTID_HPD_RX_D: 389 return DC_IRQ_SOURCE_HPD4RX; 390 case VISLANDS30_IV_EXTID_HPD_RX_E: 391 return DC_IRQ_SOURCE_HPD5RX; 392 case VISLANDS30_IV_EXTID_HPD_RX_F: 393 return DC_IRQ_SOURCE_HPD6RX; 394 default: 395 return DC_IRQ_SOURCE_INVALID; 396 } 397 break; 398 399 default: 400 return DC_IRQ_SOURCE_INVALID; 401 } 402} 403 404static const struct irq_service_funcs irq_service_funcs_dce110 = { 405 .to_dal_irq_source = to_dal_irq_source_dce110 406}; 407 408static void dce110_irq_construct(struct irq_service *irq_service, 409 struct irq_service_init_data *init_data) 410{ 411 dal_irq_service_construct(irq_service, init_data); 412 413 irq_service->info = irq_source_info_dce110; 414 irq_service->funcs = &irq_service_funcs_dce110; 415} 416 417struct irq_service * 418dal_irq_service_dce110_create(struct irq_service_init_data *init_data) 419{ 420 struct irq_service *irq_service = kzalloc(sizeof(*irq_service), 421 GFP_KERNEL); 422 423 if (!irq_service) 424 return NULL; 425 426 dce110_irq_construct(irq_service, init_data); 427 return irq_service; 428}