irq_service_dcn30.c (13039B)
1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25#include "dm_services.h" 26 27#include "include/logger_interface.h" 28 29#include "../dce110/irq_service_dce110.h" 30 31 32#include "sienna_cichlid_ip_offset.h" 33#include "dcn/dcn_3_0_0_offset.h" 34#include "dcn/dcn_3_0_0_sh_mask.h" 35 36#include "nbio/nbio_7_4_offset.h" 37 38#include "dpcs/dpcs_3_0_0_offset.h" 39#include "dpcs/dpcs_3_0_0_sh_mask.h" 40 41#include "mmhub/mmhub_2_0_0_offset.h" 42#include "mmhub/mmhub_2_0_0_sh_mask.h" 43 44#include "irq_service_dcn30.h" 45 46#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 47 48static enum dc_irq_source to_dal_irq_source_dcn30( 49 struct irq_service *irq_service, 50 uint32_t src_id, 51 uint32_t ext_id) 52{ 53 switch (src_id) { 54 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 55 return DC_IRQ_SOURCE_VBLANK1; 56 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: 57 return DC_IRQ_SOURCE_VBLANK2; 58 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: 59 return DC_IRQ_SOURCE_VBLANK3; 60 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: 61 return DC_IRQ_SOURCE_VBLANK4; 62 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: 63 return DC_IRQ_SOURCE_VBLANK5; 64 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: 65 return DC_IRQ_SOURCE_VBLANK6; 66 case DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT: 67 return DC_IRQ_SOURCE_DMCUB_OUTBOX0; 68 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: 69 return DC_IRQ_SOURCE_DC1_VLINE0; 70 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: 71 return DC_IRQ_SOURCE_DC2_VLINE0; 72 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL: 73 return DC_IRQ_SOURCE_DC3_VLINE0; 74 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL: 75 return DC_IRQ_SOURCE_DC4_VLINE0; 76 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL: 77 return DC_IRQ_SOURCE_DC5_VLINE0; 78 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL: 79 return DC_IRQ_SOURCE_DC6_VLINE0; 80 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: 81 return DC_IRQ_SOURCE_PFLIP1; 82 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: 83 return DC_IRQ_SOURCE_PFLIP2; 84 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: 85 return DC_IRQ_SOURCE_PFLIP3; 86 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: 87 return DC_IRQ_SOURCE_PFLIP4; 88 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: 89 return DC_IRQ_SOURCE_PFLIP5; 90 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: 91 return DC_IRQ_SOURCE_PFLIP6; 92 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 93 return DC_IRQ_SOURCE_VUPDATE1; 94 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 95 return DC_IRQ_SOURCE_VUPDATE2; 96 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 97 return DC_IRQ_SOURCE_VUPDATE3; 98 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 99 return DC_IRQ_SOURCE_VUPDATE4; 100 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 101 return DC_IRQ_SOURCE_VUPDATE5; 102 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 103 return DC_IRQ_SOURCE_VUPDATE6; 104 105 case DCN_1_0__SRCID__DC_HPD1_INT: 106 /* generic src_id for all HPD and HPDRX interrupts */ 107 switch (ext_id) { 108 case DCN_1_0__CTXID__DC_HPD1_INT: 109 return DC_IRQ_SOURCE_HPD1; 110 case DCN_1_0__CTXID__DC_HPD2_INT: 111 return DC_IRQ_SOURCE_HPD2; 112 case DCN_1_0__CTXID__DC_HPD3_INT: 113 return DC_IRQ_SOURCE_HPD3; 114 case DCN_1_0__CTXID__DC_HPD4_INT: 115 return DC_IRQ_SOURCE_HPD4; 116 case DCN_1_0__CTXID__DC_HPD5_INT: 117 return DC_IRQ_SOURCE_HPD5; 118 case DCN_1_0__CTXID__DC_HPD6_INT: 119 return DC_IRQ_SOURCE_HPD6; 120 case DCN_1_0__CTXID__DC_HPD1_RX_INT: 121 return DC_IRQ_SOURCE_HPD1RX; 122 case DCN_1_0__CTXID__DC_HPD2_RX_INT: 123 return DC_IRQ_SOURCE_HPD2RX; 124 case DCN_1_0__CTXID__DC_HPD3_RX_INT: 125 return DC_IRQ_SOURCE_HPD3RX; 126 case DCN_1_0__CTXID__DC_HPD4_RX_INT: 127 return DC_IRQ_SOURCE_HPD4RX; 128 case DCN_1_0__CTXID__DC_HPD5_RX_INT: 129 return DC_IRQ_SOURCE_HPD5RX; 130 case DCN_1_0__CTXID__DC_HPD6_RX_INT: 131 return DC_IRQ_SOURCE_HPD6RX; 132 default: 133 return DC_IRQ_SOURCE_INVALID; 134 } 135 break; 136 137 default: 138 return DC_IRQ_SOURCE_INVALID; 139 } 140} 141 142static bool hpd_ack( 143 struct irq_service *irq_service, 144 const struct irq_source_info *info) 145{ 146 uint32_t addr = info->status_reg; 147 uint32_t value = dm_read_reg(irq_service->ctx, addr); 148 uint32_t current_status = 149 get_reg_field_value( 150 value, 151 HPD0_DC_HPD_INT_STATUS, 152 DC_HPD_SENSE_DELAYED); 153 154 dal_irq_service_ack_generic(irq_service, info); 155 156 value = dm_read_reg(irq_service->ctx, info->enable_reg); 157 158 set_reg_field_value( 159 value, 160 current_status ? 0 : 1, 161 HPD0_DC_HPD_INT_CONTROL, 162 DC_HPD_INT_POLARITY); 163 164 dm_write_reg(irq_service->ctx, info->enable_reg, value); 165 166 return true; 167} 168 169static const struct irq_source_info_funcs hpd_irq_info_funcs = { 170 .set = NULL, 171 .ack = hpd_ack 172}; 173 174static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { 175 .set = NULL, 176 .ack = NULL 177}; 178 179static const struct irq_source_info_funcs pflip_irq_info_funcs = { 180 .set = NULL, 181 .ack = NULL 182}; 183 184static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { 185 .set = NULL, 186 .ack = NULL 187}; 188 189static const struct irq_source_info_funcs vblank_irq_info_funcs = { 190 .set = NULL, 191 .ack = NULL 192}; 193 194static const struct irq_source_info_funcs dmub_trace_irq_info_funcs = { 195 .set = NULL, 196 .ack = NULL 197}; 198 199static const struct irq_source_info_funcs vline0_irq_info_funcs = { 200 .set = NULL, 201 .ack = NULL 202}; 203 204#undef BASE_INNER 205#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 206 207/* compile time expand base address. */ 208#define BASE(seg) \ 209 BASE_INNER(seg) 210 211 212#define SRI(reg_name, block, id)\ 213 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 214 mm ## block ## id ## _ ## reg_name 215 216#define SRI_DMUB(reg_name)\ 217 BASE(mm ## reg_name ## _BASE_IDX) + \ 218 mm ## reg_name 219 220#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 221 .enable_reg = SRI(reg1, block, reg_num),\ 222 .enable_mask = \ 223 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 224 .enable_value = {\ 225 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 226 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 227 },\ 228 .ack_reg = SRI(reg2, block, reg_num),\ 229 .ack_mask = \ 230 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 231 .ack_value = \ 232 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 233 234#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ 235 .enable_reg = SRI_DMUB(reg1),\ 236 .enable_mask = \ 237 reg1 ## __ ## mask1 ## _MASK,\ 238 .enable_value = {\ 239 reg1 ## __ ## mask1 ## _MASK,\ 240 ~reg1 ## __ ## mask1 ## _MASK \ 241 },\ 242 .ack_reg = SRI_DMUB(reg2),\ 243 .ack_mask = \ 244 reg2 ## __ ## mask2 ## _MASK,\ 245 .ack_value = \ 246 reg2 ## __ ## mask2 ## _MASK \ 247 248#define hpd_int_entry(reg_num)\ 249 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ 250 IRQ_REG_ENTRY(HPD, reg_num,\ 251 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ 252 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ 253 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 254 .funcs = &hpd_irq_info_funcs\ 255 } 256 257#define hpd_rx_int_entry(reg_num)\ 258 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ 259 IRQ_REG_ENTRY(HPD, reg_num,\ 260 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ 261 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ 262 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 263 .funcs = &hpd_rx_irq_info_funcs\ 264 } 265#define pflip_int_entry(reg_num)\ 266 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 267 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 268 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ 269 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ 270 .funcs = &pflip_irq_info_funcs\ 271 } 272 273/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic 274 * of DCE's DC_IRQ_SOURCE_VUPDATEx. 275 */ 276#define vupdate_no_lock_int_entry(reg_num)\ 277 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 278 IRQ_REG_ENTRY(OTG, reg_num,\ 279 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ 280 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ 281 .funcs = &vupdate_no_lock_irq_info_funcs\ 282 } 283 284#define vblank_int_entry(reg_num)\ 285 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ 286 IRQ_REG_ENTRY(OTG, reg_num,\ 287 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ 288 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ 289 .funcs = &vblank_irq_info_funcs\ 290 } 291 292#define vline0_int_entry(reg_num)\ 293 [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\ 294 IRQ_REG_ENTRY(OTG, reg_num,\ 295 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\ 296 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\ 297 .funcs = &vline0_irq_info_funcs\ 298 } 299 300#define dmub_trace_int_entry()\ 301 [DC_IRQ_SOURCE_DMCUB_OUTBOX0] = {\ 302 IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX0_READY_INT_EN,\ 303 DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX0_READY_INT_ACK),\ 304 .funcs = &dmub_trace_irq_info_funcs\ 305 } 306 307#define dummy_irq_entry() \ 308 {\ 309 .funcs = &dummy_irq_info_funcs\ 310 } 311 312#define i2c_int_entry(reg_num) \ 313 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() 314 315#define dp_sink_int_entry(reg_num) \ 316 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() 317 318#define gpio_pad_int_entry(reg_num) \ 319 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() 320 321#define dc_underflow_int_entry(reg_num) \ 322 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() 323 324static const struct irq_source_info_funcs dummy_irq_info_funcs = { 325 .set = dal_irq_service_dummy_set, 326 .ack = dal_irq_service_dummy_ack 327}; 328 329static const struct irq_source_info 330irq_source_info_dcn30[DAL_IRQ_SOURCES_NUMBER] = { 331 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), 332 hpd_int_entry(0), 333 hpd_int_entry(1), 334 hpd_int_entry(2), 335 hpd_int_entry(3), 336 hpd_int_entry(4), 337 hpd_int_entry(5), 338 hpd_rx_int_entry(0), 339 hpd_rx_int_entry(1), 340 hpd_rx_int_entry(2), 341 hpd_rx_int_entry(3), 342 hpd_rx_int_entry(4), 343 hpd_rx_int_entry(5), 344 i2c_int_entry(1), 345 i2c_int_entry(2), 346 i2c_int_entry(3), 347 i2c_int_entry(4), 348 i2c_int_entry(5), 349 i2c_int_entry(6), 350 dp_sink_int_entry(1), 351 dp_sink_int_entry(2), 352 dp_sink_int_entry(3), 353 dp_sink_int_entry(4), 354 dp_sink_int_entry(5), 355 dp_sink_int_entry(6), 356 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), 357 pflip_int_entry(0), 358 pflip_int_entry(1), 359 pflip_int_entry(2), 360 pflip_int_entry(3), 361 pflip_int_entry(4), 362 pflip_int_entry(5), 363 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), 364 gpio_pad_int_entry(0), 365 gpio_pad_int_entry(1), 366 gpio_pad_int_entry(2), 367 gpio_pad_int_entry(3), 368 gpio_pad_int_entry(4), 369 gpio_pad_int_entry(5), 370 gpio_pad_int_entry(6), 371 gpio_pad_int_entry(7), 372 gpio_pad_int_entry(8), 373 gpio_pad_int_entry(9), 374 gpio_pad_int_entry(10), 375 gpio_pad_int_entry(11), 376 gpio_pad_int_entry(12), 377 gpio_pad_int_entry(13), 378 gpio_pad_int_entry(14), 379 gpio_pad_int_entry(15), 380 gpio_pad_int_entry(16), 381 gpio_pad_int_entry(17), 382 gpio_pad_int_entry(18), 383 gpio_pad_int_entry(19), 384 gpio_pad_int_entry(20), 385 gpio_pad_int_entry(21), 386 gpio_pad_int_entry(22), 387 gpio_pad_int_entry(23), 388 gpio_pad_int_entry(24), 389 gpio_pad_int_entry(25), 390 gpio_pad_int_entry(26), 391 gpio_pad_int_entry(27), 392 gpio_pad_int_entry(28), 393 gpio_pad_int_entry(29), 394 gpio_pad_int_entry(30), 395 dc_underflow_int_entry(1), 396 dc_underflow_int_entry(2), 397 dc_underflow_int_entry(3), 398 dc_underflow_int_entry(4), 399 dc_underflow_int_entry(5), 400 dc_underflow_int_entry(6), 401 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), 402 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), 403 vupdate_no_lock_int_entry(0), 404 vupdate_no_lock_int_entry(1), 405 vupdate_no_lock_int_entry(2), 406 vupdate_no_lock_int_entry(3), 407 vupdate_no_lock_int_entry(4), 408 vupdate_no_lock_int_entry(5), 409 vblank_int_entry(0), 410 vblank_int_entry(1), 411 vblank_int_entry(2), 412 vblank_int_entry(3), 413 vblank_int_entry(4), 414 vblank_int_entry(5), 415 vline0_int_entry(0), 416 vline0_int_entry(1), 417 vline0_int_entry(2), 418 vline0_int_entry(3), 419 vline0_int_entry(4), 420 vline0_int_entry(5), 421 dmub_trace_int_entry(), 422}; 423 424static const struct irq_service_funcs irq_service_funcs_dcn30 = { 425 .to_dal_irq_source = to_dal_irq_source_dcn30 426}; 427 428static void dcn30_irq_construct( 429 struct irq_service *irq_service, 430 struct irq_service_init_data *init_data) 431{ 432 dal_irq_service_construct(irq_service, init_data); 433 434 irq_service->info = irq_source_info_dcn30; 435 irq_service->funcs = &irq_service_funcs_dcn30; 436} 437 438struct irq_service *dal_irq_service_dcn30_create( 439 struct irq_service_init_data *init_data) 440{ 441 struct irq_service *irq_service = kzalloc(sizeof(*irq_service), 442 GFP_KERNEL); 443 444 if (!irq_service) 445 return NULL; 446 447 dcn30_irq_construct(irq_service, init_data); 448 return irq_service; 449} 450