cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dmub_trace_buffer.h (2082B)

      1/*
      2 * Copyright 2019 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: AMD
     23 *
     24 */
     25#ifndef _DMUB_TRACE_BUFFER_H_
     26#define _DMUB_TRACE_BUFFER_H_
     27
     28#include "dmub_cmd.h"
     29
     30#define LOAD_DMCU_FW	1
     31#define LOAD_PHY_FW	2
     32
     33
     34enum dmucb_trace_code {
     35	DMCUB__UNKNOWN,
     36	DMCUB__MAIN_BEGIN,
     37	DMCUB__PHY_INIT_BEGIN,
     38	DMCUB__PHY_FW_SRAM_LOAD_BEGIN,
     39	DMCUB__PHY_FW_SRAM_LOAD_END,
     40	DMCUB__PHY_INIT_POLL_DONE,
     41	DMCUB__PHY_INIT_END,
     42	DMCUB__DMCU_ERAM_LOAD_BEGIN,
     43	DMCUB__DMCU_ERAM_LOAD_END,
     44	DMCUB__DMCU_ISR_LOAD_BEGIN,
     45	DMCUB__DMCU_ISR_LOAD_END,
     46	DMCUB__MAIN_IDLE,
     47	DMCUB__PERF_TRACE,
     48	DMCUB__PG_DONE,
     49};
     50
     51struct dmcub_trace_buf_entry {
     52	enum dmucb_trace_code trace_code;
     53	uint32_t tick_count;
     54	uint32_t param0;
     55	uint32_t param1;
     56};
     57
     58#define TRACE_BUF_SIZE (1024) //1 kB
     59#define PERF_TRACE_MAX_ENTRY ((TRACE_BUF_SIZE - 8)/sizeof(struct dmcub_trace_buf_entry))
     60
     61
     62struct dmcub_trace_buf {
     63	uint32_t entry_count;
     64	uint32_t clk_freq;
     65	struct dmcub_trace_buf_entry entries[PERF_TRACE_MAX_ENTRY];
     66};
     67
     68#endif /* _DMUB_TRACE_BUFFER_H_ */