atomfirmware.h (162509B)
1/****************************************************************************\ 2* 3* File Name atomfirmware.h 4* Project This is an interface header file between atombios and OS GPU drivers for SoC15 products 5* 6* Description header file of general definitions for OS and pre-OS video drivers 7* 8* Copyright 2014 Advanced Micro Devices, Inc. 9* 10* Permission is hereby granted, free of charge, to any person obtaining a copy of this software 11* and associated documentation files (the "Software"), to deal in the Software without restriction, 12* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, 13* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, 14* subject to the following conditions: 15* 16* The above copyright notice and this permission notice shall be included in all copies or substantial 17* portions of the Software. 18* 19* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 23* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25* OTHER DEALINGS IN THE SOFTWARE. 26* 27\****************************************************************************/ 28 29/*IMPORTANT NOTES 30* If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file. 31* If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file. 32* If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h. 33*/ 34 35#ifndef _ATOMFIRMWARE_H_ 36#define _ATOMFIRMWARE_H_ 37 38enum atom_bios_header_version_def{ 39 ATOM_MAJOR_VERSION =0x0003, 40 ATOM_MINOR_VERSION =0x0003, 41}; 42 43#ifdef _H2INC 44 #ifndef uint32_t 45 typedef unsigned long uint32_t; 46 #endif 47 48 #ifndef uint16_t 49 typedef unsigned short uint16_t; 50 #endif 51 52 #ifndef uint8_t 53 typedef unsigned char uint8_t; 54 #endif 55#endif 56 57enum atom_crtc_def{ 58 ATOM_CRTC1 =0, 59 ATOM_CRTC2 =1, 60 ATOM_CRTC3 =2, 61 ATOM_CRTC4 =3, 62 ATOM_CRTC5 =4, 63 ATOM_CRTC6 =5, 64 ATOM_CRTC_INVALID =0xff, 65}; 66 67enum atom_ppll_def{ 68 ATOM_PPLL0 =2, 69 ATOM_GCK_DFS =8, 70 ATOM_FCH_CLK =9, 71 ATOM_DP_DTO =11, 72 ATOM_COMBOPHY_PLL0 =20, 73 ATOM_COMBOPHY_PLL1 =21, 74 ATOM_COMBOPHY_PLL2 =22, 75 ATOM_COMBOPHY_PLL3 =23, 76 ATOM_COMBOPHY_PLL4 =24, 77 ATOM_COMBOPHY_PLL5 =25, 78 ATOM_PPLL_INVALID =0xff, 79}; 80 81// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel 82enum atom_dig_def{ 83 ASIC_INT_DIG1_ENCODER_ID =0x03, 84 ASIC_INT_DIG2_ENCODER_ID =0x09, 85 ASIC_INT_DIG3_ENCODER_ID =0x0a, 86 ASIC_INT_DIG4_ENCODER_ID =0x0b, 87 ASIC_INT_DIG5_ENCODER_ID =0x0c, 88 ASIC_INT_DIG6_ENCODER_ID =0x0d, 89 ASIC_INT_DIG7_ENCODER_ID =0x0e, 90}; 91 92//ucEncoderMode 93enum atom_encode_mode_def 94{ 95 ATOM_ENCODER_MODE_DP =0, 96 ATOM_ENCODER_MODE_DP_SST =0, 97 ATOM_ENCODER_MODE_LVDS =1, 98 ATOM_ENCODER_MODE_DVI =2, 99 ATOM_ENCODER_MODE_HDMI =3, 100 ATOM_ENCODER_MODE_DP_AUDIO =5, 101 ATOM_ENCODER_MODE_DP_MST =5, 102 ATOM_ENCODER_MODE_CRT =15, 103 ATOM_ENCODER_MODE_DVO =16, 104}; 105 106enum atom_encoder_refclk_src_def{ 107 ENCODER_REFCLK_SRC_P1PLL =0, 108 ENCODER_REFCLK_SRC_P2PLL =1, 109 ENCODER_REFCLK_SRC_P3PLL =2, 110 ENCODER_REFCLK_SRC_EXTCLK =3, 111 ENCODER_REFCLK_SRC_INVALID =0xff, 112}; 113 114enum atom_scaler_def{ 115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/ 116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication 117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/ 118}; 119 120enum atom_operation_def{ 121 ATOM_DISABLE = 0, 122 ATOM_ENABLE = 1, 123 ATOM_INIT = 7, 124 ATOM_GET_STATUS = 8, 125}; 126 127enum atom_embedded_display_op_def{ 128 ATOM_LCD_BL_OFF = 2, 129 ATOM_LCD_BL_OM = 3, 130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4, 131 ATOM_LCD_SELFTEST_START = 5, 132 ATOM_LCD_SELFTEST_STOP = 6, 133}; 134 135enum atom_spread_spectrum_mode{ 136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01, 137 ATOM_SS_DOWN_SPREAD_MODE = 0x00, 138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01, 139 ATOM_INT_OR_EXT_SS_MASK = 0x02, 140 ATOM_INTERNAL_SS_MASK = 0x00, 141 ATOM_EXTERNAL_SS_MASK = 0x02, 142}; 143 144/* define panel bit per color */ 145enum atom_panel_bit_per_color{ 146 PANEL_BPC_UNDEFINE =0x00, 147 PANEL_6BIT_PER_COLOR =0x01, 148 PANEL_8BIT_PER_COLOR =0x02, 149 PANEL_10BIT_PER_COLOR =0x03, 150 PANEL_12BIT_PER_COLOR =0x04, 151 PANEL_16BIT_PER_COLOR =0x05, 152}; 153 154//ucVoltageType 155enum atom_voltage_type 156{ 157 VOLTAGE_TYPE_VDDC = 1, 158 VOLTAGE_TYPE_MVDDC = 2, 159 VOLTAGE_TYPE_MVDDQ = 3, 160 VOLTAGE_TYPE_VDDCI = 4, 161 VOLTAGE_TYPE_VDDGFX = 5, 162 VOLTAGE_TYPE_PCC = 6, 163 VOLTAGE_TYPE_MVPP = 7, 164 VOLTAGE_TYPE_LEDDPM = 8, 165 VOLTAGE_TYPE_PCC_MVDD = 9, 166 VOLTAGE_TYPE_PCIE_VDDC = 10, 167 VOLTAGE_TYPE_PCIE_VDDR = 11, 168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11, 169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12, 170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13, 171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14, 172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15, 173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16, 174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17, 175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18, 176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19, 177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A, 178}; 179 180enum atom_dgpu_vram_type { 181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50, 182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60, 183 ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61, 184 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70, 185}; 186 187enum atom_dp_vs_preemph_def{ 188 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00, 189 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01, 190 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02, 191 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03, 192 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08, 193 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09, 194 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a, 195 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10, 196 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11, 197 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18, 198}; 199 200#define BIOS_ATOM_PREFIX "ATOMBIOS" 201#define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD" 202#define BIOS_STRING_LENGTH 43 203 204/* 205enum atom_string_def{ 206asic_bus_type_pcie_string = "PCI_EXPRESS", 207atom_fire_gl_string = "FGL", 208atom_bios_string = "ATOM" 209}; 210*/ 211 212#pragma pack(1) /* BIOS data must use byte aligment*/ 213 214enum atombios_image_offset{ 215 OFFSET_TO_ATOM_ROM_HEADER_POINTER = 0x00000048, 216 OFFSET_TO_ATOM_ROM_IMAGE_SIZE = 0x00000002, 217 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE = 0x94, 218 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE = 20, /*including the terminator 0x0!*/ 219 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS = 0x2f, 220 OFFSET_TO_GET_ATOMBIOS_STRING_START = 0x6e, 221 OFFSET_TO_VBIOS_PART_NUMBER = 0x80, 222 OFFSET_TO_VBIOS_DATE = 0x50, 223}; 224 225/**************************************************************************** 226* Common header for all tables (Data table, Command function). 227* Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. 228* And the pointer actually points to this header. 229****************************************************************************/ 230 231struct atom_common_table_header 232{ 233 uint16_t structuresize; 234 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible 235 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change 236}; 237 238/**************************************************************************** 239* Structure stores the ROM header. 240****************************************************************************/ 241struct atom_rom_header_v2_2 242{ 243 struct atom_common_table_header table_header; 244 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, 245 uint16_t bios_segment_address; 246 uint16_t protectedmodeoffset; 247 uint16_t configfilenameoffset; 248 uint16_t crc_block_offset; 249 uint16_t vbios_bootupmessageoffset; 250 uint16_t int10_offset; 251 uint16_t pcibusdevinitcode; 252 uint16_t iobaseaddress; 253 uint16_t subsystem_vendor_id; 254 uint16_t subsystem_id; 255 uint16_t pci_info_offset; 256 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position 257 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position 258 uint16_t reserved; 259 uint32_t pspdirtableoffset; 260}; 261 262/*==============================hw function portion======================================================================*/ 263 264 265/**************************************************************************** 266* Structures used in Command.mtb, each function name is not given here since those function could change from time to time 267* The real functionality of each function is associated with the parameter structure version when defined 268* For all internal cmd function definitions, please reference to atomstruct.h 269****************************************************************************/ 270struct atom_master_list_of_command_functions_v2_1{ 271 uint16_t asic_init; //Function 272 uint16_t cmd_function1; //used as an internal one 273 uint16_t cmd_function2; //used as an internal one 274 uint16_t cmd_function3; //used as an internal one 275 uint16_t digxencodercontrol; //Function 276 uint16_t cmd_function5; //used as an internal one 277 uint16_t cmd_function6; //used as an internal one 278 uint16_t cmd_function7; //used as an internal one 279 uint16_t cmd_function8; //used as an internal one 280 uint16_t cmd_function9; //used as an internal one 281 uint16_t setengineclock; //Function 282 uint16_t setmemoryclock; //Function 283 uint16_t setpixelclock; //Function 284 uint16_t enabledisppowergating; //Function 285 uint16_t cmd_function14; //used as an internal one 286 uint16_t cmd_function15; //used as an internal one 287 uint16_t cmd_function16; //used as an internal one 288 uint16_t cmd_function17; //used as an internal one 289 uint16_t cmd_function18; //used as an internal one 290 uint16_t cmd_function19; //used as an internal one 291 uint16_t cmd_function20; //used as an internal one 292 uint16_t cmd_function21; //used as an internal one 293 uint16_t cmd_function22; //used as an internal one 294 uint16_t cmd_function23; //used as an internal one 295 uint16_t cmd_function24; //used as an internal one 296 uint16_t cmd_function25; //used as an internal one 297 uint16_t cmd_function26; //used as an internal one 298 uint16_t cmd_function27; //used as an internal one 299 uint16_t cmd_function28; //used as an internal one 300 uint16_t cmd_function29; //used as an internal one 301 uint16_t cmd_function30; //used as an internal one 302 uint16_t cmd_function31; //used as an internal one 303 uint16_t cmd_function32; //used as an internal one 304 uint16_t cmd_function33; //used as an internal one 305 uint16_t blankcrtc; //Function 306 uint16_t enablecrtc; //Function 307 uint16_t cmd_function36; //used as an internal one 308 uint16_t cmd_function37; //used as an internal one 309 uint16_t cmd_function38; //used as an internal one 310 uint16_t cmd_function39; //used as an internal one 311 uint16_t cmd_function40; //used as an internal one 312 uint16_t getsmuclockinfo; //Function 313 uint16_t selectcrtc_source; //Function 314 uint16_t cmd_function43; //used as an internal one 315 uint16_t cmd_function44; //used as an internal one 316 uint16_t cmd_function45; //used as an internal one 317 uint16_t setdceclock; //Function 318 uint16_t getmemoryclock; //Function 319 uint16_t getengineclock; //Function 320 uint16_t setcrtc_usingdtdtiming; //Function 321 uint16_t externalencodercontrol; //Function 322 uint16_t cmd_function51; //used as an internal one 323 uint16_t cmd_function52; //used as an internal one 324 uint16_t cmd_function53; //used as an internal one 325 uint16_t processi2cchanneltransaction;//Function 326 uint16_t cmd_function55; //used as an internal one 327 uint16_t cmd_function56; //used as an internal one 328 uint16_t cmd_function57; //used as an internal one 329 uint16_t cmd_function58; //used as an internal one 330 uint16_t cmd_function59; //used as an internal one 331 uint16_t computegpuclockparam; //Function 332 uint16_t cmd_function61; //used as an internal one 333 uint16_t cmd_function62; //used as an internal one 334 uint16_t dynamicmemorysettings; //Function function 335 uint16_t memorytraining; //Function function 336 uint16_t cmd_function65; //used as an internal one 337 uint16_t cmd_function66; //used as an internal one 338 uint16_t setvoltage; //Function 339 uint16_t cmd_function68; //used as an internal one 340 uint16_t readefusevalue; //Function 341 uint16_t cmd_function70; //used as an internal one 342 uint16_t cmd_function71; //used as an internal one 343 uint16_t cmd_function72; //used as an internal one 344 uint16_t cmd_function73; //used as an internal one 345 uint16_t cmd_function74; //used as an internal one 346 uint16_t cmd_function75; //used as an internal one 347 uint16_t dig1transmittercontrol; //Function 348 uint16_t cmd_function77; //used as an internal one 349 uint16_t processauxchanneltransaction;//Function 350 uint16_t cmd_function79; //used as an internal one 351 uint16_t getvoltageinfo; //Function 352}; 353 354struct atom_master_command_function_v2_1 355{ 356 struct atom_common_table_header table_header; 357 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions; 358}; 359 360/**************************************************************************** 361* Structures used in every command function 362****************************************************************************/ 363struct atom_function_attribute 364{ 365 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 366 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 367 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util 368}; 369 370 371/**************************************************************************** 372* Common header for all hw functions. 373* Every function pointed by _master_list_of_hw_function has this common header. 374* And the pointer actually points to this header. 375****************************************************************************/ 376struct atom_rom_hw_function_header 377{ 378 struct atom_common_table_header func_header; 379 struct atom_function_attribute func_attrib; 380}; 381 382 383/*==============================sw data table portion======================================================================*/ 384/**************************************************************************** 385* Structures used in data.mtb, each data table name is not given here since those data table could change from time to time 386* The real name of each table is given when its data structure version is defined 387****************************************************************************/ 388struct atom_master_list_of_data_tables_v2_1{ 389 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/ 390 uint16_t multimedia_info; 391 uint16_t smc_dpm_info; 392 uint16_t sw_datatable3; 393 uint16_t firmwareinfo; /* Shared by various SW components */ 394 uint16_t sw_datatable5; 395 uint16_t lcd_info; /* Shared by various SW components */ 396 uint16_t sw_datatable7; 397 uint16_t smu_info; 398 uint16_t sw_datatable9; 399 uint16_t sw_datatable10; 400 uint16_t vram_usagebyfirmware; /* Shared by various SW components */ 401 uint16_t gpio_pin_lut; /* Shared by various SW components */ 402 uint16_t sw_datatable13; 403 uint16_t gfx_info; 404 uint16_t powerplayinfo; /* Shared by various SW components */ 405 uint16_t sw_datatable16; 406 uint16_t sw_datatable17; 407 uint16_t sw_datatable18; 408 uint16_t sw_datatable19; 409 uint16_t sw_datatable20; 410 uint16_t sw_datatable21; 411 uint16_t displayobjectinfo; /* Shared by various SW components */ 412 uint16_t indirectioaccess; /* used as an internal one */ 413 uint16_t umc_info; /* Shared by various SW components */ 414 uint16_t sw_datatable25; 415 uint16_t sw_datatable26; 416 uint16_t dce_info; /* Shared by various SW components */ 417 uint16_t vram_info; /* Shared by various SW components */ 418 uint16_t sw_datatable29; 419 uint16_t integratedsysteminfo; /* Shared by various SW components */ 420 uint16_t asic_profiling_info; /* Shared by various SW components */ 421 uint16_t voltageobject_info; /* shared by various SW components */ 422 uint16_t sw_datatable33; 423 uint16_t sw_datatable34; 424}; 425 426 427struct atom_master_data_table_v2_1 428{ 429 struct atom_common_table_header table_header; 430 struct atom_master_list_of_data_tables_v2_1 listOfdatatables; 431}; 432 433 434struct atom_dtd_format 435{ 436 uint16_t pixclk; 437 uint16_t h_active; 438 uint16_t h_blanking_time; 439 uint16_t v_active; 440 uint16_t v_blanking_time; 441 uint16_t h_sync_offset; 442 uint16_t h_sync_width; 443 uint16_t v_sync_offset; 444 uint16_t v_syncwidth; 445 uint16_t reserved; 446 uint16_t reserved0; 447 uint8_t h_border; 448 uint8_t v_border; 449 uint16_t miscinfo; 450 uint8_t atom_mode_id; 451 uint8_t refreshrate; 452}; 453 454/* atom_dtd_format.modemiscinfo defintion */ 455enum atom_dtd_format_modemiscinfo{ 456 ATOM_HSYNC_POLARITY = 0x0002, 457 ATOM_VSYNC_POLARITY = 0x0004, 458 ATOM_H_REPLICATIONBY2 = 0x0010, 459 ATOM_V_REPLICATIONBY2 = 0x0020, 460 ATOM_INTERLACE = 0x0080, 461 ATOM_COMPOSITESYNC = 0x0040, 462}; 463 464 465/* utilitypipeline 466 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it. 467 * the location of it can't change 468*/ 469 470 471/* 472 *************************************************************************** 473 Data Table firmwareinfo structure 474 *************************************************************************** 475*/ 476 477struct atom_firmware_info_v3_1 478{ 479 struct atom_common_table_header table_header; 480 uint32_t firmware_revision; 481 uint32_t bootup_sclk_in10khz; 482 uint32_t bootup_mclk_in10khz; 483 uint32_t firmware_capability; // enum atombios_firmware_capability 484 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 485 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 486 uint16_t bootup_vddc_mv; 487 uint16_t bootup_vddci_mv; 488 uint16_t bootup_mvddc_mv; 489 uint16_t bootup_vddgfx_mv; 490 uint8_t mem_module_id; 491 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 492 uint8_t reserved1[2]; 493 uint32_t mc_baseaddr_high; 494 uint32_t mc_baseaddr_low; 495 uint32_t reserved2[6]; 496}; 497 498/* Total 32bit cap indication */ 499enum atombios_firmware_capability 500{ 501 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001, 502 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002, 503 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040, 504 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080, 505 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100, 506 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200, 507 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400, 508 ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000, 509 ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000, 510}; 511 512enum atom_cooling_solution_id{ 513 AIR_COOLING = 0x00, 514 LIQUID_COOLING = 0x01 515}; 516 517struct atom_firmware_info_v3_2 { 518 struct atom_common_table_header table_header; 519 uint32_t firmware_revision; 520 uint32_t bootup_sclk_in10khz; 521 uint32_t bootup_mclk_in10khz; 522 uint32_t firmware_capability; // enum atombios_firmware_capability 523 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 524 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 525 uint16_t bootup_vddc_mv; 526 uint16_t bootup_vddci_mv; 527 uint16_t bootup_mvddc_mv; 528 uint16_t bootup_vddgfx_mv; 529 uint8_t mem_module_id; 530 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 531 uint8_t reserved1[2]; 532 uint32_t mc_baseaddr_high; 533 uint32_t mc_baseaddr_low; 534 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 535 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 536 uint8_t board_i2c_feature_slave_addr; 537 uint8_t reserved3; 538 uint16_t bootup_mvddq_mv; 539 uint16_t bootup_mvpp_mv; 540 uint32_t zfbstartaddrin16mb; 541 uint32_t reserved2[3]; 542}; 543 544struct atom_firmware_info_v3_3 545{ 546 struct atom_common_table_header table_header; 547 uint32_t firmware_revision; 548 uint32_t bootup_sclk_in10khz; 549 uint32_t bootup_mclk_in10khz; 550 uint32_t firmware_capability; // enum atombios_firmware_capability 551 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 552 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 553 uint16_t bootup_vddc_mv; 554 uint16_t bootup_vddci_mv; 555 uint16_t bootup_mvddc_mv; 556 uint16_t bootup_vddgfx_mv; 557 uint8_t mem_module_id; 558 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 559 uint8_t reserved1[2]; 560 uint32_t mc_baseaddr_high; 561 uint32_t mc_baseaddr_low; 562 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 563 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 564 uint8_t board_i2c_feature_slave_addr; 565 uint8_t reserved3; 566 uint16_t bootup_mvddq_mv; 567 uint16_t bootup_mvpp_mv; 568 uint32_t zfbstartaddrin16mb; 569 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 570 uint32_t reserved2[2]; 571}; 572 573struct atom_firmware_info_v3_4 { 574 struct atom_common_table_header table_header; 575 uint32_t firmware_revision; 576 uint32_t bootup_sclk_in10khz; 577 uint32_t bootup_mclk_in10khz; 578 uint32_t firmware_capability; // enum atombios_firmware_capability 579 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 580 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 581 uint16_t bootup_vddc_mv; 582 uint16_t bootup_vddci_mv; 583 uint16_t bootup_mvddc_mv; 584 uint16_t bootup_vddgfx_mv; 585 uint8_t mem_module_id; 586 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 587 uint8_t reserved1[2]; 588 uint32_t mc_baseaddr_high; 589 uint32_t mc_baseaddr_low; 590 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 591 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 592 uint8_t board_i2c_feature_slave_addr; 593 uint8_t ras_rom_i2c_slave_addr; 594 uint16_t bootup_mvddq_mv; 595 uint16_t bootup_mvpp_mv; 596 uint32_t zfbstartaddrin16mb; 597 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 598 uint32_t mvdd_ratio; // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2) 599 uint16_t hw_bootup_vddgfx_mv; // hw default vddgfx voltage level decide by board strap 600 uint16_t hw_bootup_vddc_mv; // hw default vddc voltage level decide by board strap 601 uint16_t hw_bootup_mvddc_mv; // hw default mvddc voltage level decide by board strap 602 uint16_t hw_bootup_vddci_mv; // hw default vddci voltage level decide by board strap 603 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt 604 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt 605 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb. 606 uint32_t pspbl_init_done_reg_addr; 607 uint32_t pspbl_init_done_value; 608 uint32_t pspbl_init_done_check_timeout; // time out in unit of us when polling pspbl init done 609 uint32_t reserved[2]; 610}; 611 612/* 613 *************************************************************************** 614 Data Table lcd_info structure 615 *************************************************************************** 616*/ 617 618struct lcd_info_v2_1 619{ 620 struct atom_common_table_header table_header; 621 struct atom_dtd_format lcd_timing; 622 uint16_t backlight_pwm; 623 uint16_t special_handle_cap; 624 uint16_t panel_misc; 625 uint16_t lvds_max_slink_pclk; 626 uint16_t lvds_ss_percentage; 627 uint16_t lvds_ss_rate_10hz; 628 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/ 629 uint8_t pwr_on_de_to_vary_bl; 630 uint8_t pwr_down_vary_bloff_to_de; 631 uint8_t pwr_down_de_to_digoff; 632 uint8_t pwr_off_delay; 633 uint8_t pwr_on_vary_bl_to_blon; 634 uint8_t pwr_down_bloff_to_vary_bloff; 635 uint8_t panel_bpc; 636 uint8_t dpcd_edp_config_cap; 637 uint8_t dpcd_max_link_rate; 638 uint8_t dpcd_max_lane_count; 639 uint8_t dpcd_max_downspread; 640 uint8_t min_allowed_bl_level; 641 uint8_t max_allowed_bl_level; 642 uint8_t bootup_bl_level; 643 uint8_t dplvdsrxid; 644 uint32_t reserved1[8]; 645}; 646 647/* lcd_info_v2_1.panel_misc defintion */ 648enum atom_lcd_info_panel_misc{ 649 ATOM_PANEL_MISC_FPDI =0x0002, 650}; 651 652//uceDPToLVDSRxId 653enum atom_lcd_info_dptolvds_rx_id 654{ 655 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip 656 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init 657 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init 658}; 659 660 661/* 662 *************************************************************************** 663 Data Table gpio_pin_lut structure 664 *************************************************************************** 665*/ 666 667struct atom_gpio_pin_assignment 668{ 669 uint32_t data_a_reg_index; 670 uint8_t gpio_bitshift; 671 uint8_t gpio_mask_bitshift; 672 uint8_t gpio_id; 673 uint8_t reserved; 674}; 675 676/* atom_gpio_pin_assignment.gpio_id definition */ 677enum atom_gpio_pin_assignment_gpio_id { 678 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */ 679 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ 680 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */ 681 682 /* gpio_id pre-define id for multiple usage */ 683 /* GPIO use to control PCIE_VDDC in certain SLT board */ 684 PCIE_VDDC_CONTROL_GPIO_PINID = 56, 685 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */ 686 PP_AC_DC_SWITCH_GPIO_PINID = 60, 687 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */ 688 VDDC_VRHOT_GPIO_PINID = 61, 689 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */ 690 VDDC_PCC_GPIO_PINID = 62, 691 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */ 692 EFUSE_CUT_ENABLE_GPIO_PINID = 63, 693 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */ 694 DRAM_SELF_REFRESH_GPIO_PINID = 64, 695 /* Thermal interrupt output->system thermal chip GPIO pin */ 696 THERMAL_INT_OUTPUT_GPIO_PINID =65, 697}; 698 699 700struct atom_gpio_pin_lut_v2_1 701{ 702 struct atom_common_table_header table_header; 703 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */ 704 struct atom_gpio_pin_assignment gpio_pin[8]; 705}; 706 707 708/* 709 *************************************************************************** 710 Data Table vram_usagebyfirmware structure 711 *************************************************************************** 712*/ 713 714struct vram_usagebyfirmware_v2_1 715{ 716 struct atom_common_table_header table_header; 717 uint32_t start_address_in_kb; 718 uint16_t used_by_firmware_in_kb; 719 uint16_t used_by_driver_in_kb; 720}; 721 722 723/* 724 *************************************************************************** 725 Data Table displayobjectinfo structure 726 *************************************************************************** 727*/ 728 729enum atom_object_record_type_id 730{ 731 ATOM_I2C_RECORD_TYPE =1, 732 ATOM_HPD_INT_RECORD_TYPE =2, 733 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9, 734 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16, 735 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17, 736 ATOM_ENCODER_CAP_RECORD_TYPE=20, 737 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21, 738 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22, 739 ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE=23, 740 ATOM_RECORD_END_TYPE =0xFF, 741}; 742 743struct atom_common_record_header 744{ 745 uint8_t record_type; //An emun to indicate the record type 746 uint8_t record_size; //The size of the whole record in byte 747}; 748 749struct atom_i2c_record 750{ 751 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE 752 uint8_t i2c_id; 753 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC 754}; 755 756struct atom_hpd_int_record 757{ 758 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE 759 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info 760 uint8_t plugin_pin_state; 761}; 762 763// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 764enum atom_encoder_caps_def 765{ 766 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 767 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. 768 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 769 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. 770 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. 771 ATOM_ENCODER_CAP_RECORD_DP2 =0x10, // DP2 is supported by ASIC/board. 772 ATOM_ENCODER_CAP_RECORD_UHBR10_EN =0x20, // DP2.0 UHBR10 settings is supported by board 773 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN =0x40, // DP2.0 UHBR13.5 settings is supported by board 774 ATOM_ENCODER_CAP_RECORD_UHBR20_EN =0x80, // DP2.0 UHBR20 settings is supported by board 775 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type. 776}; 777 778struct atom_encoder_caps_record 779{ 780 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE 781 uint32_t encodercaps; 782}; 783 784enum atom_connector_caps_def 785{ 786 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display 787 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq 788}; 789 790struct atom_disp_connector_caps_record 791{ 792 struct atom_common_record_header record_header; 793 uint32_t connectcaps; 794}; 795 796//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 797struct atom_gpio_pin_control_pair 798{ 799 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table 800 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin 801}; 802 803struct atom_object_gpio_cntl_record 804{ 805 struct atom_common_record_header record_header; 806 uint8_t flag; // Future expnadibility 807 uint8_t number_of_pins; // Number of GPIO pins used to control the object 808 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 809}; 810 811//Definitions for GPIO pin state 812enum atom_gpio_pin_control_pinstate_def 813{ 814 GPIO_PIN_TYPE_INPUT = 0x00, 815 GPIO_PIN_TYPE_OUTPUT = 0x10, 816 GPIO_PIN_TYPE_HW_CONTROL = 0x20, 817 818//For GPIO_PIN_TYPE_OUTPUT the following is defined 819 GPIO_PIN_OUTPUT_STATE_MASK = 0x01, 820 GPIO_PIN_OUTPUT_STATE_SHIFT = 0, 821 GPIO_PIN_STATE_ACTIVE_LOW = 0x0, 822 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1, 823}; 824 825// Indexes to GPIO array in GLSync record 826// GLSync record is for Frame Lock/Gen Lock feature. 827enum atom_glsync_record_gpio_index_def 828{ 829 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0, 830 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1, 831 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2, 832 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3, 833 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4, 834 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5, 835 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6, 836 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7, 837 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8, 838 ATOM_GPIO_INDEX_GLSYNC_MAX = 9, 839}; 840 841 842struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 843{ 844 struct atom_common_record_header record_header; 845 uint8_t hpd_pin_map[8]; 846}; 847 848struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 849{ 850 struct atom_common_record_header record_header; 851 uint8_t aux_ddc_map[8]; 852}; 853 854struct atom_connector_forced_tmds_cap_record 855{ 856 struct atom_common_record_header record_header; 857 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 858 uint8_t maxtmdsclkrate_in2_5mhz; 859 uint8_t reserved; 860}; 861 862struct atom_connector_layout_info 863{ 864 uint16_t connectorobjid; 865 uint8_t connector_type; 866 uint8_t position; 867}; 868 869// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 870enum atom_connector_layout_info_connector_type_def 871{ 872 CONNECTOR_TYPE_DVI_D = 1, 873 874 CONNECTOR_TYPE_HDMI = 4, 875 CONNECTOR_TYPE_DISPLAY_PORT = 5, 876 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6, 877}; 878 879struct atom_bracket_layout_record 880{ 881 struct atom_common_record_header record_header; 882 uint8_t bracketlen; 883 uint8_t bracketwidth; 884 uint8_t conn_num; 885 uint8_t reserved; 886 struct atom_connector_layout_info conn_info[1]; 887}; 888 889enum atom_display_device_tag_def{ 890 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display 891 ATOM_DISPLAY_LCD2_SUPPORT = 0x0020, //second edp device tag 0x0020 for backward compability 892 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008, 893 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080, 894 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200, 895 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400, 896 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800, 897 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040, 898 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8, 899}; 900 901struct atom_display_object_path_v2 902{ 903 uint16_t display_objid; //Connector Object ID or Misc Object ID 904 uint16_t disp_recordoffset; 905 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder 906 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view; 907 uint16_t encoder_recordoffset; 908 uint16_t extencoder_recordoffset; 909 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first 910 uint8_t priority_id; 911 uint8_t reserved; 912}; 913 914struct display_object_info_table_v1_4 915{ 916 struct atom_common_table_header table_header; 917 uint16_t supporteddevices; 918 uint8_t number_of_path; 919 uint8_t reserved; 920 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path 921}; 922 923 924/* 925 *************************************************************************** 926 Data Table dce_info structure 927 *************************************************************************** 928*/ 929struct atom_display_controller_info_v4_1 930{ 931 struct atom_common_table_header table_header; 932 uint32_t display_caps; 933 uint32_t bootup_dispclk_10khz; 934 uint16_t dce_refclk_10khz; 935 uint16_t i2c_engine_refclk_10khz; 936 uint16_t dvi_ss_percentage; // in unit of 0.001% 937 uint16_t dvi_ss_rate_10hz; 938 uint16_t hdmi_ss_percentage; // in unit of 0.001% 939 uint16_t hdmi_ss_rate_10hz; 940 uint16_t dp_ss_percentage; // in unit of 0.001% 941 uint16_t dp_ss_rate_10hz; 942 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 943 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 944 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 945 uint8_t ss_reserved; 946 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available 947 uint8_t reserved1[3]; 948 uint16_t dpphy_refclk_10khz; 949 uint16_t reserved2; 950 uint8_t dceip_min_ver; 951 uint8_t dceip_max_ver; 952 uint8_t max_disp_pipe_num; 953 uint8_t max_vbios_active_disp_pipe_num; 954 uint8_t max_ppll_num; 955 uint8_t max_disp_phy_num; 956 uint8_t max_aux_pairs; 957 uint8_t remotedisplayconfig; 958 uint8_t reserved3[8]; 959}; 960 961struct atom_display_controller_info_v4_2 962{ 963 struct atom_common_table_header table_header; 964 uint32_t display_caps; 965 uint32_t bootup_dispclk_10khz; 966 uint16_t dce_refclk_10khz; 967 uint16_t i2c_engine_refclk_10khz; 968 uint16_t dvi_ss_percentage; // in unit of 0.001% 969 uint16_t dvi_ss_rate_10hz; 970 uint16_t hdmi_ss_percentage; // in unit of 0.001% 971 uint16_t hdmi_ss_rate_10hz; 972 uint16_t dp_ss_percentage; // in unit of 0.001% 973 uint16_t dp_ss_rate_10hz; 974 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 975 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 976 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 977 uint8_t ss_reserved; 978 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 979 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 980 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 981 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 982 uint16_t dpphy_refclk_10khz; 983 uint16_t reserved2; 984 uint8_t dcnip_min_ver; 985 uint8_t dcnip_max_ver; 986 uint8_t max_disp_pipe_num; 987 uint8_t max_vbios_active_disp_pipe_num; 988 uint8_t max_ppll_num; 989 uint8_t max_disp_phy_num; 990 uint8_t max_aux_pairs; 991 uint8_t remotedisplayconfig; 992 uint8_t reserved3[8]; 993}; 994 995struct atom_display_controller_info_v4_3 996{ 997 struct atom_common_table_header table_header; 998 uint32_t display_caps; 999 uint32_t bootup_dispclk_10khz; 1000 uint16_t dce_refclk_10khz; 1001 uint16_t i2c_engine_refclk_10khz; 1002 uint16_t dvi_ss_percentage; // in unit of 0.001% 1003 uint16_t dvi_ss_rate_10hz; 1004 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1005 uint16_t hdmi_ss_rate_10hz; 1006 uint16_t dp_ss_percentage; // in unit of 0.001% 1007 uint16_t dp_ss_rate_10hz; 1008 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1009 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1010 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1011 uint8_t ss_reserved; 1012 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1013 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1014 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1015 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1016 uint16_t dpphy_refclk_10khz; 1017 uint16_t reserved2; 1018 uint8_t dcnip_min_ver; 1019 uint8_t dcnip_max_ver; 1020 uint8_t max_disp_pipe_num; 1021 uint8_t max_vbios_active_disp_pipe_num; 1022 uint8_t max_ppll_num; 1023 uint8_t max_disp_phy_num; 1024 uint8_t max_aux_pairs; 1025 uint8_t remotedisplayconfig; 1026 uint8_t reserved3[8]; 1027}; 1028 1029struct atom_display_controller_info_v4_4 { 1030 struct atom_common_table_header table_header; 1031 uint32_t display_caps; 1032 uint32_t bootup_dispclk_10khz; 1033 uint16_t dce_refclk_10khz; 1034 uint16_t i2c_engine_refclk_10khz; 1035 uint16_t dvi_ss_percentage; // in unit of 0.001% 1036 uint16_t dvi_ss_rate_10hz; 1037 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1038 uint16_t hdmi_ss_rate_10hz; 1039 uint16_t dp_ss_percentage; // in unit of 0.001% 1040 uint16_t dp_ss_rate_10hz; 1041 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1042 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1043 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1044 uint8_t ss_reserved; 1045 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1046 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1047 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1048 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1049 uint16_t dpphy_refclk_10khz; 1050 uint16_t hw_chip_id; 1051 uint8_t dcnip_min_ver; 1052 uint8_t dcnip_max_ver; 1053 uint8_t max_disp_pipe_num; 1054 uint8_t max_vbios_active_disp_pipum; 1055 uint8_t max_ppll_num; 1056 uint8_t max_disp_phy_num; 1057 uint8_t max_aux_pairs; 1058 uint8_t remotedisplayconfig; 1059 uint32_t dispclk_pll_vco_freq; 1060 uint32_t dp_ref_clk_freq; 1061 uint32_t max_mclk_chg_lat; // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us) 1062 uint32_t max_sr_exit_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0.1us) 1063 uint32_t max_sr_enter_exit_lat; // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us) 1064 uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx 1065 uint16_t dc_golden_table_ver; 1066 uint32_t reserved3[3]; 1067}; 1068 1069struct atom_dc_golden_table_v1 1070{ 1071 uint32_t aux_dphy_rx_control0_val; 1072 uint32_t aux_dphy_tx_control_val; 1073 uint32_t aux_dphy_rx_control1_val; 1074 uint32_t dc_gpio_aux_ctrl_0_val; 1075 uint32_t dc_gpio_aux_ctrl_1_val; 1076 uint32_t dc_gpio_aux_ctrl_2_val; 1077 uint32_t dc_gpio_aux_ctrl_3_val; 1078 uint32_t dc_gpio_aux_ctrl_4_val; 1079 uint32_t dc_gpio_aux_ctrl_5_val; 1080 uint32_t reserved[23]; 1081}; 1082 1083enum dce_info_caps_def 1084{ 1085 // only for VBIOS 1086 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02, 1087 // only for VBIOS 1088 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04, 1089 // only for VBIOS 1090 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08, 1091 // only for VBIOS 1092 DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE =0x20, 1093 DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40, 1094}; 1095 1096/* 1097 *************************************************************************** 1098 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure 1099 *************************************************************************** 1100*/ 1101struct atom_ext_display_path 1102{ 1103 uint16_t device_tag; //A bit vector to show what devices are supported 1104 uint16_t device_acpi_enum; //16bit device ACPI id. 1105 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions 1106 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT 1107 uint8_t hpdlut_index; //An index into external HPD pin LUT 1108 uint16_t ext_encoder_objid; //external encoder object id 1109 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping 1110 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 1111 uint16_t caps; 1112 uint16_t reserved; 1113}; 1114 1115//usCaps 1116enum ext_display_path_cap_def { 1117 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE = 0x0001, 1118 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = 0x0002, 1119 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007C, 1120 EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x01 << 2), //PI redriver chip 1121 EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip 1122 EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x03 << 2) //Parade DP->HDMI recoverter chip 1123}; 1124 1125struct atom_external_display_connection_info 1126{ 1127 struct atom_common_table_header table_header; 1128 uint8_t guid[16]; // a GUID is a 16 byte long string 1129 struct atom_ext_display_path path[7]; // total of fixed 7 entries. 1130 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. 1131 uint8_t stereopinid; // use for eDP panel 1132 uint8_t remotedisplayconfig; 1133 uint8_t edptolvdsrxid; 1134 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value 1135 uint8_t reserved[3]; // for potential expansion 1136}; 1137 1138/* 1139 *************************************************************************** 1140 Data Table integratedsysteminfo structure 1141 *************************************************************************** 1142*/ 1143 1144struct atom_camera_dphy_timing_param 1145{ 1146 uint8_t profile_id; // SENSOR_PROFILES 1147 uint32_t param; 1148}; 1149 1150struct atom_camera_dphy_elec_param 1151{ 1152 uint16_t param[3]; 1153}; 1154 1155struct atom_camera_module_info 1156{ 1157 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user 1158 uint8_t module_name[8]; 1159 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor 1160}; 1161 1162struct atom_camera_flashlight_info 1163{ 1164 uint8_t flashlight_id; // 0: Rear, 1: Front 1165 uint8_t name[8]; 1166}; 1167 1168struct atom_camera_data 1169{ 1170 uint32_t versionCode; 1171 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max 1172 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max 1173 struct atom_camera_dphy_elec_param dphy_param; 1174 uint32_t crc_val; // CRC 1175}; 1176 1177 1178struct atom_14nm_dpphy_dvihdmi_tuningset 1179{ 1180 uint32_t max_symclk_in10khz; 1181 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1182 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1183 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1184 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1185 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1186 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms 1187 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL 1188}; 1189 1190struct atom_14nm_dpphy_dp_setting{ 1191 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1192 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1193 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1194 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1195}; 1196 1197struct atom_14nm_dpphy_dp_tuningset{ 1198 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1199 uint8_t version; 1200 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset 1201 uint16_t reserved; 1202 struct atom_14nm_dpphy_dp_setting dptuning[10]; 1203}; 1204 1205struct atom_14nm_dig_transmitter_info_header_v4_0{ 1206 struct atom_common_table_header table_header; 1207 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl 1208 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl 1209 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl 1210}; 1211 1212struct atom_14nm_combphy_tmds_vs_set 1213{ 1214 uint8_t sym_clk; 1215 uint8_t dig_mode; 1216 uint8_t phy_sel; 1217 uint16_t common_mar_deemph_nom__margin_deemph_val; 1218 uint8_t common_seldeemph60__deemph_6db_4_val; 1219 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ; 1220 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val; 1221 uint8_t margin_deemph_lane0__deemph_sel_val; 1222}; 1223 1224struct atom_DCN_dpphy_dvihdmi_tuningset 1225{ 1226 uint32_t max_symclk_in10khz; 1227 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1228 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1229 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1230 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1231 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1232 uint8_t reserved1; 1233 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1234 uint8_t reserved2; 1235}; 1236 1237struct atom_DCN_dpphy_dp_setting{ 1238 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1239 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1240 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1241 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1242 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1243}; 1244 1245struct atom_DCN_dpphy_dp_tuningset{ 1246 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1247 uint8_t version; 1248 uint16_t table_size; // size of atom_14nm_dpphy_dp_setting 1249 uint16_t reserved; 1250 struct atom_DCN_dpphy_dp_setting dptunings[10]; 1251}; 1252 1253struct atom_i2c_reg_info { 1254 uint8_t ucI2cRegIndex; 1255 uint8_t ucI2cRegVal; 1256}; 1257 1258struct atom_hdmi_retimer_redriver_set { 1259 uint8_t HdmiSlvAddr; 1260 uint8_t HdmiRegNum; 1261 uint8_t Hdmi6GRegNum; 1262 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use 1263 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use. 1264}; 1265 1266struct atom_integrated_system_info_v1_11 1267{ 1268 struct atom_common_table_header table_header; 1269 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1270 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1271 uint32_t system_config; 1272 uint32_t cpucapinfo; 1273 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1274 uint16_t gpuclk_ss_type; 1275 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1276 uint16_t lvds_ss_rate_10hz; 1277 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1278 uint16_t hdmi_ss_rate_10hz; 1279 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1280 uint16_t dvi_ss_rate_10hz; 1281 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1282 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1283 uint16_t backlight_pwm_hz; // pwm frequency in hz 1284 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1285 uint8_t umachannelnumber; // number of memory channels 1286 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */ 1287 uint8_t pwr_on_de_to_vary_bl; 1288 uint8_t pwr_down_vary_bloff_to_de; 1289 uint8_t pwr_down_de_to_digoff; 1290 uint8_t pwr_off_delay; 1291 uint8_t pwr_on_vary_bl_to_blon; 1292 uint8_t pwr_down_bloff_to_vary_bloff; 1293 uint8_t min_allowed_bl_level; 1294 uint8_t htc_hyst_limit; 1295 uint8_t htc_tmp_limit; 1296 uint8_t reserved1; 1297 uint8_t reserved2; 1298 struct atom_external_display_connection_info extdispconninfo; 1299 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset; 1300 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset; 1301 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset; 1302 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set 1303 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set 1304 struct atom_camera_data camera_info; 1305 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1306 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1307 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1308 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1309 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set 1310 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set 1311 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set 1312 uint32_t reserved[66]; 1313}; 1314 1315struct atom_integrated_system_info_v1_12 1316{ 1317 struct atom_common_table_header table_header; 1318 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1319 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1320 uint32_t system_config; 1321 uint32_t cpucapinfo; 1322 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1323 uint16_t gpuclk_ss_type; 1324 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1325 uint16_t lvds_ss_rate_10hz; 1326 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1327 uint16_t hdmi_ss_rate_10hz; 1328 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1329 uint16_t dvi_ss_rate_10hz; 1330 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1331 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1332 uint16_t backlight_pwm_hz; // pwm frequency in hz 1333 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1334 uint8_t umachannelnumber; // number of memory channels 1335 uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms // 1336 uint8_t pwr_on_de_to_vary_bl; 1337 uint8_t pwr_down_vary_bloff_to_de; 1338 uint8_t pwr_down_de_to_digoff; 1339 uint8_t pwr_off_delay; 1340 uint8_t pwr_on_vary_bl_to_blon; 1341 uint8_t pwr_down_bloff_to_vary_bloff; 1342 uint8_t min_allowed_bl_level; 1343 uint8_t htc_hyst_limit; 1344 uint8_t htc_tmp_limit; 1345 uint8_t reserved1; 1346 uint8_t reserved2; 1347 struct atom_external_display_connection_info extdispconninfo; 1348 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1349 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; 1350 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1351 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1352 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1353 struct atom_camera_data camera_info; 1354 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1355 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1356 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1357 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1358 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1359 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1360 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1361 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1362 uint32_t reserved[63]; 1363}; 1364 1365struct edp_info_table 1366{ 1367 uint16_t edp_backlight_pwm_hz; 1368 uint16_t edp_ss_percentage; 1369 uint16_t edp_ss_rate_10hz; 1370 uint16_t reserved1; 1371 uint32_t reserved2; 1372 uint8_t edp_pwr_on_off_delay; 1373 uint8_t edp_pwr_on_vary_bl_to_blon; 1374 uint8_t edp_pwr_down_bloff_to_vary_bloff; 1375 uint8_t edp_panel_bpc; 1376 uint8_t edp_bootup_bl_level; 1377 uint8_t reserved3[3]; 1378 uint32_t reserved4[3]; 1379}; 1380 1381struct atom_integrated_system_info_v2_1 1382{ 1383 struct atom_common_table_header table_header; 1384 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1385 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1386 uint32_t system_config; 1387 uint32_t cpucapinfo; 1388 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1389 uint16_t gpuclk_ss_type; 1390 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1391 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1392 uint8_t umachannelnumber; // number of memory channels 1393 uint8_t htc_hyst_limit; 1394 uint8_t htc_tmp_limit; 1395 uint8_t reserved1; 1396 uint8_t reserved2; 1397 struct edp_info_table edp1_info; 1398 struct edp_info_table edp2_info; 1399 uint32_t reserved3[8]; 1400 struct atom_external_display_connection_info extdispconninfo; 1401 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1402 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; //add clk6 1403 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1404 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1405 uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset) 1406 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1407 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1408 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1409 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1410 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1411 uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset) 1412 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1413 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1414 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1415 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1416 uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info 1417 uint32_t reserved7[32]; 1418 1419}; 1420 1421struct atom_n6_display_phy_tuning_set { 1422 uint8_t display_signal_type; 1423 uint8_t phy_sel; 1424 uint8_t preset_level; 1425 uint8_t reserved1; 1426 uint32_t reserved2; 1427 uint32_t speed_upto; 1428 uint8_t tx_vboost_level; 1429 uint8_t tx_vreg_v2i; 1430 uint8_t tx_vregdrv_byp; 1431 uint8_t tx_term_cntl; 1432 uint8_t tx_peak_level; 1433 uint8_t tx_slew_en; 1434 uint8_t tx_eq_pre; 1435 uint8_t tx_eq_main; 1436 uint8_t tx_eq_post; 1437 uint8_t tx_en_inv_pre; 1438 uint8_t tx_en_inv_post; 1439 uint8_t reserved3; 1440 uint32_t reserved4; 1441 uint32_t reserved5; 1442 uint32_t reserved6; 1443}; 1444 1445struct atom_display_phy_tuning_info { 1446 struct atom_common_table_header table_header; 1447 struct atom_n6_display_phy_tuning_set disp_phy_tuning[1]; 1448}; 1449 1450struct atom_integrated_system_info_v2_2 1451{ 1452 struct atom_common_table_header table_header; 1453 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1454 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1455 uint32_t system_config; 1456 uint32_t cpucapinfo; 1457 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1458 uint16_t gpuclk_ss_type; 1459 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1460 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1461 uint8_t umachannelnumber; // number of memory channels 1462 uint8_t htc_hyst_limit; 1463 uint8_t htc_tmp_limit; 1464 uint8_t reserved1; 1465 uint8_t reserved2; 1466 struct edp_info_table edp1_info; 1467 struct edp_info_table edp2_info; 1468 uint32_t reserved3[8]; 1469 struct atom_external_display_connection_info extdispconninfo; 1470 1471 uint32_t reserved4[189]; 1472}; 1473 1474// system_config 1475enum atom_system_vbiosmisc_def{ 1476 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01, 1477}; 1478 1479 1480// gpucapinfo 1481enum atom_system_gpucapinf_def{ 1482 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10, 1483}; 1484 1485//dpphy_override 1486enum atom_sysinfo_dpphy_override_def{ 1487 ATOM_ENABLE_DVI_TUNINGSET = 0x01, 1488 ATOM_ENABLE_HDMI_TUNINGSET = 0x02, 1489 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04, 1490 ATOM_ENABLE_DP_TUNINGSET = 0x08, 1491 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, 1492}; 1493 1494//lvds_misc 1495enum atom_sys_info_lvds_misc_def 1496{ 1497 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01, 1498 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04, 1499 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08, 1500}; 1501 1502 1503//memorytype DMI Type 17 offset 12h - Memory Type 1504enum atom_dmi_t17_mem_type_def{ 1505 OtherMemType = 0x01, ///< Assign 01 to Other 1506 UnknownMemType, ///< Assign 02 to Unknown 1507 DramMemType, ///< Assign 03 to DRAM 1508 EdramMemType, ///< Assign 04 to EDRAM 1509 VramMemType, ///< Assign 05 to VRAM 1510 SramMemType, ///< Assign 06 to SRAM 1511 RamMemType, ///< Assign 07 to RAM 1512 RomMemType, ///< Assign 08 to ROM 1513 FlashMemType, ///< Assign 09 to Flash 1514 EepromMemType, ///< Assign 10 to EEPROM 1515 FepromMemType, ///< Assign 11 to FEPROM 1516 EpromMemType, ///< Assign 12 to EPROM 1517 CdramMemType, ///< Assign 13 to CDRAM 1518 ThreeDramMemType, ///< Assign 14 to 3DRAM 1519 SdramMemType, ///< Assign 15 to SDRAM 1520 SgramMemType, ///< Assign 16 to SGRAM 1521 RdramMemType, ///< Assign 17 to RDRAM 1522 DdrMemType, ///< Assign 18 to DDR 1523 Ddr2MemType, ///< Assign 19 to DDR2 1524 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM 1525 Ddr3MemType = 0x18, ///< Assign 24 to DDR3 1526 Fbd2MemType, ///< Assign 25 to FBD2 1527 Ddr4MemType, ///< Assign 26 to DDR4 1528 LpDdrMemType, ///< Assign 27 to LPDDR 1529 LpDdr2MemType, ///< Assign 28 to LPDDR2 1530 LpDdr3MemType, ///< Assign 29 to LPDDR3 1531 LpDdr4MemType, ///< Assign 30 to LPDDR4 1532 GDdr6MemType, ///< Assign 31 to GDDR6 1533 HbmMemType, ///< Assign 32 to HBM 1534 Hbm2MemType, ///< Assign 33 to HBM2 1535 Ddr5MemType, ///< Assign 34 to DDR5 1536 LpDdr5MemType, ///< Assign 35 to LPDDR5 1537}; 1538 1539 1540// this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable 1541struct atom_fusion_system_info_v4 1542{ 1543 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 1544 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable 1545}; 1546 1547 1548/* 1549 *************************************************************************** 1550 Data Table gfx_info structure 1551 *************************************************************************** 1552*/ 1553 1554struct atom_gfx_info_v2_2 1555{ 1556 struct atom_common_table_header table_header; 1557 uint8_t gfxip_min_ver; 1558 uint8_t gfxip_max_ver; 1559 uint8_t max_shader_engines; 1560 uint8_t max_tile_pipes; 1561 uint8_t max_cu_per_sh; 1562 uint8_t max_sh_per_se; 1563 uint8_t max_backends_per_se; 1564 uint8_t max_texture_channel_caches; 1565 uint32_t regaddr_cp_dma_src_addr; 1566 uint32_t regaddr_cp_dma_src_addr_hi; 1567 uint32_t regaddr_cp_dma_dst_addr; 1568 uint32_t regaddr_cp_dma_dst_addr_hi; 1569 uint32_t regaddr_cp_dma_command; 1570 uint32_t regaddr_cp_status; 1571 uint32_t regaddr_rlc_gpu_clock_32; 1572 uint32_t rlc_gpu_timer_refclk; 1573}; 1574 1575struct atom_gfx_info_v2_3 { 1576 struct atom_common_table_header table_header; 1577 uint8_t gfxip_min_ver; 1578 uint8_t gfxip_max_ver; 1579 uint8_t max_shader_engines; 1580 uint8_t max_tile_pipes; 1581 uint8_t max_cu_per_sh; 1582 uint8_t max_sh_per_se; 1583 uint8_t max_backends_per_se; 1584 uint8_t max_texture_channel_caches; 1585 uint32_t regaddr_cp_dma_src_addr; 1586 uint32_t regaddr_cp_dma_src_addr_hi; 1587 uint32_t regaddr_cp_dma_dst_addr; 1588 uint32_t regaddr_cp_dma_dst_addr_hi; 1589 uint32_t regaddr_cp_dma_command; 1590 uint32_t regaddr_cp_status; 1591 uint32_t regaddr_rlc_gpu_clock_32; 1592 uint32_t rlc_gpu_timer_refclk; 1593 uint8_t active_cu_per_sh; 1594 uint8_t active_rb_per_se; 1595 uint16_t gcgoldenoffset; 1596 uint32_t rm21_sram_vmin_value; 1597}; 1598 1599struct atom_gfx_info_v2_4 1600{ 1601 struct atom_common_table_header table_header; 1602 uint8_t gfxip_min_ver; 1603 uint8_t gfxip_max_ver; 1604 uint8_t max_shader_engines; 1605 uint8_t reserved; 1606 uint8_t max_cu_per_sh; 1607 uint8_t max_sh_per_se; 1608 uint8_t max_backends_per_se; 1609 uint8_t max_texture_channel_caches; 1610 uint32_t regaddr_cp_dma_src_addr; 1611 uint32_t regaddr_cp_dma_src_addr_hi; 1612 uint32_t regaddr_cp_dma_dst_addr; 1613 uint32_t regaddr_cp_dma_dst_addr_hi; 1614 uint32_t regaddr_cp_dma_command; 1615 uint32_t regaddr_cp_status; 1616 uint32_t regaddr_rlc_gpu_clock_32; 1617 uint32_t rlc_gpu_timer_refclk; 1618 uint8_t active_cu_per_sh; 1619 uint8_t active_rb_per_se; 1620 uint16_t gcgoldenoffset; 1621 uint16_t gc_num_gprs; 1622 uint16_t gc_gsprim_buff_depth; 1623 uint16_t gc_parameter_cache_depth; 1624 uint16_t gc_wave_size; 1625 uint16_t gc_max_waves_per_simd; 1626 uint16_t gc_lds_size; 1627 uint8_t gc_num_max_gs_thds; 1628 uint8_t gc_gs_table_depth; 1629 uint8_t gc_double_offchip_lds_buffer; 1630 uint8_t gc_max_scratch_slots_per_cu; 1631 uint32_t sram_rm_fuses_val; 1632 uint32_t sram_custom_rm_fuses_val; 1633}; 1634 1635struct atom_gfx_info_v2_7 { 1636 struct atom_common_table_header table_header; 1637 uint8_t gfxip_min_ver; 1638 uint8_t gfxip_max_ver; 1639 uint8_t max_shader_engines; 1640 uint8_t reserved; 1641 uint8_t max_cu_per_sh; 1642 uint8_t max_sh_per_se; 1643 uint8_t max_backends_per_se; 1644 uint8_t max_texture_channel_caches; 1645 uint32_t regaddr_cp_dma_src_addr; 1646 uint32_t regaddr_cp_dma_src_addr_hi; 1647 uint32_t regaddr_cp_dma_dst_addr; 1648 uint32_t regaddr_cp_dma_dst_addr_hi; 1649 uint32_t regaddr_cp_dma_command; 1650 uint32_t regaddr_cp_status; 1651 uint32_t regaddr_rlc_gpu_clock_32; 1652 uint32_t rlc_gpu_timer_refclk; 1653 uint8_t active_cu_per_sh; 1654 uint8_t active_rb_per_se; 1655 uint16_t gcgoldenoffset; 1656 uint16_t gc_num_gprs; 1657 uint16_t gc_gsprim_buff_depth; 1658 uint16_t gc_parameter_cache_depth; 1659 uint16_t gc_wave_size; 1660 uint16_t gc_max_waves_per_simd; 1661 uint16_t gc_lds_size; 1662 uint8_t gc_num_max_gs_thds; 1663 uint8_t gc_gs_table_depth; 1664 uint8_t gc_double_offchip_lds_buffer; 1665 uint8_t gc_max_scratch_slots_per_cu; 1666 uint32_t sram_rm_fuses_val; 1667 uint32_t sram_custom_rm_fuses_val; 1668 uint8_t cut_cu; 1669 uint8_t active_cu_total; 1670 uint8_t cu_reserved[2]; 1671 uint32_t gc_config; 1672 uint8_t inactive_cu_per_se[8]; 1673 uint32_t reserved2[6]; 1674}; 1675 1676struct atom_gfx_info_v3_0 { 1677 struct atom_common_table_header table_header; 1678 uint8_t gfxip_min_ver; 1679 uint8_t gfxip_max_ver; 1680 uint8_t max_shader_engines; 1681 uint8_t max_tile_pipes; 1682 uint8_t max_cu_per_sh; 1683 uint8_t max_sh_per_se; 1684 uint8_t max_backends_per_se; 1685 uint8_t max_texture_channel_caches; 1686 uint32_t regaddr_lsdma_queue0_rb_rptr; 1687 uint32_t regaddr_lsdma_queue0_rb_rptr_hi; 1688 uint32_t regaddr_lsdma_queue0_rb_wptr; 1689 uint32_t regaddr_lsdma_queue0_rb_wptr_hi; 1690 uint32_t regaddr_lsdma_command; 1691 uint32_t regaddr_lsdma_status; 1692 uint32_t regaddr_golden_tsc_count_lower; 1693 uint32_t golden_tsc_count_lower_refclk; 1694 uint8_t active_wgp_per_se; 1695 uint8_t active_rb_per_se; 1696 uint8_t active_se; 1697 uint8_t reserved1; 1698 uint32_t sram_rm_fuses_val; 1699 uint32_t sram_custom_rm_fuses_val; 1700 uint32_t inactive_sa_mask; 1701 uint32_t gc_config; 1702 uint8_t inactive_wgp[16]; 1703 uint8_t inactive_rb[16]; 1704 uint32_t gdfll_as_wait_ctrl_val; 1705 uint32_t gdfll_as_step_ctrl_val; 1706 uint32_t reserved[8]; 1707}; 1708 1709/* 1710 *************************************************************************** 1711 Data Table smu_info structure 1712 *************************************************************************** 1713*/ 1714struct atom_smu_info_v3_1 1715{ 1716 struct atom_common_table_header table_header; 1717 uint8_t smuip_min_ver; 1718 uint8_t smuip_max_ver; 1719 uint8_t smu_rsd1; 1720 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode 1721 uint16_t sclk_ss_percentage; 1722 uint16_t sclk_ss_rate_10hz; 1723 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1724 uint16_t gpuclk_ss_rate_10hz; 1725 uint32_t core_refclk_10khz; 1726 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1727 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1728 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1729 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1730 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1731 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1732 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1733 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1734}; 1735 1736struct atom_smu_info_v3_2 { 1737 struct atom_common_table_header table_header; 1738 uint8_t smuip_min_ver; 1739 uint8_t smuip_max_ver; 1740 uint8_t smu_rsd1; 1741 uint8_t gpuclk_ss_mode; 1742 uint16_t sclk_ss_percentage; 1743 uint16_t sclk_ss_rate_10hz; 1744 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1745 uint16_t gpuclk_ss_rate_10hz; 1746 uint32_t core_refclk_10khz; 1747 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1748 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1749 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1750 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1751 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1752 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1753 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1754 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1755 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1756 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1757 uint16_t smugoldenoffset; 1758 uint32_t gpupll_vco_freq_10khz; 1759 uint32_t bootup_smnclk_10khz; 1760 uint32_t bootup_socclk_10khz; 1761 uint32_t bootup_mp0clk_10khz; 1762 uint32_t bootup_mp1clk_10khz; 1763 uint32_t bootup_lclk_10khz; 1764 uint32_t bootup_dcefclk_10khz; 1765 uint32_t ctf_threshold_override_value; 1766 uint32_t reserved[5]; 1767}; 1768 1769struct atom_smu_info_v3_3 { 1770 struct atom_common_table_header table_header; 1771 uint8_t smuip_min_ver; 1772 uint8_t smuip_max_ver; 1773 uint8_t waflclk_ss_mode; 1774 uint8_t gpuclk_ss_mode; 1775 uint16_t sclk_ss_percentage; 1776 uint16_t sclk_ss_rate_10hz; 1777 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1778 uint16_t gpuclk_ss_rate_10hz; 1779 uint32_t core_refclk_10khz; 1780 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1781 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1782 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1783 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1784 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1785 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1786 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1787 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1788 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1789 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1790 uint16_t smugoldenoffset; 1791 uint32_t gpupll_vco_freq_10khz; 1792 uint32_t bootup_smnclk_10khz; 1793 uint32_t bootup_socclk_10khz; 1794 uint32_t bootup_mp0clk_10khz; 1795 uint32_t bootup_mp1clk_10khz; 1796 uint32_t bootup_lclk_10khz; 1797 uint32_t bootup_dcefclk_10khz; 1798 uint32_t ctf_threshold_override_value; 1799 uint32_t syspll3_0_vco_freq_10khz; 1800 uint32_t syspll3_1_vco_freq_10khz; 1801 uint32_t bootup_fclk_10khz; 1802 uint32_t bootup_waflclk_10khz; 1803 uint32_t smu_info_caps; 1804 uint16_t waflclk_ss_percentage; // in unit of 0.001% 1805 uint16_t smuinitoffset; 1806 uint32_t reserved; 1807}; 1808 1809struct atom_smu_info_v3_6 1810{ 1811 struct atom_common_table_header table_header; 1812 uint8_t smuip_min_ver; 1813 uint8_t smuip_max_ver; 1814 uint8_t waflclk_ss_mode; 1815 uint8_t gpuclk_ss_mode; 1816 uint16_t sclk_ss_percentage; 1817 uint16_t sclk_ss_rate_10hz; 1818 uint16_t gpuclk_ss_percentage; 1819 uint16_t gpuclk_ss_rate_10hz; 1820 uint32_t core_refclk_10khz; 1821 uint32_t syspll0_1_vco_freq_10khz; 1822 uint32_t syspll0_2_vco_freq_10khz; 1823 uint8_t pcc_gpio_bit; 1824 uint8_t pcc_gpio_polarity; 1825 uint16_t smugoldenoffset; 1826 uint32_t syspll0_0_vco_freq_10khz; 1827 uint32_t bootup_smnclk_10khz; 1828 uint32_t bootup_socclk_10khz; 1829 uint32_t bootup_mp0clk_10khz; 1830 uint32_t bootup_mp1clk_10khz; 1831 uint32_t bootup_lclk_10khz; 1832 uint32_t bootup_dxioclk_10khz; 1833 uint32_t ctf_threshold_override_value; 1834 uint32_t syspll3_0_vco_freq_10khz; 1835 uint32_t syspll3_1_vco_freq_10khz; 1836 uint32_t bootup_fclk_10khz; 1837 uint32_t bootup_waflclk_10khz; 1838 uint32_t smu_info_caps; 1839 uint16_t waflclk_ss_percentage; 1840 uint16_t smuinitoffset; 1841 uint32_t bootup_gfxavsclk_10khz; 1842 uint32_t bootup_mpioclk_10khz; 1843 uint32_t smb_slave_address; 1844 uint32_t cg_fdo_ctrl0_val; 1845 uint32_t cg_fdo_ctrl1_val; 1846 uint32_t cg_fdo_ctrl2_val; 1847 uint32_t gdfll_as_wait_ctrl_val; 1848 uint32_t gdfll_as_step_ctrl_val; 1849 uint32_t reserved_clk; 1850 uint32_t fclk_syspll_refclk_10khz; 1851 uint32_t smusvi_svc0_val; 1852 uint32_t smusvi_svc1_val; 1853 uint32_t smusvi_svd0_val; 1854 uint32_t smusvi_svd1_val; 1855 uint32_t smusvi_svt0_val; 1856 uint32_t smusvi_svt1_val; 1857 uint32_t cg_tach_ctrl_val; 1858 uint32_t cg_pump_ctrl1_val; 1859 uint32_t cg_pump_tach_ctrl_val; 1860 uint32_t thm_ctf_delay_val; 1861 uint32_t thm_thermal_int_ctrl_val; 1862 uint32_t thm_tmon_config_val; 1863 uint32_t bootup_vclk_10khz; 1864 uint32_t bootup_dclk_10khz; 1865 uint32_t smu_gpiopad_pu_en_val; 1866 uint32_t smu_gpiopad_pd_en_val; 1867 uint32_t reserved[12]; 1868}; 1869 1870struct atom_smu_info_v4_0 { 1871 struct atom_common_table_header table_header; 1872 uint32_t bootup_gfxclk_bypass_10khz; 1873 uint32_t bootup_usrclk_10khz; 1874 uint32_t bootup_csrclk_10khz; 1875 uint32_t core_refclk_10khz; 1876 uint32_t syspll1_vco_freq_10khz; 1877 uint32_t syspll2_vco_freq_10khz; 1878 uint8_t pcc_gpio_bit; 1879 uint8_t pcc_gpio_polarity; 1880 uint16_t bootup_vddusr_mv; 1881 uint32_t syspll0_vco_freq_10khz; 1882 uint32_t bootup_smnclk_10khz; 1883 uint32_t bootup_socclk_10khz; 1884 uint32_t bootup_mp0clk_10khz; 1885 uint32_t bootup_mp1clk_10khz; 1886 uint32_t bootup_lclk_10khz; 1887 uint32_t bootup_dcefclk_10khz; 1888 uint32_t ctf_threshold_override_value; 1889 uint32_t syspll3_vco_freq_10khz; 1890 uint32_t mm_syspll_vco_freq_10khz; 1891 uint32_t bootup_fclk_10khz; 1892 uint32_t bootup_waflclk_10khz; 1893 uint32_t smu_info_caps; 1894 uint16_t waflclk_ss_percentage; 1895 uint16_t smuinitoffset; 1896 uint32_t bootup_dprefclk_10khz; 1897 uint32_t bootup_usbclk_10khz; 1898 uint32_t smb_slave_address; 1899 uint32_t cg_fdo_ctrl0_val; 1900 uint32_t cg_fdo_ctrl1_val; 1901 uint32_t cg_fdo_ctrl2_val; 1902 uint32_t gdfll_as_wait_ctrl_val; 1903 uint32_t gdfll_as_step_ctrl_val; 1904 uint32_t bootup_dtbclk_10khz; 1905 uint32_t fclk_syspll_refclk_10khz; 1906 uint32_t smusvi_svc0_val; 1907 uint32_t smusvi_svc1_val; 1908 uint32_t smusvi_svd0_val; 1909 uint32_t smusvi_svd1_val; 1910 uint32_t smusvi_svt0_val; 1911 uint32_t smusvi_svt1_val; 1912 uint32_t cg_tach_ctrl_val; 1913 uint32_t cg_pump_ctrl1_val; 1914 uint32_t cg_pump_tach_ctrl_val; 1915 uint32_t thm_ctf_delay_val; 1916 uint32_t thm_thermal_int_ctrl_val; 1917 uint32_t thm_tmon_config_val; 1918 uint32_t smbus_timing_cntrl0_val; 1919 uint32_t smbus_timing_cntrl1_val; 1920 uint32_t smbus_timing_cntrl2_val; 1921 uint32_t pwr_disp_timer_global_control_val; 1922 uint32_t bootup_mpioclk_10khz; 1923 uint32_t bootup_dclk0_10khz; 1924 uint32_t bootup_vclk0_10khz; 1925 uint32_t bootup_dclk1_10khz; 1926 uint32_t bootup_vclk1_10khz; 1927 uint32_t bootup_baco400clk_10khz; 1928 uint32_t bootup_baco1200clk_bypass_10khz; 1929 uint32_t bootup_baco700clk_bypass_10khz; 1930 uint32_t reserved[16]; 1931}; 1932 1933/* 1934 *************************************************************************** 1935 Data Table smc_dpm_info structure 1936 *************************************************************************** 1937 */ 1938struct atom_smc_dpm_info_v4_1 1939{ 1940 struct atom_common_table_header table_header; 1941 uint8_t liquid1_i2c_address; 1942 uint8_t liquid2_i2c_address; 1943 uint8_t vr_i2c_address; 1944 uint8_t plx_i2c_address; 1945 1946 uint8_t liquid_i2c_linescl; 1947 uint8_t liquid_i2c_linesda; 1948 uint8_t vr_i2c_linescl; 1949 uint8_t vr_i2c_linesda; 1950 1951 uint8_t plx_i2c_linescl; 1952 uint8_t plx_i2c_linesda; 1953 uint8_t vrsensorpresent; 1954 uint8_t liquidsensorpresent; 1955 1956 uint16_t maxvoltagestepgfx; 1957 uint16_t maxvoltagestepsoc; 1958 1959 uint8_t vddgfxvrmapping; 1960 uint8_t vddsocvrmapping; 1961 uint8_t vddmem0vrmapping; 1962 uint8_t vddmem1vrmapping; 1963 1964 uint8_t gfxulvphasesheddingmask; 1965 uint8_t soculvphasesheddingmask; 1966 uint8_t padding8_v[2]; 1967 1968 uint16_t gfxmaxcurrent; 1969 uint8_t gfxoffset; 1970 uint8_t padding_telemetrygfx; 1971 1972 uint16_t socmaxcurrent; 1973 uint8_t socoffset; 1974 uint8_t padding_telemetrysoc; 1975 1976 uint16_t mem0maxcurrent; 1977 uint8_t mem0offset; 1978 uint8_t padding_telemetrymem0; 1979 1980 uint16_t mem1maxcurrent; 1981 uint8_t mem1offset; 1982 uint8_t padding_telemetrymem1; 1983 1984 uint8_t acdcgpio; 1985 uint8_t acdcpolarity; 1986 uint8_t vr0hotgpio; 1987 uint8_t vr0hotpolarity; 1988 1989 uint8_t vr1hotgpio; 1990 uint8_t vr1hotpolarity; 1991 uint8_t padding1; 1992 uint8_t padding2; 1993 1994 uint8_t ledpin0; 1995 uint8_t ledpin1; 1996 uint8_t ledpin2; 1997 uint8_t padding8_4; 1998 1999 uint8_t pllgfxclkspreadenabled; 2000 uint8_t pllgfxclkspreadpercent; 2001 uint16_t pllgfxclkspreadfreq; 2002 2003 uint8_t uclkspreadenabled; 2004 uint8_t uclkspreadpercent; 2005 uint16_t uclkspreadfreq; 2006 2007 uint8_t socclkspreadenabled; 2008 uint8_t socclkspreadpercent; 2009 uint16_t socclkspreadfreq; 2010 2011 uint8_t acggfxclkspreadenabled; 2012 uint8_t acggfxclkspreadpercent; 2013 uint16_t acggfxclkspreadfreq; 2014 2015 uint8_t Vr2_I2C_address; 2016 uint8_t padding_vr2[3]; 2017 2018 uint32_t boardreserved[9]; 2019}; 2020 2021/* 2022 *************************************************************************** 2023 Data Table smc_dpm_info structure 2024 *************************************************************************** 2025 */ 2026struct atom_smc_dpm_info_v4_3 2027{ 2028 struct atom_common_table_header table_header; 2029 uint8_t liquid1_i2c_address; 2030 uint8_t liquid2_i2c_address; 2031 uint8_t vr_i2c_address; 2032 uint8_t plx_i2c_address; 2033 2034 uint8_t liquid_i2c_linescl; 2035 uint8_t liquid_i2c_linesda; 2036 uint8_t vr_i2c_linescl; 2037 uint8_t vr_i2c_linesda; 2038 2039 uint8_t plx_i2c_linescl; 2040 uint8_t plx_i2c_linesda; 2041 uint8_t vrsensorpresent; 2042 uint8_t liquidsensorpresent; 2043 2044 uint16_t maxvoltagestepgfx; 2045 uint16_t maxvoltagestepsoc; 2046 2047 uint8_t vddgfxvrmapping; 2048 uint8_t vddsocvrmapping; 2049 uint8_t vddmem0vrmapping; 2050 uint8_t vddmem1vrmapping; 2051 2052 uint8_t gfxulvphasesheddingmask; 2053 uint8_t soculvphasesheddingmask; 2054 uint8_t externalsensorpresent; 2055 uint8_t padding8_v; 2056 2057 uint16_t gfxmaxcurrent; 2058 uint8_t gfxoffset; 2059 uint8_t padding_telemetrygfx; 2060 2061 uint16_t socmaxcurrent; 2062 uint8_t socoffset; 2063 uint8_t padding_telemetrysoc; 2064 2065 uint16_t mem0maxcurrent; 2066 uint8_t mem0offset; 2067 uint8_t padding_telemetrymem0; 2068 2069 uint16_t mem1maxcurrent; 2070 uint8_t mem1offset; 2071 uint8_t padding_telemetrymem1; 2072 2073 uint8_t acdcgpio; 2074 uint8_t acdcpolarity; 2075 uint8_t vr0hotgpio; 2076 uint8_t vr0hotpolarity; 2077 2078 uint8_t vr1hotgpio; 2079 uint8_t vr1hotpolarity; 2080 uint8_t padding1; 2081 uint8_t padding2; 2082 2083 uint8_t ledpin0; 2084 uint8_t ledpin1; 2085 uint8_t ledpin2; 2086 uint8_t padding8_4; 2087 2088 uint8_t pllgfxclkspreadenabled; 2089 uint8_t pllgfxclkspreadpercent; 2090 uint16_t pllgfxclkspreadfreq; 2091 2092 uint8_t uclkspreadenabled; 2093 uint8_t uclkspreadpercent; 2094 uint16_t uclkspreadfreq; 2095 2096 uint8_t fclkspreadenabled; 2097 uint8_t fclkspreadpercent; 2098 uint16_t fclkspreadfreq; 2099 2100 uint8_t fllgfxclkspreadenabled; 2101 uint8_t fllgfxclkspreadpercent; 2102 uint16_t fllgfxclkspreadfreq; 2103 2104 uint32_t boardreserved[10]; 2105}; 2106 2107struct smudpm_i2ccontrollerconfig_t { 2108 uint32_t enabled; 2109 uint32_t slaveaddress; 2110 uint32_t controllerport; 2111 uint32_t controllername; 2112 uint32_t thermalthrottler; 2113 uint32_t i2cprotocol; 2114 uint32_t i2cspeed; 2115}; 2116 2117struct atom_smc_dpm_info_v4_4 2118{ 2119 struct atom_common_table_header table_header; 2120 uint32_t i2c_padding[3]; 2121 2122 uint16_t maxvoltagestepgfx; 2123 uint16_t maxvoltagestepsoc; 2124 2125 uint8_t vddgfxvrmapping; 2126 uint8_t vddsocvrmapping; 2127 uint8_t vddmem0vrmapping; 2128 uint8_t vddmem1vrmapping; 2129 2130 uint8_t gfxulvphasesheddingmask; 2131 uint8_t soculvphasesheddingmask; 2132 uint8_t externalsensorpresent; 2133 uint8_t padding8_v; 2134 2135 uint16_t gfxmaxcurrent; 2136 uint8_t gfxoffset; 2137 uint8_t padding_telemetrygfx; 2138 2139 uint16_t socmaxcurrent; 2140 uint8_t socoffset; 2141 uint8_t padding_telemetrysoc; 2142 2143 uint16_t mem0maxcurrent; 2144 uint8_t mem0offset; 2145 uint8_t padding_telemetrymem0; 2146 2147 uint16_t mem1maxcurrent; 2148 uint8_t mem1offset; 2149 uint8_t padding_telemetrymem1; 2150 2151 2152 uint8_t acdcgpio; 2153 uint8_t acdcpolarity; 2154 uint8_t vr0hotgpio; 2155 uint8_t vr0hotpolarity; 2156 2157 uint8_t vr1hotgpio; 2158 uint8_t vr1hotpolarity; 2159 uint8_t padding1; 2160 uint8_t padding2; 2161 2162 2163 uint8_t ledpin0; 2164 uint8_t ledpin1; 2165 uint8_t ledpin2; 2166 uint8_t padding8_4; 2167 2168 2169 uint8_t pllgfxclkspreadenabled; 2170 uint8_t pllgfxclkspreadpercent; 2171 uint16_t pllgfxclkspreadfreq; 2172 2173 2174 uint8_t uclkspreadenabled; 2175 uint8_t uclkspreadpercent; 2176 uint16_t uclkspreadfreq; 2177 2178 2179 uint8_t fclkspreadenabled; 2180 uint8_t fclkspreadpercent; 2181 uint16_t fclkspreadfreq; 2182 2183 2184 uint8_t fllgfxclkspreadenabled; 2185 uint8_t fllgfxclkspreadpercent; 2186 uint16_t fllgfxclkspreadfreq; 2187 2188 2189 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7]; 2190 2191 2192 uint32_t boardreserved[10]; 2193}; 2194 2195enum smudpm_v4_5_i2ccontrollername_e{ 2196 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0, 2197 SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC, 2198 SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI, 2199 SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD, 2200 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0, 2201 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1, 2202 SMC_V4_5_I2C_CONTROLLER_NAME_PLX, 2203 SMC_V4_5_I2C_CONTROLLER_NAME_SPARE, 2204 SMC_V4_5_I2C_CONTROLLER_NAME_COUNT, 2205}; 2206 2207enum smudpm_v4_5_i2ccontrollerthrottler_e{ 2208 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 2209 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX, 2210 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC, 2211 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI, 2212 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD, 2213 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0, 2214 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1, 2215 SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX, 2216 SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT, 2217}; 2218 2219enum smudpm_v4_5_i2ccontrollerprotocol_e{ 2220 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0, 2221 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1, 2222 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0, 2223 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1, 2224 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0, 2225 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1, 2226 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT, 2227}; 2228 2229struct smudpm_i2c_controller_config_v2 2230{ 2231 uint8_t Enabled; 2232 uint8_t Speed; 2233 uint8_t Padding[2]; 2234 uint32_t SlaveAddress; 2235 uint8_t ControllerPort; 2236 uint8_t ControllerName; 2237 uint8_t ThermalThrotter; 2238 uint8_t I2cProtocol; 2239}; 2240 2241struct atom_smc_dpm_info_v4_5 2242{ 2243 struct atom_common_table_header table_header; 2244 // SECTION: BOARD PARAMETERS 2245 // I2C Control 2246 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 2247 2248 // SVI2 Board Parameters 2249 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2250 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2251 2252 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2253 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2254 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2255 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2256 2257 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2258 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2259 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 2260 uint8_t Padding8_V; 2261 2262 // Telemetry Settings 2263 uint16_t GfxMaxCurrent; // in Amps 2264 uint8_t GfxOffset; // in Amps 2265 uint8_t Padding_TelemetryGfx; 2266 uint16_t SocMaxCurrent; // in Amps 2267 uint8_t SocOffset; // in Amps 2268 uint8_t Padding_TelemetrySoc; 2269 2270 uint16_t Mem0MaxCurrent; // in Amps 2271 uint8_t Mem0Offset; // in Amps 2272 uint8_t Padding_TelemetryMem0; 2273 2274 uint16_t Mem1MaxCurrent; // in Amps 2275 uint8_t Mem1Offset; // in Amps 2276 uint8_t Padding_TelemetryMem1; 2277 2278 // GPIO Settings 2279 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2280 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2281 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2282 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2283 2284 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2285 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2286 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2287 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2288 2289 // LED Display Settings 2290 uint8_t LedPin0; // GPIO number for LedPin[0] 2291 uint8_t LedPin1; // GPIO number for LedPin[1] 2292 uint8_t LedPin2; // GPIO number for LedPin[2] 2293 uint8_t padding8_4; 2294 2295 // GFXCLK PLL Spread Spectrum 2296 uint8_t PllGfxclkSpreadEnabled; // on or off 2297 uint8_t PllGfxclkSpreadPercent; // Q4.4 2298 uint16_t PllGfxclkSpreadFreq; // kHz 2299 2300 // GFXCLK DFLL Spread Spectrum 2301 uint8_t DfllGfxclkSpreadEnabled; // on or off 2302 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2303 uint16_t DfllGfxclkSpreadFreq; // kHz 2304 2305 // UCLK Spread Spectrum 2306 uint8_t UclkSpreadEnabled; // on or off 2307 uint8_t UclkSpreadPercent; // Q4.4 2308 uint16_t UclkSpreadFreq; // kHz 2309 2310 // SOCCLK Spread Spectrum 2311 uint8_t SoclkSpreadEnabled; // on or off 2312 uint8_t SocclkSpreadPercent; // Q4.4 2313 uint16_t SocclkSpreadFreq; // kHz 2314 2315 // Total board power 2316 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2317 uint16_t BoardPadding; 2318 2319 // Mvdd Svi2 Div Ratio Setting 2320 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2321 2322 uint32_t BoardReserved[9]; 2323 2324}; 2325 2326struct atom_smc_dpm_info_v4_6 2327{ 2328 struct atom_common_table_header table_header; 2329 // section: board parameters 2330 uint32_t i2c_padding[3]; // old i2c control are moved to new area 2331 2332 uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 2333 uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 2334 2335 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields 2336 uint8_t vddsocvrmapping; // use vr_mapping* bitfields 2337 uint8_t vddmemvrmapping; // use vr_mapping* bitfields 2338 uint8_t boardvrmapping; // use vr_mapping* bitfields 2339 2340 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode 2341 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in) 2342 uint8_t padding8_v[2]; 2343 2344 // telemetry settings 2345 uint16_t gfxmaxcurrent; // in amps 2346 uint8_t gfxoffset; // in amps 2347 uint8_t padding_telemetrygfx; 2348 2349 uint16_t socmaxcurrent; // in amps 2350 uint8_t socoffset; // in amps 2351 uint8_t padding_telemetrysoc; 2352 2353 uint16_t memmaxcurrent; // in amps 2354 uint8_t memoffset; // in amps 2355 uint8_t padding_telemetrymem; 2356 2357 uint16_t boardmaxcurrent; // in amps 2358 uint8_t boardoffset; // in amps 2359 uint8_t padding_telemetryboardinput; 2360 2361 // gpio settings 2362 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event 2363 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event 2364 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event 2365 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event 2366 2367 // gfxclk pll spread spectrum 2368 uint8_t pllgfxclkspreadenabled; // on or off 2369 uint8_t pllgfxclkspreadpercent; // q4.4 2370 uint16_t pllgfxclkspreadfreq; // khz 2371 2372 // uclk spread spectrum 2373 uint8_t uclkspreadenabled; // on or off 2374 uint8_t uclkspreadpercent; // q4.4 2375 uint16_t uclkspreadfreq; // khz 2376 2377 // fclk spread spectrum 2378 uint8_t fclkspreadenabled; // on or off 2379 uint8_t fclkspreadpercent; // q4.4 2380 uint16_t fclkspreadfreq; // khz 2381 2382 2383 // gfxclk fll spread spectrum 2384 uint8_t fllgfxclkspreadenabled; // on or off 2385 uint8_t fllgfxclkspreadpercent; // q4.4 2386 uint16_t fllgfxclkspreadfreq; // khz 2387 2388 // i2c controller structure 2389 struct smudpm_i2c_controller_config_v2 i2ccontrollers[8]; 2390 2391 // memory section 2392 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask. 2393 2394 uint8_t drambitwidth; // for dram use only. see dram bit width type defines 2395 uint8_t paddingmem[3]; 2396 2397 // total board power 2398 uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power 2399 uint16_t boardpadding; 2400 2401 // section: xgmi training 2402 uint8_t xgmilinkspeed[4]; 2403 uint8_t xgmilinkwidth[4]; 2404 2405 uint16_t xgmifclkfreq[4]; 2406 uint16_t xgmisocvoltage[4]; 2407 2408 // reserved 2409 uint32_t boardreserved[10]; 2410}; 2411 2412struct atom_smc_dpm_info_v4_7 2413{ 2414 struct atom_common_table_header table_header; 2415 // SECTION: BOARD PARAMETERS 2416 // I2C Control 2417 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 2418 2419 // SVI2 Board Parameters 2420 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2421 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2422 2423 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2424 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2425 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2426 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2427 2428 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2429 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2430 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 2431 uint8_t Padding8_V; 2432 2433 // Telemetry Settings 2434 uint16_t GfxMaxCurrent; // in Amps 2435 uint8_t GfxOffset; // in Amps 2436 uint8_t Padding_TelemetryGfx; 2437 uint16_t SocMaxCurrent; // in Amps 2438 uint8_t SocOffset; // in Amps 2439 uint8_t Padding_TelemetrySoc; 2440 2441 uint16_t Mem0MaxCurrent; // in Amps 2442 uint8_t Mem0Offset; // in Amps 2443 uint8_t Padding_TelemetryMem0; 2444 2445 uint16_t Mem1MaxCurrent; // in Amps 2446 uint8_t Mem1Offset; // in Amps 2447 uint8_t Padding_TelemetryMem1; 2448 2449 // GPIO Settings 2450 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2451 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2452 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2453 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2454 2455 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2456 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2457 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2458 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2459 2460 // LED Display Settings 2461 uint8_t LedPin0; // GPIO number for LedPin[0] 2462 uint8_t LedPin1; // GPIO number for LedPin[1] 2463 uint8_t LedPin2; // GPIO number for LedPin[2] 2464 uint8_t padding8_4; 2465 2466 // GFXCLK PLL Spread Spectrum 2467 uint8_t PllGfxclkSpreadEnabled; // on or off 2468 uint8_t PllGfxclkSpreadPercent; // Q4.4 2469 uint16_t PllGfxclkSpreadFreq; // kHz 2470 2471 // GFXCLK DFLL Spread Spectrum 2472 uint8_t DfllGfxclkSpreadEnabled; // on or off 2473 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2474 uint16_t DfllGfxclkSpreadFreq; // kHz 2475 2476 // UCLK Spread Spectrum 2477 uint8_t UclkSpreadEnabled; // on or off 2478 uint8_t UclkSpreadPercent; // Q4.4 2479 uint16_t UclkSpreadFreq; // kHz 2480 2481 // SOCCLK Spread Spectrum 2482 uint8_t SoclkSpreadEnabled; // on or off 2483 uint8_t SocclkSpreadPercent; // Q4.4 2484 uint16_t SocclkSpreadFreq; // kHz 2485 2486 // Total board power 2487 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2488 uint16_t BoardPadding; 2489 2490 // Mvdd Svi2 Div Ratio Setting 2491 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2492 2493 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 2494 uint8_t GpioI2cScl; // Serial Clock 2495 uint8_t GpioI2cSda; // Serial Data 2496 uint16_t GpioPadding; 2497 2498 // Additional LED Display Settings 2499 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed 2500 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status 2501 uint16_t LedEnableMask; 2502 2503 // Power Limit Scalars 2504 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT] 2505 2506 uint8_t MvddUlvPhaseSheddingMask; 2507 uint8_t VddciUlvPhaseSheddingMask; 2508 uint8_t Padding8_Psi1; 2509 uint8_t Padding8_Psi2; 2510 2511 uint32_t BoardReserved[5]; 2512}; 2513 2514struct smudpm_i2c_controller_config_v3 2515{ 2516 uint8_t Enabled; 2517 uint8_t Speed; 2518 uint8_t SlaveAddress; 2519 uint8_t ControllerPort; 2520 uint8_t ControllerName; 2521 uint8_t ThermalThrotter; 2522 uint8_t I2cProtocol; 2523 uint8_t PaddingConfig; 2524}; 2525 2526struct atom_smc_dpm_info_v4_9 2527{ 2528 struct atom_common_table_header table_header; 2529 2530 //SECTION: Gaming Clocks 2531 //uint32_t GamingClk[6]; 2532 2533 // SECTION: I2C Control 2534 struct smudpm_i2c_controller_config_v3 I2cControllers[16]; 2535 2536 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 2537 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 2538 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 2539 uint8_t I2cSpare; 2540 2541 // SECTION: SVI2 Board Parameters 2542 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2543 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2544 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2545 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2546 2547 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2548 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2549 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2550 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2551 2552 // SECTION: Telemetry Settings 2553 uint16_t GfxMaxCurrent; // in Amps 2554 uint8_t GfxOffset; // in Amps 2555 uint8_t Padding_TelemetryGfx; 2556 2557 uint16_t SocMaxCurrent; // in Amps 2558 uint8_t SocOffset; // in Amps 2559 uint8_t Padding_TelemetrySoc; 2560 2561 uint16_t Mem0MaxCurrent; // in Amps 2562 uint8_t Mem0Offset; // in Amps 2563 uint8_t Padding_TelemetryMem0; 2564 2565 uint16_t Mem1MaxCurrent; // in Amps 2566 uint8_t Mem1Offset; // in Amps 2567 uint8_t Padding_TelemetryMem1; 2568 2569 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 2570 2571 // SECTION: GPIO Settings 2572 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2573 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2574 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2575 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2576 2577 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2578 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2579 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2580 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2581 2582 // LED Display Settings 2583 uint8_t LedPin0; // GPIO number for LedPin[0] 2584 uint8_t LedPin1; // GPIO number for LedPin[1] 2585 uint8_t LedPin2; // GPIO number for LedPin[2] 2586 uint8_t LedEnableMask; 2587 2588 uint8_t LedPcie; // GPIO number for PCIE results 2589 uint8_t LedError; // GPIO number for Error Cases 2590 uint8_t LedSpare1[2]; 2591 2592 // SECTION: Clock Spread Spectrum 2593 2594 // GFXCLK PLL Spread Spectrum 2595 uint8_t PllGfxclkSpreadEnabled; // on or off 2596 uint8_t PllGfxclkSpreadPercent; // Q4.4 2597 uint16_t PllGfxclkSpreadFreq; // kHz 2598 2599 // GFXCLK DFLL Spread Spectrum 2600 uint8_t DfllGfxclkSpreadEnabled; // on or off 2601 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2602 uint16_t DfllGfxclkSpreadFreq; // kHz 2603 2604 // UCLK Spread Spectrum 2605 uint8_t UclkSpreadEnabled; // on or off 2606 uint8_t UclkSpreadPercent; // Q4.4 2607 uint16_t UclkSpreadFreq; // kHz 2608 2609 // FCLK Spread Spectrum 2610 uint8_t FclkSpreadEnabled; // on or off 2611 uint8_t FclkSpreadPercent; // Q4.4 2612 uint16_t FclkSpreadFreq; // kHz 2613 2614 // Section: Memory Config 2615 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 2616 2617 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 2618 uint8_t PaddingMem1[3]; 2619 2620 // Section: Total Board Power 2621 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2622 uint16_t BoardPowerPadding; 2623 2624 // SECTION: XGMI Training 2625 uint8_t XgmiLinkSpeed [4]; 2626 uint8_t XgmiLinkWidth [4]; 2627 2628 uint16_t XgmiFclkFreq [4]; 2629 uint16_t XgmiSocVoltage [4]; 2630 2631 // SECTION: Board Reserved 2632 2633 uint32_t BoardReserved[16]; 2634 2635}; 2636 2637struct atom_smc_dpm_info_v4_10 2638{ 2639 struct atom_common_table_header table_header; 2640 2641 // SECTION: BOARD PARAMETERS 2642 // Telemetry Settings 2643 uint16_t GfxMaxCurrent; // in Amps 2644 uint8_t GfxOffset; // in Amps 2645 uint8_t Padding_TelemetryGfx; 2646 2647 uint16_t SocMaxCurrent; // in Amps 2648 uint8_t SocOffset; // in Amps 2649 uint8_t Padding_TelemetrySoc; 2650 2651 uint16_t MemMaxCurrent; // in Amps 2652 uint8_t MemOffset; // in Amps 2653 uint8_t Padding_TelemetryMem; 2654 2655 uint16_t BoardMaxCurrent; // in Amps 2656 uint8_t BoardOffset; // in Amps 2657 uint8_t Padding_TelemetryBoardInput; 2658 2659 // Platform input telemetry voltage coefficient 2660 uint32_t BoardVoltageCoeffA; // decode by /1000 2661 uint32_t BoardVoltageCoeffB; // decode by /1000 2662 2663 // GPIO Settings 2664 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2665 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2666 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2667 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2668 2669 // UCLK Spread Spectrum 2670 uint8_t UclkSpreadEnabled; // on or off 2671 uint8_t UclkSpreadPercent; // Q4.4 2672 uint16_t UclkSpreadFreq; // kHz 2673 2674 // FCLK Spread Spectrum 2675 uint8_t FclkSpreadEnabled; // on or off 2676 uint8_t FclkSpreadPercent; // Q4.4 2677 uint16_t FclkSpreadFreq; // kHz 2678 2679 // I2C Controller Structure 2680 struct smudpm_i2c_controller_config_v3 I2cControllers[8]; 2681 2682 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 2683 uint8_t GpioI2cScl; // Serial Clock 2684 uint8_t GpioI2cSda; // Serial Data 2685 uint16_t spare5; 2686 2687 uint32_t reserved[16]; 2688}; 2689 2690/* 2691 *************************************************************************** 2692 Data Table asic_profiling_info structure 2693 *************************************************************************** 2694*/ 2695struct atom_asic_profiling_info_v4_1 2696{ 2697 struct atom_common_table_header table_header; 2698 uint32_t maxvddc; 2699 uint32_t minvddc; 2700 uint32_t avfs_meannsigma_acontant0; 2701 uint32_t avfs_meannsigma_acontant1; 2702 uint32_t avfs_meannsigma_acontant2; 2703 uint16_t avfs_meannsigma_dc_tol_sigma; 2704 uint16_t avfs_meannsigma_platform_mean; 2705 uint16_t avfs_meannsigma_platform_sigma; 2706 uint32_t gb_vdroop_table_cksoff_a0; 2707 uint32_t gb_vdroop_table_cksoff_a1; 2708 uint32_t gb_vdroop_table_cksoff_a2; 2709 uint32_t gb_vdroop_table_ckson_a0; 2710 uint32_t gb_vdroop_table_ckson_a1; 2711 uint32_t gb_vdroop_table_ckson_a2; 2712 uint32_t avfsgb_fuse_table_cksoff_m1; 2713 uint32_t avfsgb_fuse_table_cksoff_m2; 2714 uint32_t avfsgb_fuse_table_cksoff_b; 2715 uint32_t avfsgb_fuse_table_ckson_m1; 2716 uint32_t avfsgb_fuse_table_ckson_m2; 2717 uint32_t avfsgb_fuse_table_ckson_b; 2718 uint16_t max_voltage_0_25mv; 2719 uint8_t enable_gb_vdroop_table_cksoff; 2720 uint8_t enable_gb_vdroop_table_ckson; 2721 uint8_t enable_gb_fuse_table_cksoff; 2722 uint8_t enable_gb_fuse_table_ckson; 2723 uint16_t psm_age_comfactor; 2724 uint8_t enable_apply_avfs_cksoff_voltage; 2725 uint8_t reserved; 2726 uint32_t dispclk2gfxclk_a; 2727 uint32_t dispclk2gfxclk_b; 2728 uint32_t dispclk2gfxclk_c; 2729 uint32_t pixclk2gfxclk_a; 2730 uint32_t pixclk2gfxclk_b; 2731 uint32_t pixclk2gfxclk_c; 2732 uint32_t dcefclk2gfxclk_a; 2733 uint32_t dcefclk2gfxclk_b; 2734 uint32_t dcefclk2gfxclk_c; 2735 uint32_t phyclk2gfxclk_a; 2736 uint32_t phyclk2gfxclk_b; 2737 uint32_t phyclk2gfxclk_c; 2738}; 2739 2740struct atom_asic_profiling_info_v4_2 { 2741 struct atom_common_table_header table_header; 2742 uint32_t maxvddc; 2743 uint32_t minvddc; 2744 uint32_t avfs_meannsigma_acontant0; 2745 uint32_t avfs_meannsigma_acontant1; 2746 uint32_t avfs_meannsigma_acontant2; 2747 uint16_t avfs_meannsigma_dc_tol_sigma; 2748 uint16_t avfs_meannsigma_platform_mean; 2749 uint16_t avfs_meannsigma_platform_sigma; 2750 uint32_t gb_vdroop_table_cksoff_a0; 2751 uint32_t gb_vdroop_table_cksoff_a1; 2752 uint32_t gb_vdroop_table_cksoff_a2; 2753 uint32_t gb_vdroop_table_ckson_a0; 2754 uint32_t gb_vdroop_table_ckson_a1; 2755 uint32_t gb_vdroop_table_ckson_a2; 2756 uint32_t avfsgb_fuse_table_cksoff_m1; 2757 uint32_t avfsgb_fuse_table_cksoff_m2; 2758 uint32_t avfsgb_fuse_table_cksoff_b; 2759 uint32_t avfsgb_fuse_table_ckson_m1; 2760 uint32_t avfsgb_fuse_table_ckson_m2; 2761 uint32_t avfsgb_fuse_table_ckson_b; 2762 uint16_t max_voltage_0_25mv; 2763 uint8_t enable_gb_vdroop_table_cksoff; 2764 uint8_t enable_gb_vdroop_table_ckson; 2765 uint8_t enable_gb_fuse_table_cksoff; 2766 uint8_t enable_gb_fuse_table_ckson; 2767 uint16_t psm_age_comfactor; 2768 uint8_t enable_apply_avfs_cksoff_voltage; 2769 uint8_t reserved; 2770 uint32_t dispclk2gfxclk_a; 2771 uint32_t dispclk2gfxclk_b; 2772 uint32_t dispclk2gfxclk_c; 2773 uint32_t pixclk2gfxclk_a; 2774 uint32_t pixclk2gfxclk_b; 2775 uint32_t pixclk2gfxclk_c; 2776 uint32_t dcefclk2gfxclk_a; 2777 uint32_t dcefclk2gfxclk_b; 2778 uint32_t dcefclk2gfxclk_c; 2779 uint32_t phyclk2gfxclk_a; 2780 uint32_t phyclk2gfxclk_b; 2781 uint32_t phyclk2gfxclk_c; 2782 uint32_t acg_gb_vdroop_table_a0; 2783 uint32_t acg_gb_vdroop_table_a1; 2784 uint32_t acg_gb_vdroop_table_a2; 2785 uint32_t acg_avfsgb_fuse_table_m1; 2786 uint32_t acg_avfsgb_fuse_table_m2; 2787 uint32_t acg_avfsgb_fuse_table_b; 2788 uint8_t enable_acg_gb_vdroop_table; 2789 uint8_t enable_acg_gb_fuse_table; 2790 uint32_t acg_dispclk2gfxclk_a; 2791 uint32_t acg_dispclk2gfxclk_b; 2792 uint32_t acg_dispclk2gfxclk_c; 2793 uint32_t acg_pixclk2gfxclk_a; 2794 uint32_t acg_pixclk2gfxclk_b; 2795 uint32_t acg_pixclk2gfxclk_c; 2796 uint32_t acg_dcefclk2gfxclk_a; 2797 uint32_t acg_dcefclk2gfxclk_b; 2798 uint32_t acg_dcefclk2gfxclk_c; 2799 uint32_t acg_phyclk2gfxclk_a; 2800 uint32_t acg_phyclk2gfxclk_b; 2801 uint32_t acg_phyclk2gfxclk_c; 2802}; 2803 2804/* 2805 *************************************************************************** 2806 Data Table multimedia_info structure 2807 *************************************************************************** 2808*/ 2809struct atom_multimedia_info_v2_1 2810{ 2811 struct atom_common_table_header table_header; 2812 uint8_t uvdip_min_ver; 2813 uint8_t uvdip_max_ver; 2814 uint8_t vceip_min_ver; 2815 uint8_t vceip_max_ver; 2816 uint16_t uvd_enc_max_input_width_pixels; 2817 uint16_t uvd_enc_max_input_height_pixels; 2818 uint16_t vce_enc_max_input_width_pixels; 2819 uint16_t vce_enc_max_input_height_pixels; 2820 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 2821 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 2822}; 2823 2824 2825/* 2826 *************************************************************************** 2827 Data Table umc_info structure 2828 *************************************************************************** 2829*/ 2830struct atom_umc_info_v3_1 2831{ 2832 struct atom_common_table_header table_header; 2833 uint32_t ucode_version; 2834 uint32_t ucode_rom_startaddr; 2835 uint32_t ucode_length; 2836 uint16_t umc_reg_init_offset; 2837 uint16_t customer_ucode_name_offset; 2838 uint16_t mclk_ss_percentage; 2839 uint16_t mclk_ss_rate_10hz; 2840 uint8_t umcip_min_ver; 2841 uint8_t umcip_max_ver; 2842 uint8_t vram_type; //enum of atom_dgpu_vram_type 2843 uint8_t umc_config; 2844 uint32_t mem_refclk_10khz; 2845}; 2846 2847// umc_info.umc_config 2848enum atom_umc_config_def { 2849 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001, 2850 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002, 2851 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004, 2852 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008, 2853 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010, 2854 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020, 2855}; 2856 2857struct atom_umc_info_v3_2 2858{ 2859 struct atom_common_table_header table_header; 2860 uint32_t ucode_version; 2861 uint32_t ucode_rom_startaddr; 2862 uint32_t ucode_length; 2863 uint16_t umc_reg_init_offset; 2864 uint16_t customer_ucode_name_offset; 2865 uint16_t mclk_ss_percentage; 2866 uint16_t mclk_ss_rate_10hz; 2867 uint8_t umcip_min_ver; 2868 uint8_t umcip_max_ver; 2869 uint8_t vram_type; //enum of atom_dgpu_vram_type 2870 uint8_t umc_config; 2871 uint32_t mem_refclk_10khz; 2872 uint32_t pstate_uclk_10khz[4]; 2873 uint16_t umcgoldenoffset; 2874 uint16_t densitygoldenoffset; 2875}; 2876 2877struct atom_umc_info_v3_3 2878{ 2879 struct atom_common_table_header table_header; 2880 uint32_t ucode_reserved; 2881 uint32_t ucode_rom_startaddr; 2882 uint32_t ucode_length; 2883 uint16_t umc_reg_init_offset; 2884 uint16_t customer_ucode_name_offset; 2885 uint16_t mclk_ss_percentage; 2886 uint16_t mclk_ss_rate_10hz; 2887 uint8_t umcip_min_ver; 2888 uint8_t umcip_max_ver; 2889 uint8_t vram_type; //enum of atom_dgpu_vram_type 2890 uint8_t umc_config; 2891 uint32_t mem_refclk_10khz; 2892 uint32_t pstate_uclk_10khz[4]; 2893 uint16_t umcgoldenoffset; 2894 uint16_t densitygoldenoffset; 2895 uint32_t umc_config1; 2896 uint32_t bist_data_startaddr; 2897 uint32_t reserved[2]; 2898}; 2899 2900enum atom_umc_config1_def { 2901 UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001, 2902 UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002, 2903 UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004, 2904 UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008, 2905 UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010, 2906 UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000, 2907}; 2908 2909/* 2910 *************************************************************************** 2911 Data Table vram_info structure 2912 *************************************************************************** 2913*/ 2914struct atom_vram_module_v9 { 2915 // Design Specific Values 2916 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2917 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2918 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 2919 uint16_t reserved[3]; 2920 uint16_t mem_voltage; // mem_voltage 2921 uint16_t vram_module_size; // Size of atom_vram_module_v9 2922 uint8_t ext_memory_id; // Current memory module ID 2923 uint8_t memory_type; // enum of atom_dgpu_vram_type 2924 uint8_t channel_num; // Number of mem. channels supported in this module 2925 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2926 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2927 uint8_t tunningset_id; // MC phy registers set per. 2928 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2929 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2930 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id 2931 uint8_t vram_rsd2; // reserved 2932 char dram_pnstring[20]; // part number end with '0'. 2933}; 2934 2935struct atom_vram_info_header_v2_3 { 2936 struct atom_common_table_header table_header; 2937 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 2938 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 2939 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2940 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2941 uint16_t dram_data_remap_tbloffset; // reserved for now 2942 uint16_t tmrs_seq_offset; // offset of HBM tmrs 2943 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2944 uint16_t vram_rsd2; 2945 uint8_t vram_module_num; // indicate number of VRAM module 2946 uint8_t umcip_min_ver; 2947 uint8_t umcip_max_ver; 2948 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2949 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2950}; 2951 2952/* 2953 *************************************************************************** 2954 Data Table vram_info v3.0 structure 2955 *************************************************************************** 2956*/ 2957struct atom_vram_module_v3_0 { 2958 uint8_t density; 2959 uint8_t tunningset_id; 2960 uint8_t ext_memory_id; 2961 uint8_t dram_vendor_id; 2962 uint16_t dram_info_offset; 2963 uint16_t mem_tuning_offset; 2964 uint16_t tmrs_seq_offset; 2965 uint16_t reserved1; 2966 uint32_t dram_size_per_ch; 2967 uint32_t reserved[3]; 2968 char dram_pnstring[40]; 2969}; 2970 2971struct atom_vram_info_header_v3_0 { 2972 struct atom_common_table_header table_header; 2973 uint16_t mem_tuning_table_offset; 2974 uint16_t dram_info_table_offset; 2975 uint16_t tmrs_table_offset; 2976 uint16_t mc_init_table_offset; 2977 uint16_t dram_data_remap_table_offset; 2978 uint16_t umc_emuinittable_offset; 2979 uint16_t reserved_sub_table_offset[2]; 2980 uint8_t vram_module_num; 2981 uint8_t umcip_min_ver; 2982 uint8_t umcip_max_ver; 2983 uint8_t mc_phy_tile_num; 2984 uint8_t memory_type; 2985 uint8_t channel_num; 2986 uint8_t channel_width; 2987 uint8_t reserved1; 2988 uint32_t channel_enable; 2989 uint32_t channel1_enable; 2990 uint32_t feature_enable; 2991 uint32_t feature1_enable; 2992 uint32_t hardcode_mem_size; 2993 uint32_t reserved4[4]; 2994 struct atom_vram_module_v3_0 vram_module[8]; 2995}; 2996 2997struct atom_umc_register_addr_info{ 2998 uint32_t umc_register_addr:24; 2999 uint32_t umc_reg_type_ind:1; 3000 uint32_t umc_reg_rsvd:7; 3001}; 3002 3003//atom_umc_register_addr_info. 3004enum atom_umc_register_addr_info_flag{ 3005 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01, 3006}; 3007 3008union atom_umc_register_addr_info_access 3009{ 3010 struct atom_umc_register_addr_info umc_reg_addr; 3011 uint32_t u32umc_reg_addr; 3012}; 3013 3014struct atom_umc_reg_setting_id_config{ 3015 uint32_t memclockrange:24; 3016 uint32_t mem_blk_id:8; 3017}; 3018 3019union atom_umc_reg_setting_id_config_access 3020{ 3021 struct atom_umc_reg_setting_id_config umc_id_access; 3022 uint32_t u32umc_id_access; 3023}; 3024 3025struct atom_umc_reg_setting_data_block{ 3026 union atom_umc_reg_setting_id_config_access block_id; 3027 uint32_t u32umc_reg_data[1]; 3028}; 3029 3030struct atom_umc_init_reg_block{ 3031 uint16_t umc_reg_num; 3032 uint16_t reserved; 3033 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num; 3034 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1]; 3035}; 3036 3037struct atom_vram_module_v10 { 3038 // Design Specific Values 3039 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 3040 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 3041 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 3042 uint16_t reserved[3]; 3043 uint16_t mem_voltage; // mem_voltage 3044 uint16_t vram_module_size; // Size of atom_vram_module_v9 3045 uint8_t ext_memory_id; // Current memory module ID 3046 uint8_t memory_type; // enum of atom_dgpu_vram_type 3047 uint8_t channel_num; // Number of mem. channels supported in this module 3048 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 3049 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 3050 uint8_t tunningset_id; // MC phy registers set per 3051 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 3052 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 3053 uint8_t vram_flags; // bit0= bankgroup enable 3054 uint8_t vram_rsd2; // reserved 3055 uint16_t gddr6_mr10; // gddr6 mode register10 value 3056 uint16_t gddr6_mr1; // gddr6 mode register1 value 3057 uint16_t gddr6_mr2; // gddr6 mode register2 value 3058 uint16_t gddr6_mr7; // gddr6 mode register7 value 3059 char dram_pnstring[20]; // part number end with '0' 3060}; 3061 3062struct atom_vram_info_header_v2_4 { 3063 struct atom_common_table_header table_header; 3064 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 3065 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 3066 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 3067 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 3068 uint16_t dram_data_remap_tbloffset; // reserved for now 3069 uint16_t reserved; // offset of reserved 3070 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 3071 uint16_t vram_rsd2; 3072 uint8_t vram_module_num; // indicate number of VRAM module 3073 uint8_t umcip_min_ver; 3074 uint8_t umcip_max_ver; 3075 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 3076 struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 3077}; 3078 3079struct atom_vram_module_v11 { 3080 // Design Specific Values 3081 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 3082 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 3083 uint16_t mem_voltage; // mem_voltage 3084 uint16_t vram_module_size; // Size of atom_vram_module_v9 3085 uint8_t ext_memory_id; // Current memory module ID 3086 uint8_t memory_type; // enum of atom_dgpu_vram_type 3087 uint8_t channel_num; // Number of mem. channels supported in this module 3088 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 3089 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 3090 uint8_t tunningset_id; // MC phy registers set per. 3091 uint16_t reserved[4]; // reserved 3092 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 3093 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 3094 uint8_t vram_flags; // bit0= bankgroup enable 3095 uint8_t vram_rsd2; // reserved 3096 uint16_t gddr6_mr10; // gddr6 mode register10 value 3097 uint16_t gddr6_mr0; // gddr6 mode register0 value 3098 uint16_t gddr6_mr1; // gddr6 mode register1 value 3099 uint16_t gddr6_mr2; // gddr6 mode register2 value 3100 uint16_t gddr6_mr4; // gddr6 mode register4 value 3101 uint16_t gddr6_mr7; // gddr6 mode register7 value 3102 uint16_t gddr6_mr8; // gddr6 mode register8 value 3103 char dram_pnstring[40]; // part number end with '0'. 3104}; 3105 3106struct atom_gddr6_ac_timing_v2_5 { 3107 uint32_t u32umc_id_access; 3108 uint8_t RL; 3109 uint8_t WL; 3110 uint8_t tRAS; 3111 uint8_t tRC; 3112 3113 uint16_t tREFI; 3114 uint8_t tRFC; 3115 uint8_t tRFCpb; 3116 3117 uint8_t tRREFD; 3118 uint8_t tRCDRD; 3119 uint8_t tRCDWR; 3120 uint8_t tRP; 3121 3122 uint8_t tRRDS; 3123 uint8_t tRRDL; 3124 uint8_t tWR; 3125 uint8_t tWTRS; 3126 3127 uint8_t tWTRL; 3128 uint8_t tFAW; 3129 uint8_t tCCDS; 3130 uint8_t tCCDL; 3131 3132 uint8_t tCRCRL; 3133 uint8_t tCRCWL; 3134 uint8_t tCKE; 3135 uint8_t tCKSRE; 3136 3137 uint8_t tCKSRX; 3138 uint8_t tRTPS; 3139 uint8_t tRTPL; 3140 uint8_t tMRD; 3141 3142 uint8_t tMOD; 3143 uint8_t tXS; 3144 uint8_t tXHP; 3145 uint8_t tXSMRS; 3146 3147 uint32_t tXSH; 3148 3149 uint8_t tPD; 3150 uint8_t tXP; 3151 uint8_t tCPDED; 3152 uint8_t tACTPDE; 3153 3154 uint8_t tPREPDE; 3155 uint8_t tREFPDE; 3156 uint8_t tMRSPDEN; 3157 uint8_t tRDSRE; 3158 3159 uint8_t tWRSRE; 3160 uint8_t tPPD; 3161 uint8_t tCCDMW; 3162 uint8_t tWTRTR; 3163 3164 uint8_t tLTLTR; 3165 uint8_t tREFTR; 3166 uint8_t VNDR; 3167 uint8_t reserved[9]; 3168}; 3169 3170struct atom_gddr6_bit_byte_remap { 3171 uint32_t dphy_byteremap; //mmUMC_DPHY_ByteRemap 3172 uint32_t dphy_bitremap0; //mmUMC_DPHY_BitRemap0 3173 uint32_t dphy_bitremap1; //mmUMC_DPHY_BitRemap1 3174 uint32_t dphy_bitremap2; //mmUMC_DPHY_BitRemap2 3175 uint32_t aphy_bitremap0; //mmUMC_APHY_BitRemap0 3176 uint32_t aphy_bitremap1; //mmUMC_APHY_BitRemap1 3177 uint32_t phy_dram; //mmUMC_PHY_DRAM 3178}; 3179 3180struct atom_gddr6_dram_data_remap { 3181 uint32_t table_size; 3182 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK 3183 struct atom_gddr6_bit_byte_remap bit_byte_remap[16]; 3184}; 3185 3186struct atom_vram_info_header_v2_5 { 3187 struct atom_common_table_header table_header; 3188 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings 3189 uint16_t gddr6_ac_timing_offset; // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings 3190 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 3191 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 3192 uint16_t dram_data_remap_tbloffset; // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping 3193 uint16_t reserved; // offset of reserved 3194 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 3195 uint16_t strobe_mode_patch_tbloffset; // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings 3196 uint8_t vram_module_num; // indicate number of VRAM module 3197 uint8_t umcip_min_ver; 3198 uint8_t umcip_max_ver; 3199 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 3200 struct atom_vram_module_v11 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 3201}; 3202 3203struct atom_vram_info_header_v2_6 { 3204 struct atom_common_table_header table_header; 3205 uint16_t mem_adjust_tbloffset; 3206 uint16_t mem_clk_patch_tbloffset; 3207 uint16_t mc_adjust_pertile_tbloffset; 3208 uint16_t mc_phyinit_tbloffset; 3209 uint16_t dram_data_remap_tbloffset; 3210 uint16_t tmrs_seq_offset; 3211 uint16_t post_ucode_init_offset; 3212 uint16_t vram_rsd2; 3213 uint8_t vram_module_num; 3214 uint8_t umcip_min_ver; 3215 uint8_t umcip_max_ver; 3216 uint8_t mc_phy_tile_num; 3217 struct atom_vram_module_v9 vram_module[16]; 3218}; 3219/* 3220 *************************************************************************** 3221 Data Table voltageobject_info structure 3222 *************************************************************************** 3223*/ 3224struct atom_i2c_data_entry 3225{ 3226 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit 3227 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit 3228}; 3229 3230struct atom_voltage_object_header_v4{ 3231 uint8_t voltage_type; //enum atom_voltage_type 3232 uint8_t voltage_mode; //enum atom_voltage_object_mode 3233 uint16_t object_size; //Size of Object 3234}; 3235 3236// atom_voltage_object_header_v4.voltage_mode 3237enum atom_voltage_object_mode 3238{ 3239 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4 3240 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4 3241 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4 3242 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4 3243 VOLTAGE_OBJ_EVV = 8, 3244 VOLTAGE_OBJ_MERGED_POWER = 9, 3245}; 3246 3247struct atom_i2c_voltage_object_v4 3248{ 3249 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3250 uint8_t regulator_id; //Indicate Voltage Regulator Id 3251 uint8_t i2c_id; 3252 uint8_t i2c_slave_addr; 3253 uint8_t i2c_control_offset; 3254 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data 3255 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. 3256 uint8_t reserved[2]; 3257 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff 3258}; 3259 3260// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 3261enum atom_i2c_voltage_control_flag 3262{ 3263 VOLTAGE_DATA_ONE_BYTE = 0, 3264 VOLTAGE_DATA_TWO_BYTE = 1, 3265}; 3266 3267 3268struct atom_voltage_gpio_map_lut 3269{ 3270 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register 3271 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV 3272}; 3273 3274struct atom_gpio_voltage_object_v4 3275{ 3276 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 3277 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode 3278 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table 3279 uint8_t phase_delay_us; // phase delay in unit of micro second 3280 uint8_t reserved; 3281 uint32_t gpio_mask_val; // GPIO Mask value 3282 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1]; 3283}; 3284 3285struct atom_svid2_voltage_object_v4 3286{ 3287 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2 3288 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable 3289 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold 3290 uint8_t psi0_enable; // 3291 uint8_t maxvstep; 3292 uint8_t telemetry_offset; 3293 uint8_t telemetry_gain; 3294 uint16_t reserved1; 3295}; 3296 3297struct atom_merged_voltage_object_v4 3298{ 3299 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 3300 uint8_t merged_powerrail_type; //enum atom_voltage_type 3301 uint8_t reserved[3]; 3302}; 3303 3304union atom_voltage_object_v4{ 3305 struct atom_gpio_voltage_object_v4 gpio_voltage_obj; 3306 struct atom_i2c_voltage_object_v4 i2c_voltage_obj; 3307 struct atom_svid2_voltage_object_v4 svid2_voltage_obj; 3308 struct atom_merged_voltage_object_v4 merged_voltage_obj; 3309}; 3310 3311struct atom_voltage_objects_info_v4_1 3312{ 3313 struct atom_common_table_header table_header; 3314 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control 3315}; 3316 3317 3318/* 3319 *************************************************************************** 3320 All Command Function structure definition 3321 *************************************************************************** 3322*/ 3323 3324/* 3325 *************************************************************************** 3326 Structures used by asic_init 3327 *************************************************************************** 3328*/ 3329 3330struct asic_init_engine_parameters 3331{ 3332 uint32_t sclkfreqin10khz:24; 3333 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */ 3334}; 3335 3336struct asic_init_mem_parameters 3337{ 3338 uint32_t mclkfreqin10khz:24; 3339 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */ 3340}; 3341 3342struct asic_init_parameters_v2_1 3343{ 3344 struct asic_init_engine_parameters engineparam; 3345 struct asic_init_mem_parameters memparam; 3346}; 3347 3348struct asic_init_ps_allocation_v2_1 3349{ 3350 struct asic_init_parameters_v2_1 param; 3351 uint32_t reserved[16]; 3352}; 3353 3354 3355enum atom_asic_init_engine_flag 3356{ 3357 b3NORMAL_ENGINE_INIT = 0, 3358 b3SRIOV_SKIP_ASIC_INIT = 0x02, 3359 b3SRIOV_LOAD_UCODE = 0x40, 3360}; 3361 3362enum atom_asic_init_mem_flag 3363{ 3364 b3NORMAL_MEM_INIT = 0, 3365 b3DRAM_SELF_REFRESH_EXIT =0x20, 3366}; 3367 3368/* 3369 *************************************************************************** 3370 Structures used by setengineclock 3371 *************************************************************************** 3372*/ 3373 3374struct set_engine_clock_parameters_v2_1 3375{ 3376 uint32_t sclkfreqin10khz:24; 3377 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 3378 uint32_t reserved[10]; 3379}; 3380 3381struct set_engine_clock_ps_allocation_v2_1 3382{ 3383 struct set_engine_clock_parameters_v2_1 clockinfo; 3384 uint32_t reserved[10]; 3385}; 3386 3387 3388enum atom_set_engine_mem_clock_flag 3389{ 3390 b3NORMAL_CHANGE_CLOCK = 0, 3391 b3FIRST_TIME_CHANGE_CLOCK = 0x08, 3392 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result 3393}; 3394 3395/* 3396 *************************************************************************** 3397 Structures used by getengineclock 3398 *************************************************************************** 3399*/ 3400struct get_engine_clock_parameter 3401{ 3402 uint32_t sclk_10khz; // current engine speed in 10KHz unit 3403 uint32_t reserved; 3404}; 3405 3406/* 3407 *************************************************************************** 3408 Structures used by setmemoryclock 3409 *************************************************************************** 3410*/ 3411struct set_memory_clock_parameters_v2_1 3412{ 3413 uint32_t mclkfreqin10khz:24; 3414 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 3415 uint32_t reserved[10]; 3416}; 3417 3418struct set_memory_clock_ps_allocation_v2_1 3419{ 3420 struct set_memory_clock_parameters_v2_1 clockinfo; 3421 uint32_t reserved[10]; 3422}; 3423 3424 3425/* 3426 *************************************************************************** 3427 Structures used by getmemoryclock 3428 *************************************************************************** 3429*/ 3430struct get_memory_clock_parameter 3431{ 3432 uint32_t mclk_10khz; // current engine speed in 10KHz unit 3433 uint32_t reserved; 3434}; 3435 3436 3437 3438/* 3439 *************************************************************************** 3440 Structures used by setvoltage 3441 *************************************************************************** 3442*/ 3443 3444struct set_voltage_parameters_v1_4 3445{ 3446 uint8_t voltagetype; /* enum atom_voltage_type */ 3447 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */ 3448 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */ 3449}; 3450 3451//set_voltage_parameters_v2_1.voltagemode 3452enum atom_set_voltage_command{ 3453 ATOM_SET_VOLTAGE = 0, 3454 ATOM_INIT_VOLTAGE_REGULATOR = 3, 3455 ATOM_SET_VOLTAGE_PHASE = 4, 3456 ATOM_GET_LEAKAGE_ID = 8, 3457}; 3458 3459struct set_voltage_ps_allocation_v1_4 3460{ 3461 struct set_voltage_parameters_v1_4 setvoltageparam; 3462 uint32_t reserved[10]; 3463}; 3464 3465 3466/* 3467 *************************************************************************** 3468 Structures used by computegpuclockparam 3469 *************************************************************************** 3470*/ 3471 3472//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 3473enum atom_gpu_clock_type 3474{ 3475 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00, 3476 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01, 3477 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02, 3478}; 3479 3480struct compute_gpu_clock_input_parameter_v1_8 3481{ 3482 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 3483 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type 3484 uint32_t reserved[5]; 3485}; 3486 3487 3488struct compute_gpu_clock_output_parameter_v1_8 3489{ 3490 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 3491 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly 3492 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac 3493 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac 3494 uint16_t pll_ss_slew_frac; 3495 uint8_t pll_ss_enable; 3496 uint8_t reserved; 3497 uint32_t reserved1[2]; 3498}; 3499 3500 3501 3502/* 3503 *************************************************************************** 3504 Structures used by ReadEfuseValue 3505 *************************************************************************** 3506*/ 3507 3508struct read_efuse_input_parameters_v3_1 3509{ 3510 uint16_t efuse_start_index; 3511 uint8_t reserved; 3512 uint8_t bitslen; 3513}; 3514 3515// ReadEfuseValue input/output parameter 3516union read_efuse_value_parameters_v3_1 3517{ 3518 struct read_efuse_input_parameters_v3_1 efuse_info; 3519 uint32_t efusevalue; 3520}; 3521 3522 3523/* 3524 *************************************************************************** 3525 Structures used by getsmuclockinfo 3526 *************************************************************************** 3527*/ 3528struct atom_get_smu_clock_info_parameters_v3_1 3529{ 3530 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 3531 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 3532 uint8_t command; // enum of atom_get_smu_clock_info_command 3533 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 3534}; 3535 3536enum atom_get_smu_clock_info_command 3537{ 3538 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0, 3539 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1, 3540 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2, 3541}; 3542 3543enum atom_smu9_syspll0_clock_id 3544{ 3545 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK 3546 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK) 3547 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3548 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 3549 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK 3550 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK 3551 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK 3552 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK 3553 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK 3554 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK 3555 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK 3556}; 3557 3558enum atom_smu11_syspll_id { 3559 SMU11_SYSPLL0_ID = 0, 3560 SMU11_SYSPLL1_0_ID = 1, 3561 SMU11_SYSPLL1_1_ID = 2, 3562 SMU11_SYSPLL1_2_ID = 3, 3563 SMU11_SYSPLL2_ID = 4, 3564 SMU11_SYSPLL3_0_ID = 5, 3565 SMU11_SYSPLL3_1_ID = 6, 3566}; 3567 3568enum atom_smu11_syspll0_clock_id { 3569 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK 3570 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 3571 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3572 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK 3573 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK 3574 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK 3575}; 3576 3577enum atom_smu11_syspll1_0_clock_id { 3578 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a 3579}; 3580 3581enum atom_smu11_syspll1_1_clock_id { 3582 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b 3583}; 3584 3585enum atom_smu11_syspll1_2_clock_id { 3586 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK 3587}; 3588 3589enum atom_smu11_syspll2_clock_id { 3590 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK 3591}; 3592 3593enum atom_smu11_syspll3_0_clock_id { 3594 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK 3595 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK 3596 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK 3597}; 3598 3599enum atom_smu11_syspll3_1_clock_id { 3600 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK 3601 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK 3602 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK 3603}; 3604 3605enum atom_smu12_syspll_id { 3606 SMU12_SYSPLL0_ID = 0, 3607 SMU12_SYSPLL1_ID = 1, 3608 SMU12_SYSPLL2_ID = 2, 3609 SMU12_SYSPLL3_0_ID = 3, 3610 SMU12_SYSPLL3_1_ID = 4, 3611}; 3612 3613enum atom_smu12_syspll0_clock_id { 3614 SMU12_SYSPLL0_SMNCLK_ID = 0, // SOCCLK 3615 SMU12_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 3616 SMU12_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3617 SMU12_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 3618 SMU12_SYSPLL0_MP2CLK_ID = 4, // MP2CLK 3619 SMU12_SYSPLL0_VCLK_ID = 5, // VCLK 3620 SMU12_SYSPLL0_LCLK_ID = 6, // LCLK 3621 SMU12_SYSPLL0_DCLK_ID = 7, // DCLK 3622 SMU12_SYSPLL0_ACLK_ID = 8, // ACLK 3623 SMU12_SYSPLL0_ISPCLK_ID = 9, // ISPCLK 3624 SMU12_SYSPLL0_SHUBCLK_ID = 10, // SHUBCLK 3625}; 3626 3627enum atom_smu12_syspll1_clock_id { 3628 SMU12_SYSPLL1_DISPCLK_ID = 0, // DISPCLK 3629 SMU12_SYSPLL1_DPPCLK_ID = 1, // DPPCLK 3630 SMU12_SYSPLL1_DPREFCLK_ID = 2, // DPREFCLK 3631 SMU12_SYSPLL1_DCFCLK_ID = 3, // DCFCLK 3632}; 3633 3634enum atom_smu12_syspll2_clock_id { 3635 SMU12_SYSPLL2_Pre_GFXCLK_ID = 0, // Pre_GFXCLK 3636}; 3637 3638enum atom_smu12_syspll3_0_clock_id { 3639 SMU12_SYSPLL3_0_FCLK_ID = 0, // FCLK 3640}; 3641 3642enum atom_smu12_syspll3_1_clock_id { 3643 SMU12_SYSPLL3_1_UMCCLK_ID = 0, // UMCCLK 3644}; 3645 3646struct atom_get_smu_clock_info_output_parameters_v3_1 3647{ 3648 union { 3649 uint32_t smu_clock_freq_hz; 3650 uint32_t syspllvcofreq_10khz; 3651 uint32_t sysspllrefclk_10khz; 3652 }atom_smu_outputclkfreq; 3653}; 3654 3655 3656 3657/* 3658 *************************************************************************** 3659 Structures used by dynamicmemorysettings 3660 *************************************************************************** 3661*/ 3662 3663enum atom_dynamic_memory_setting_command 3664{ 3665 COMPUTE_MEMORY_PLL_PARAM = 1, 3666 COMPUTE_ENGINE_PLL_PARAM = 2, 3667 ADJUST_MC_SETTING_PARAM = 3, 3668}; 3669 3670/* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */ 3671struct dynamic_mclk_settings_parameters_v2_1 3672{ 3673 uint32_t mclk_10khz:24; //Input= target mclk 3674 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3675 uint32_t reserved; 3676}; 3677 3678/* when command = COMPUTE_ENGINE_PLL_PARAM */ 3679struct dynamic_sclk_settings_parameters_v2_1 3680{ 3681 uint32_t sclk_10khz:24; //Input= target mclk 3682 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3683 uint32_t mclk_10khz; 3684 uint32_t reserved; 3685}; 3686 3687union dynamic_memory_settings_parameters_v2_1 3688{ 3689 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting; 3690 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; 3691}; 3692 3693 3694 3695/* 3696 *************************************************************************** 3697 Structures used by memorytraining 3698 *************************************************************************** 3699*/ 3700 3701enum atom_umc6_0_ucode_function_call_enum_id 3702{ 3703 UMC60_UCODE_FUNC_ID_REINIT = 0, 3704 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1, 3705 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2, 3706}; 3707 3708 3709struct memory_training_parameters_v2_1 3710{ 3711 uint8_t ucode_func_id; 3712 uint8_t ucode_reserved[3]; 3713 uint32_t reserved[5]; 3714}; 3715 3716 3717/* 3718 *************************************************************************** 3719 Structures used by setpixelclock 3720 *************************************************************************** 3721*/ 3722 3723struct set_pixel_clock_parameter_v1_7 3724{ 3725 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 3726 3727 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 3728 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, 3729 // indicate which graphic encoder will be used. 3730 uint8_t encoder_mode; // Encoder mode: 3731 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info 3732 uint8_t crtc_id; // enum of atom_crtc_def 3733 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio 3734 uint8_t reserved1[2]; 3735 uint32_t reserved2; 3736}; 3737 3738//ucMiscInfo 3739enum atom_set_pixel_clock_v1_7_misc_info 3740{ 3741 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01, 3742 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02, 3743 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04, 3744 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08, 3745 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30, 3746 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00, 3747 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10, 3748 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20, 3749 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, 3750 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40, 3751 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80, 3752}; 3753 3754/* deep_color_ratio */ 3755enum atom_set_pixel_clock_v1_7_deepcolor_ratio 3756{ 3757 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 3758 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 3759 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 3760 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 3761}; 3762 3763/* 3764 *************************************************************************** 3765 Structures used by setdceclock 3766 *************************************************************************** 3767*/ 3768 3769// SetDCEClock input parameter for DCE11.2( ELM and BF ) and above 3770struct set_dce_clock_parameters_v2_1 3771{ 3772 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 3773 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 3774 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 3775 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 3776 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 3777}; 3778 3779//ucDCEClkType 3780enum atom_set_dce_clock_clock_type 3781{ 3782 DCE_CLOCK_TYPE_DISPCLK = 0, 3783 DCE_CLOCK_TYPE_DPREFCLK = 1, 3784 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock 3785}; 3786 3787//ucDCEClkFlag when ucDCEClkType == DPREFCLK 3788enum atom_set_dce_clock_dprefclk_flag 3789{ 3790 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03, 3791 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00, 3792 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01, 3793 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02, 3794 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03, 3795}; 3796 3797//ucDCEClkFlag when ucDCEClkType == PIXCLK 3798enum atom_set_dce_clock_pixclk_flag 3799{ 3800 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03, 3801 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 3802 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 3803 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 3804 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 3805 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04, 3806}; 3807 3808struct set_dce_clock_ps_allocation_v2_1 3809{ 3810 struct set_dce_clock_parameters_v2_1 param; 3811 uint32_t ulReserved[2]; 3812}; 3813 3814 3815/****************************************************************************/ 3816// Structures used by BlankCRTC 3817/****************************************************************************/ 3818struct blank_crtc_parameters 3819{ 3820 uint8_t crtc_id; // enum atom_crtc_def 3821 uint8_t blanking; // enum atom_blank_crtc_command 3822 uint16_t reserved; 3823 uint32_t reserved1; 3824}; 3825 3826enum atom_blank_crtc_command 3827{ 3828 ATOM_BLANKING = 1, 3829 ATOM_BLANKING_OFF = 0, 3830}; 3831 3832/****************************************************************************/ 3833// Structures used by enablecrtc 3834/****************************************************************************/ 3835struct enable_crtc_parameters 3836{ 3837 uint8_t crtc_id; // enum atom_crtc_def 3838 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 3839 uint8_t padding[2]; 3840}; 3841 3842 3843/****************************************************************************/ 3844// Structure used by EnableDispPowerGating 3845/****************************************************************************/ 3846struct enable_disp_power_gating_parameters_v2_1 3847{ 3848 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ... 3849 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 3850 uint8_t padding[2]; 3851}; 3852 3853struct enable_disp_power_gating_ps_allocation 3854{ 3855 struct enable_disp_power_gating_parameters_v2_1 param; 3856 uint32_t ulReserved[4]; 3857}; 3858 3859/****************************************************************************/ 3860// Structure used in setcrtc_usingdtdtiming 3861/****************************************************************************/ 3862struct set_crtc_using_dtd_timing_parameters 3863{ 3864 uint16_t h_size; 3865 uint16_t h_blanking_time; 3866 uint16_t v_size; 3867 uint16_t v_blanking_time; 3868 uint16_t h_syncoffset; 3869 uint16_t h_syncwidth; 3870 uint16_t v_syncoffset; 3871 uint16_t v_syncwidth; 3872 uint16_t modemiscinfo; 3873 uint8_t h_border; 3874 uint8_t v_border; 3875 uint8_t crtc_id; // enum atom_crtc_def 3876 uint8_t encoder_mode; // atom_encode_mode_def 3877 uint8_t padding[2]; 3878}; 3879 3880 3881/****************************************************************************/ 3882// Structures used by processi2cchanneltransaction 3883/****************************************************************************/ 3884struct process_i2c_channel_transaction_parameters 3885{ 3886 uint8_t i2cspeed_khz; 3887 union { 3888 uint8_t regindex; 3889 uint8_t status; /* enum atom_process_i2c_flag */ 3890 } regind_status; 3891 uint16_t i2c_data_out; 3892 uint8_t flag; /* enum atom_process_i2c_status */ 3893 uint8_t trans_bytes; 3894 uint8_t slave_addr; 3895 uint8_t i2c_id; 3896}; 3897 3898//ucFlag 3899enum atom_process_i2c_flag 3900{ 3901 HW_I2C_WRITE = 1, 3902 HW_I2C_READ = 0, 3903 I2C_2BYTE_ADDR = 0x02, 3904 HW_I2C_SMBUS_BYTE_WR = 0x04, 3905}; 3906 3907//status 3908enum atom_process_i2c_status 3909{ 3910 HW_ASSISTED_I2C_STATUS_FAILURE =2, 3911 HW_ASSISTED_I2C_STATUS_SUCCESS =1, 3912}; 3913 3914 3915/****************************************************************************/ 3916// Structures used by processauxchanneltransaction 3917/****************************************************************************/ 3918 3919struct process_aux_channel_transaction_parameters_v1_2 3920{ 3921 uint16_t aux_request; 3922 uint16_t dataout; 3923 uint8_t channelid; 3924 union { 3925 uint8_t reply_status; 3926 uint8_t aux_delay; 3927 } aux_status_delay; 3928 uint8_t dataout_len; 3929 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 3930}; 3931 3932 3933/****************************************************************************/ 3934// Structures used by selectcrtc_source 3935/****************************************************************************/ 3936 3937struct select_crtc_source_parameters_v2_3 3938{ 3939 uint8_t crtc_id; // enum atom_crtc_def 3940 uint8_t encoder_id; // enum atom_dig_def 3941 uint8_t encode_mode; // enum atom_encode_mode_def 3942 uint8_t dst_bpc; // enum atom_panel_bit_per_color 3943}; 3944 3945 3946/****************************************************************************/ 3947// Structures used by digxencodercontrol 3948/****************************************************************************/ 3949 3950// ucAction: 3951enum atom_dig_encoder_control_action 3952{ 3953 ATOM_ENCODER_CMD_DISABLE_DIG = 0, 3954 ATOM_ENCODER_CMD_ENABLE_DIG = 1, 3955 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08, 3956 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09, 3957 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a, 3958 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13, 3959 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b, 3960 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c, 3961 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d, 3962 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10, 3963 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14, 3964 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, 3965 ATOM_ENCODER_CMD_LINK_SETUP = 0x11, 3966 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12, 3967}; 3968 3969//define ucPanelMode 3970enum atom_dig_encoder_control_panelmode 3971{ 3972 DP_PANEL_MODE_DISABLE = 0x00, 3973 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01, 3974 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11, 3975}; 3976 3977//ucDigId 3978enum atom_dig_encoder_control_v5_digid 3979{ 3980 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00, 3981 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01, 3982 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02, 3983 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03, 3984 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04, 3985 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05, 3986 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06, 3987 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07, 3988}; 3989 3990struct dig_encoder_stream_setup_parameters_v1_5 3991{ 3992 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3993 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP 3994 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 3995 uint8_t lanenum; // Lane number 3996 uint32_t pclk_10khz; // Pixel Clock in 10Khz 3997 uint8_t bitpercolor; 3998 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 3999 uint8_t reserved[2]; 4000}; 4001 4002struct dig_encoder_link_setup_parameters_v1_5 4003{ 4004 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4005 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP 4006 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 4007 uint8_t lanenum; // Lane number 4008 uint8_t symclk_10khz; // Symbol Clock in 10Khz 4009 uint8_t hpd_sel; 4010 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 4011 uint8_t reserved[2]; 4012}; 4013 4014struct dp_panel_mode_set_parameters_v1_5 4015{ 4016 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4017 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP 4018 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode 4019 uint8_t reserved1; 4020 uint32_t reserved2[2]; 4021}; 4022 4023struct dig_encoder_generic_cmd_parameters_v1_5 4024{ 4025 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4026 uint8_t action; // = rest of generic encoder command which does not carry any parameters 4027 uint8_t reserved1[2]; 4028 uint32_t reserved2[2]; 4029}; 4030 4031union dig_encoder_control_parameters_v1_5 4032{ 4033 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param; 4034 struct dig_encoder_stream_setup_parameters_v1_5 stream_param; 4035 struct dig_encoder_link_setup_parameters_v1_5 link_param; 4036 struct dp_panel_mode_set_parameters_v1_5 dppanel_param; 4037}; 4038 4039/* 4040 *************************************************************************** 4041 Structures used by dig1transmittercontrol 4042 *************************************************************************** 4043*/ 4044struct dig_transmitter_control_parameters_v1_6 4045{ 4046 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 4047 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx 4048 union { 4049 uint8_t digmode; // enum atom_encode_mode_def 4050 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 4051 } mode_laneset; 4052 uint8_t lanenum; // Lane number 1, 2, 4, 8 4053 uint32_t symclk_10khz; // Symbol Clock in 10Khz 4054 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 4055 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 4056 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h 4057 uint8_t reserved; 4058 uint32_t reserved1; 4059}; 4060 4061struct dig_transmitter_control_ps_allocation_v1_6 4062{ 4063 struct dig_transmitter_control_parameters_v1_6 param; 4064 uint32_t reserved[4]; 4065}; 4066 4067//ucAction 4068enum atom_dig_transmitter_control_action 4069{ 4070 ATOM_TRANSMITTER_ACTION_DISABLE = 0, 4071 ATOM_TRANSMITTER_ACTION_ENABLE = 1, 4072 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2, 4073 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3, 4074 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4, 4075 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5, 4076 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6, 4077 ATOM_TRANSMITTER_ACTION_INIT = 7, 4078 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8, 4079 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9, 4080 ATOM_TRANSMITTER_ACTION_SETUP = 10, 4081 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11, 4082 ATOM_TRANSMITTER_ACTION_POWER_ON = 12, 4083 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13, 4084}; 4085 4086// digfe_sel 4087enum atom_dig_transmitter_control_digfe_sel 4088{ 4089 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01, 4090 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02, 4091 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04, 4092 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08, 4093 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10, 4094 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20, 4095 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40, 4096}; 4097 4098 4099//ucHPDSel 4100enum atom_dig_transmitter_control_hpd_sel 4101{ 4102 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00, 4103 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01, 4104 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02, 4105 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03, 4106 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04, 4107 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05, 4108 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06, 4109}; 4110 4111// ucDPLaneSet 4112enum atom_dig_transmitter_control_dplaneset 4113{ 4114 DP_LANE_SET__0DB_0_4V = 0x00, 4115 DP_LANE_SET__0DB_0_6V = 0x01, 4116 DP_LANE_SET__0DB_0_8V = 0x02, 4117 DP_LANE_SET__0DB_1_2V = 0x03, 4118 DP_LANE_SET__3_5DB_0_4V = 0x08, 4119 DP_LANE_SET__3_5DB_0_6V = 0x09, 4120 DP_LANE_SET__3_5DB_0_8V = 0x0a, 4121 DP_LANE_SET__6DB_0_4V = 0x10, 4122 DP_LANE_SET__6DB_0_6V = 0x11, 4123 DP_LANE_SET__9_5DB_0_4V = 0x18, 4124}; 4125 4126 4127 4128/****************************************************************************/ 4129// Structures used by ExternalEncoderControl V2.4 4130/****************************************************************************/ 4131 4132struct external_encoder_control_parameters_v2_4 4133{ 4134 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 4135 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 4136 uint8_t action; // 4137 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 4138 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 4139 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 4140 uint8_t hpd_id; 4141}; 4142 4143 4144// ucAction 4145enum external_encoder_control_action_def 4146{ 4147 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00, 4148 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01, 4149 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07, 4150 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f, 4151 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10, 4152 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11, 4153 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12, 4154 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14, 4155}; 4156 4157// ucConfig 4158enum external_encoder_control_v2_4_config_def 4159{ 4160 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03, 4161 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00, 4162 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01, 4163 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02, 4164 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, 4165 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70, 4166 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00, 4167 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10, 4168 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20, 4169}; 4170 4171struct external_encoder_control_ps_allocation_v2_4 4172{ 4173 struct external_encoder_control_parameters_v2_4 sExtEncoder; 4174 uint32_t reserved[2]; 4175}; 4176 4177 4178/* 4179 *************************************************************************** 4180 AMD ACPI Table 4181 4182 *************************************************************************** 4183*/ 4184 4185struct amd_acpi_description_header{ 4186 uint32_t signature; 4187 uint32_t tableLength; //Length 4188 uint8_t revision; 4189 uint8_t checksum; 4190 uint8_t oemId[6]; 4191 uint8_t oemTableId[8]; //UINT64 OemTableId; 4192 uint32_t oemRevision; 4193 uint32_t creatorId; 4194 uint32_t creatorRevision; 4195}; 4196 4197struct uefi_acpi_vfct{ 4198 struct amd_acpi_description_header sheader; 4199 uint8_t tableUUID[16]; //0x24 4200 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 4201 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 4202 uint32_t reserved[4]; //0x3C 4203}; 4204 4205struct vfct_image_header{ 4206 uint32_t pcibus; //0x4C 4207 uint32_t pcidevice; //0x50 4208 uint32_t pcifunction; //0x54 4209 uint16_t vendorid; //0x58 4210 uint16_t deviceid; //0x5A 4211 uint16_t ssvid; //0x5C 4212 uint16_t ssid; //0x5E 4213 uint32_t revision; //0x60 4214 uint32_t imagelength; //0x64 4215}; 4216 4217 4218struct gop_vbios_content { 4219 struct vfct_image_header vbiosheader; 4220 uint8_t vbioscontent[1]; 4221}; 4222 4223struct gop_lib1_content { 4224 struct vfct_image_header lib1header; 4225 uint8_t lib1content[1]; 4226}; 4227 4228 4229 4230/* 4231 *************************************************************************** 4232 Scratch Register definitions 4233 Each number below indicates which scratch regiser request, Active and 4234 Connect all share the same definitions as display_device_tag defines 4235 *************************************************************************** 4236*/ 4237 4238enum scratch_register_def{ 4239 ATOM_DEVICE_CONNECT_INFO_DEF = 0, 4240 ATOM_BL_BRI_LEVEL_INFO_DEF = 2, 4241 ATOM_ACTIVE_INFO_DEF = 3, 4242 ATOM_LCD_INFO_DEF = 4, 4243 ATOM_DEVICE_REQ_INFO_DEF = 5, 4244 ATOM_ACC_CHANGE_INFO_DEF = 6, 4245 ATOM_PRE_OS_MODE_INFO_DEF = 7, 4246 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers. 4247 ATOM_INTERNAL_TIMER_INFO_DEF = 10, 4248}; 4249 4250enum scratch_device_connect_info_bit_def{ 4251 ATOM_DISPLAY_LCD1_CONNECT =0x0002, 4252 ATOM_DISPLAY_DFP1_CONNECT =0x0008, 4253 ATOM_DISPLAY_DFP2_CONNECT =0x0080, 4254 ATOM_DISPLAY_DFP3_CONNECT =0x0200, 4255 ATOM_DISPLAY_DFP4_CONNECT =0x0400, 4256 ATOM_DISPLAY_DFP5_CONNECT =0x0800, 4257 ATOM_DISPLAY_DFP6_CONNECT =0x0040, 4258 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8, 4259 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff, 4260}; 4261 4262enum scratch_bl_bri_level_info_bit_def{ 4263 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8, 4264#ifndef _H2INC 4265 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00, 4266 ATOM_DEVICE_DPMS_STATE =0x00010000, 4267#endif 4268}; 4269 4270enum scratch_active_info_bits_def{ 4271 ATOM_DISPLAY_LCD1_ACTIVE =0x0002, 4272 ATOM_DISPLAY_DFP1_ACTIVE =0x0008, 4273 ATOM_DISPLAY_DFP2_ACTIVE =0x0080, 4274 ATOM_DISPLAY_DFP3_ACTIVE =0x0200, 4275 ATOM_DISPLAY_DFP4_ACTIVE =0x0400, 4276 ATOM_DISPLAY_DFP5_ACTIVE =0x0800, 4277 ATOM_DISPLAY_DFP6_ACTIVE =0x0040, 4278 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff, 4279}; 4280 4281enum scratch_device_req_info_bits_def{ 4282 ATOM_DISPLAY_LCD1_REQ =0x0002, 4283 ATOM_DISPLAY_DFP1_REQ =0x0008, 4284 ATOM_DISPLAY_DFP2_REQ =0x0080, 4285 ATOM_DISPLAY_DFP3_REQ =0x0200, 4286 ATOM_DISPLAY_DFP4_REQ =0x0400, 4287 ATOM_DISPLAY_DFP5_REQ =0x0800, 4288 ATOM_DISPLAY_DFP6_REQ =0x0040, 4289 ATOM_REQ_INFO_DEVICE_MASK =0x0fff, 4290}; 4291 4292enum scratch_acc_change_info_bitshift_def{ 4293 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4, 4294 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6, 4295}; 4296 4297enum scratch_acc_change_info_bits_def{ 4298 ATOM_ACC_CHANGE_ACC_MODE =0x00000010, 4299 ATOM_ACC_CHANGE_LID_STATUS =0x00000040, 4300}; 4301 4302enum scratch_pre_os_mode_info_bits_def{ 4303 ATOM_PRE_OS_MODE_MASK =0x00000003, 4304 ATOM_PRE_OS_MODE_VGA =0x00000000, 4305 ATOM_PRE_OS_MODE_VESA =0x00000001, 4306 ATOM_PRE_OS_MODE_GOP =0x00000002, 4307 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C, 4308 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0, 4309 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100, 4310 ATOM_ASIC_INIT_COMPLETE =0x00000200, 4311#ifndef _H2INC 4312 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000, 4313#endif 4314}; 4315 4316 4317 4318/* 4319 *************************************************************************** 4320 ATOM firmware ID header file 4321 !! Please keep it at end of the atomfirmware.h !! 4322 *************************************************************************** 4323*/ 4324#include "atomfirmwareid.h" 4325#pragma pack() 4326 4327#endif 4328