cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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discovery.h (9315B)


      1/*
      2 * Copyright 2018 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 */
     23
     24#ifndef _DISCOVERY_H_
     25#define _DISCOVERY_H_
     26
     27#define PSP_HEADER_SIZE                 256
     28#define BINARY_SIGNATURE                0x28211407
     29#define DISCOVERY_TABLE_SIGNATURE       0x53445049
     30#define GC_TABLE_ID                     0x4347
     31#define HARVEST_TABLE_SIGNATURE         0x56524148
     32#define VCN_INFO_TABLE_ID               0x004E4356
     33#define MALL_INFO_TABLE_ID              0x4D414C4C
     34
     35typedef enum
     36{
     37	IP_DISCOVERY = 0,
     38	GC,
     39	HARVEST_INFO,
     40	VCN_INFO,
     41	MALL_INFO,
     42	RESERVED_1,
     43	TOTAL_TABLES = 6
     44} table;
     45
     46#pragma pack(1)
     47
     48typedef struct table_info
     49{
     50	uint16_t offset;   /* Byte offset */
     51	uint16_t checksum; /* Byte sum of the table */
     52	uint16_t size;     /* Table size */
     53	uint16_t padding;
     54} table_info;
     55
     56typedef struct binary_header
     57{
     58	/* psp structure should go at the top of this structure */
     59	uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */
     60	uint16_t version_major;
     61	uint16_t version_minor;
     62	uint16_t binary_checksum;  /* Byte sum of the binary after this field */
     63	uint16_t binary_size;      /* Binary Size*/
     64	table_info table_list[TOTAL_TABLES];
     65} binary_header;
     66
     67typedef struct die_info
     68{
     69	uint16_t die_id;
     70	uint16_t die_offset; /* Points to the corresponding die_header structure */
     71} die_info;
     72
     73
     74typedef struct ip_discovery_header
     75{
     76	uint32_t signature;    /* Table Signature */
     77	uint16_t version;      /* Table Version */
     78	uint16_t size;         /* Table Size */
     79	uint32_t id;           /* Table ID */
     80	uint16_t num_dies;     /* Number of Dies */
     81	die_info die_info[16]; /* list die information for up to 16 dies */
     82	uint16_t padding[1];   /* padding */
     83} ip_discovery_header;
     84
     85typedef struct ip
     86{
     87	uint16_t hw_id;           /* Hardware ID */
     88	uint8_t number_instance;  /* instance of the IP */
     89	uint8_t num_base_address; /* Number of Base Addresses */
     90	uint8_t major;            /* HCID Major */
     91	uint8_t minor;            /* HCID Minor */
     92	uint8_t revision;         /* HCID Revision */
     93#if defined(__BIG_ENDIAN)
     94	uint8_t reserved : 4;     /* Placeholder field */
     95	uint8_t harvest : 4;      /* Harvest */
     96#else
     97	uint8_t harvest : 4;      /* Harvest */
     98	uint8_t reserved : 4;     /* Placeholder field */
     99#endif
    100	uint32_t base_address[]; /* variable number of Addresses */
    101} ip;
    102
    103typedef struct ip_v3
    104{
    105	uint16_t hw_id;                         /* Hardware ID */
    106	uint8_t instance_number;                /* Instance number for the IP */
    107	uint8_t num_base_address;               /* Number of base addresses*/
    108	uint8_t major;                          /* Hardware ID.major version */
    109	uint8_t minor;                          /* Hardware ID.minor version */
    110	uint8_t revision;                       /* Hardware ID.revision version */
    111#if defined(__BIG_ENDIAN)
    112	uint8_t variant : 4;                    /* HW variant */
    113	uint8_t sub_revision : 4;               /* HCID Sub-Revision */
    114#else
    115	uint8_t sub_revision : 4;               /* HCID Sub-Revision */
    116	uint8_t variant : 4;                    /* HW variant */
    117#endif
    118	uint32_t base_address[1];               /* Base Address list. Corresponds to the num_base_address field*/
    119} ip_v3;
    120
    121typedef struct die_header
    122{
    123	uint16_t die_id;
    124	uint16_t num_ips;
    125} die_header;
    126
    127typedef struct ip_structure
    128{
    129	ip_discovery_header* header;
    130	struct die
    131	{
    132		die_header *die_header;
    133		union
    134		{
    135			ip *ip_list;
    136			ip_v3 *ip_v3_list;
    137		};                                  /* IP list. Variable size*/
    138	} die;
    139} ip_structure;
    140
    141struct gpu_info_header {
    142	uint32_t table_id;      /* table ID */
    143	uint16_t version_major; /* table version */
    144	uint16_t version_minor; /* table version */
    145	uint32_t size;          /* size of the entire header+data in bytes */
    146};
    147
    148struct gc_info_v1_0 {
    149	struct gpu_info_header header;
    150
    151	uint32_t gc_num_se;
    152	uint32_t gc_num_wgp0_per_sa;
    153	uint32_t gc_num_wgp1_per_sa;
    154	uint32_t gc_num_rb_per_se;
    155	uint32_t gc_num_gl2c;
    156	uint32_t gc_num_gprs;
    157	uint32_t gc_num_max_gs_thds;
    158	uint32_t gc_gs_table_depth;
    159	uint32_t gc_gsprim_buff_depth;
    160	uint32_t gc_parameter_cache_depth;
    161	uint32_t gc_double_offchip_lds_buffer;
    162	uint32_t gc_wave_size;
    163	uint32_t gc_max_waves_per_simd;
    164	uint32_t gc_max_scratch_slots_per_cu;
    165	uint32_t gc_lds_size;
    166	uint32_t gc_num_sc_per_se;
    167	uint32_t gc_num_sa_per_se;
    168	uint32_t gc_num_packer_per_sc;
    169	uint32_t gc_num_gl2a;
    170};
    171
    172struct gc_info_v1_1 {
    173	struct gpu_info_header header;
    174
    175	uint32_t gc_num_se;
    176	uint32_t gc_num_wgp0_per_sa;
    177	uint32_t gc_num_wgp1_per_sa;
    178	uint32_t gc_num_rb_per_se;
    179	uint32_t gc_num_gl2c;
    180	uint32_t gc_num_gprs;
    181	uint32_t gc_num_max_gs_thds;
    182	uint32_t gc_gs_table_depth;
    183	uint32_t gc_gsprim_buff_depth;
    184	uint32_t gc_parameter_cache_depth;
    185	uint32_t gc_double_offchip_lds_buffer;
    186	uint32_t gc_wave_size;
    187	uint32_t gc_max_waves_per_simd;
    188	uint32_t gc_max_scratch_slots_per_cu;
    189	uint32_t gc_lds_size;
    190	uint32_t gc_num_sc_per_se;
    191	uint32_t gc_num_sa_per_se;
    192	uint32_t gc_num_packer_per_sc;
    193	uint32_t gc_num_gl2a;
    194	uint32_t gc_num_tcp_per_sa;
    195	uint32_t gc_num_sdp_interface;
    196	uint32_t gc_num_tcps;
    197};
    198
    199struct gc_info_v1_2 {
    200	struct gpu_info_header header;
    201	uint32_t gc_num_se;
    202	uint32_t gc_num_wgp0_per_sa;
    203	uint32_t gc_num_wgp1_per_sa;
    204	uint32_t gc_num_rb_per_se;
    205	uint32_t gc_num_gl2c;
    206	uint32_t gc_num_gprs;
    207	uint32_t gc_num_max_gs_thds;
    208	uint32_t gc_gs_table_depth;
    209	uint32_t gc_gsprim_buff_depth;
    210	uint32_t gc_parameter_cache_depth;
    211	uint32_t gc_double_offchip_lds_buffer;
    212	uint32_t gc_wave_size;
    213	uint32_t gc_max_waves_per_simd;
    214	uint32_t gc_max_scratch_slots_per_cu;
    215	uint32_t gc_lds_size;
    216	uint32_t gc_num_sc_per_se;
    217	uint32_t gc_num_sa_per_se;
    218	uint32_t gc_num_packer_per_sc;
    219	uint32_t gc_num_gl2a;
    220	uint32_t gc_num_tcp_per_sa;
    221	uint32_t gc_num_sdp_interface;
    222	uint32_t gc_num_tcps;
    223	uint32_t gc_num_tcp_per_wpg;
    224	uint32_t gc_tcp_l1_size;
    225	uint32_t gc_num_sqc_per_wgp;
    226	uint32_t gc_l1_instruction_cache_size_per_sqc;
    227	uint32_t gc_l1_data_cache_size_per_sqc;
    228	uint32_t gc_gl1c_per_sa;
    229	uint32_t gc_gl1c_size_per_instance;
    230	uint32_t gc_gl2c_per_gpu;
    231};
    232
    233struct gc_info_v2_0 {
    234	struct gpu_info_header header;
    235
    236	uint32_t gc_num_se;
    237	uint32_t gc_num_cu_per_sh;
    238	uint32_t gc_num_sh_per_se;
    239	uint32_t gc_num_rb_per_se;
    240	uint32_t gc_num_tccs;
    241	uint32_t gc_num_gprs;
    242	uint32_t gc_num_max_gs_thds;
    243	uint32_t gc_gs_table_depth;
    244	uint32_t gc_gsprim_buff_depth;
    245	uint32_t gc_parameter_cache_depth;
    246	uint32_t gc_double_offchip_lds_buffer;
    247	uint32_t gc_wave_size;
    248	uint32_t gc_max_waves_per_simd;
    249	uint32_t gc_max_scratch_slots_per_cu;
    250	uint32_t gc_lds_size;
    251	uint32_t gc_num_sc_per_se;
    252	uint32_t gc_num_packer_per_sc;
    253};
    254
    255typedef struct harvest_info_header {
    256	uint32_t signature; /* Table Signature */
    257	uint32_t version;   /* Table Version */
    258} harvest_info_header;
    259
    260typedef struct harvest_info {
    261	uint16_t hw_id;          /* Hardware ID */
    262	uint8_t number_instance; /* Instance of the IP */
    263	uint8_t reserved;        /* Reserved for alignment */
    264} harvest_info;
    265
    266typedef struct harvest_table {
    267	harvest_info_header header;
    268	harvest_info list[32];
    269} harvest_table;
    270
    271struct mall_info_header {
    272	uint32_t table_id; /* table ID */
    273	uint16_t version_major; /* table version */
    274	uint16_t version_minor; /* table version */
    275	uint32_t size_bytes; /* size of the entire header+data in bytes */
    276};
    277
    278struct mall_info_v1_0 {
    279	struct mall_info_header header;
    280	uint32_t mall_size_per_m;
    281	uint32_t m_s_present;
    282	uint32_t m_half_use;
    283	uint32_t m_mall_config;
    284	uint32_t reserved[5];
    285};
    286
    287#define VCN_INFO_TABLE_MAX_NUM_INSTANCES 4
    288
    289struct vcn_info_header {
    290    uint32_t table_id; /* table ID */
    291    uint16_t version_major; /* table version */
    292    uint16_t version_minor; /* table version */
    293    uint32_t size_bytes; /* size of the entire header+data in bytes */
    294};
    295
    296struct vcn_instance_info_v1_0
    297{
    298	uint32_t instance_num; /* VCN IP instance number. 0 - VCN0; 1 - VCN1 etc*/
    299	union _fuse_data {
    300		struct {
    301			uint32_t av1_disabled : 1;
    302			uint32_t vp9_disabled : 1;
    303			uint32_t hevc_disabled : 1;
    304			uint32_t h264_disabled : 1;
    305			uint32_t reserved : 28;
    306		} bits;
    307		uint32_t all_bits;
    308	} fuse_data;
    309	uint32_t reserved[2];
    310};
    311
    312struct vcn_info_v1_0 {
    313	struct vcn_info_header header;
    314	uint32_t num_of_instances; /* number of entries used in instance_info below*/
    315	struct vcn_instance_info_v1_0 instance_info[VCN_INFO_TABLE_MAX_NUM_INSTANCES];
    316	uint32_t reserved[4];
    317};
    318
    319#pragma pack()
    320
    321#endif