smu74.h (21942B)
1/* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 25#ifndef SMU74_H 26#define SMU74_H 27 28#pragma pack(push, 1) 29 30#define SMU__DGPU_ONLY 31 32#define SMU__NUM_SCLK_DPM_STATE 8 33#define SMU__NUM_MCLK_DPM_LEVELS 4 34#define SMU__NUM_LCLK_DPM_LEVELS 8 35#define SMU__NUM_PCIE_DPM_LEVELS 8 36 37#define EXP_M1 35 38#define EXP_M2 92821 39#define EXP_B 66629747 40 41#define EXP_M1_1 365 42#define EXP_M2_1 658700 43#define EXP_B_1 305506134 44 45#define EXP_M1_2 189 46#define EXP_M2_2 379692 47#define EXP_B_2 194609469 48 49#define EXP_M1_3 99 50#define EXP_M2_3 217915 51#define EXP_B_3 122255994 52 53#define EXP_M1_4 51 54#define EXP_M2_4 122643 55#define EXP_B_4 74893384 56 57#define EXP_M1_5 423 58#define EXP_M2_5 1103326 59#define EXP_B_5 728122621 60 61enum SID_OPTION { 62 SID_OPTION_HI, 63 SID_OPTION_LO, 64 SID_OPTION_COUNT 65}; 66 67enum Poly3rdOrderCoeff { 68 LEAKAGE_TEMPERATURE_SCALAR, 69 LEAKAGE_VOLTAGE_SCALAR, 70 DYNAMIC_VOLTAGE_SCALAR, 71 POLY_3RD_ORDER_COUNT 72}; 73 74struct SMU7_Poly3rdOrder_Data { 75 int32_t a; 76 int32_t b; 77 int32_t c; 78 int32_t d; 79 uint8_t a_shift; 80 uint8_t b_shift; 81 uint8_t c_shift; 82 uint8_t x_shift; 83}; 84 85typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data; 86 87struct Power_Calculator_Data { 88 uint16_t NoLoadVoltage; 89 uint16_t LoadVoltage; 90 uint16_t Resistance; 91 uint16_t Temperature; 92 uint16_t BaseLeakage; 93 uint16_t LkgTempScalar; 94 uint16_t LkgVoltScalar; 95 uint16_t LkgAreaScalar; 96 uint16_t LkgPower; 97 uint16_t DynVoltScalar; 98 uint32_t Cac; 99 uint32_t DynPower; 100 uint32_t TotalCurrent; 101 uint32_t TotalPower; 102}; 103 104typedef struct Power_Calculator_Data PowerCalculatorData_t; 105 106struct Gc_Cac_Weight_Data { 107 uint8_t index; 108 uint32_t value; 109}; 110 111typedef struct Gc_Cac_Weight_Data GcCacWeight_Data; 112 113 114typedef struct { 115 uint32_t high; 116 uint32_t low; 117} data_64_t; 118 119typedef struct { 120 data_64_t high; 121 data_64_t low; 122} data_128_t; 123 124#define SMU7_CONTEXT_ID_SMC 1 125#define SMU7_CONTEXT_ID_VBIOS 2 126 127#define SMU74_MAX_LEVELS_VDDC 16 128#define SMU74_MAX_LEVELS_VDDGFX 16 129#define SMU74_MAX_LEVELS_VDDCI 8 130#define SMU74_MAX_LEVELS_MVDD 4 131 132#define SMU_MAX_SMIO_LEVELS 4 133 134#define SMU74_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */ 135#define SMU74_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS /* MCLK Levels DPM */ 136#define SMU74_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS /* LCLK Levels */ 137#define SMU74_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes */ 138#define SMU74_MAX_LEVELS_UVD 8 /* VCLK/DCLK levels for UVD */ 139#define SMU74_MAX_LEVELS_VCE 8 /* ECLK levels for VCE */ 140#define SMU74_MAX_LEVELS_ACP 8 /* ACLK levels for ACP */ 141#define SMU74_MAX_LEVELS_SAMU 8 /* SAMCLK levels for SAMU */ 142#define SMU74_MAX_ENTRIES_SMIO 32 /* Number of entries in SMIO table */ 143 144#define DPM_NO_LIMIT 0 145#define DPM_NO_UP 1 146#define DPM_GO_DOWN 2 147#define DPM_GO_UP 3 148 149#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 150#define SMU7_FIRST_DPM_MEMORY_LEVEL 0 151 152#define GPIO_CLAMP_MODE_VRHOT 1 153#define GPIO_CLAMP_MODE_THERM 2 154#define GPIO_CLAMP_MODE_DC 4 155 156#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 157#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) 158#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 159#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) 160#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 161#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) 162#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 163#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) 164#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 165#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) 166#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 167#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) 168#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 169#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) 170#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 171#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) 172#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 173#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) 174#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 175#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) 176 177/* Virtualization Defines */ 178#define CG_XDMA_MASK 0x1 179#define CG_XDMA_SHIFT 0 180#define CG_UVD_MASK 0x2 181#define CG_UVD_SHIFT 1 182#define CG_VCE_MASK 0x4 183#define CG_VCE_SHIFT 2 184#define CG_SAMU_MASK 0x8 185#define CG_SAMU_SHIFT 3 186#define CG_GFX_MASK 0x10 187#define CG_GFX_SHIFT 4 188#define CG_SDMA_MASK 0x20 189#define CG_SDMA_SHIFT 5 190#define CG_HDP_MASK 0x40 191#define CG_HDP_SHIFT 6 192#define CG_MC_MASK 0x80 193#define CG_MC_SHIFT 7 194#define CG_DRM_MASK 0x100 195#define CG_DRM_SHIFT 8 196#define CG_ROM_MASK 0x200 197#define CG_ROM_SHIFT 9 198#define CG_BIF_MASK 0x400 199#define CG_BIF_SHIFT 10 200 201 202#define SMU74_DTE_ITERATIONS 5 203#define SMU74_DTE_SOURCES 3 204#define SMU74_DTE_SINKS 1 205#define SMU74_NUM_CPU_TES 0 206#define SMU74_NUM_GPU_TES 1 207#define SMU74_NUM_NON_TES 2 208#define SMU74_DTE_FAN_SCALAR_MIN 0x100 209#define SMU74_DTE_FAN_SCALAR_MAX 0x166 210#define SMU74_DTE_FAN_TEMP_MAX 93 211#define SMU74_DTE_FAN_TEMP_MIN 83 212 213 214#if defined SMU__FUSION_ONLY 215#define SMU7_DTE_ITERATIONS 5 216#define SMU7_DTE_SOURCES 5 217#define SMU7_DTE_SINKS 3 218#define SMU7_NUM_CPU_TES 2 219#define SMU7_NUM_GPU_TES 1 220#define SMU7_NUM_NON_TES 2 221#endif 222 223struct SMU7_HystController_Data { 224 uint8_t waterfall_up; 225 uint8_t waterfall_down; 226 uint8_t waterfall_limit; 227 uint8_t spare; 228 uint16_t release_cnt; 229 uint16_t release_limit; 230}; 231 232typedef struct SMU7_HystController_Data SMU7_HystController_Data; 233 234struct SMU74_PIDController { 235 uint32_t Ki; 236 int32_t LFWindupUpperLim; 237 int32_t LFWindupLowerLim; 238 uint32_t StatePrecision; 239 uint32_t LfPrecision; 240 uint32_t LfOffset; 241 uint32_t MaxState; 242 uint32_t MaxLfFraction; 243 uint32_t StateShift; 244}; 245 246typedef struct SMU74_PIDController SMU74_PIDController; 247 248struct SMU7_LocalDpmScoreboard { 249 uint32_t PercentageBusy; 250 251 int32_t PIDError; 252 int32_t PIDIntegral; 253 int32_t PIDOutput; 254 255 uint32_t SigmaDeltaAccum; 256 uint32_t SigmaDeltaOutput; 257 uint32_t SigmaDeltaLevel; 258 259 uint32_t UtilizationSetpoint; 260 261 uint8_t TdpClampMode; 262 uint8_t TdcClampMode; 263 uint8_t ThermClampMode; 264 uint8_t VoltageBusy; 265 266 int8_t CurrLevel; 267 int8_t TargLevel; 268 uint8_t LevelChangeInProgress; 269 uint8_t UpHyst; 270 271 uint8_t DownHyst; 272 uint8_t VoltageDownHyst; 273 uint8_t DpmEnable; 274 uint8_t DpmRunning; 275 276 uint8_t DpmForce; 277 uint8_t DpmForceLevel; 278 uint8_t DisplayWatermark; 279 uint8_t McArbIndex; 280 281 uint32_t MinimumPerfSclk; 282 283 uint8_t AcpiReq; 284 uint8_t AcpiAck; 285 uint8_t GfxClkSlow; 286 uint8_t GpioClampMode; 287 288 uint8_t spare2; 289 uint8_t EnabledLevelsChange; 290 uint8_t DteClampMode; 291 uint8_t FpsClampMode; 292 293 uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_GRAPHICS]; 294 uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_GRAPHICS]; 295 296 void (*TargetStateCalculator)(uint8_t); 297 void (*SavedTargetStateCalculator)(uint8_t); 298 299 uint16_t AutoDpmInterval; 300 uint16_t AutoDpmRange; 301 302 uint8_t FpsEnabled; 303 uint8_t MaxPerfLevel; 304 uint8_t AllowLowClkInterruptToHost; 305 uint8_t FpsRunning; 306 307 uint32_t MaxAllowedFrequency; 308 309 uint32_t FilteredSclkFrequency; 310 uint32_t LastSclkFrequency; 311 uint32_t FilteredSclkFrequencyCnt; 312 313 uint8_t MinPerfLevel; 314 uint8_t padding[3]; 315 316 uint16_t FpsAlpha; 317 uint16_t DeltaTime; 318 uint32_t CurrentFps; 319 uint32_t FilteredFps; 320 uint32_t FrameCount; 321 uint32_t FrameCountLast; 322 uint16_t FpsTargetScalar; 323 uint16_t FpsWaterfallLimitScalar; 324 uint16_t FpsAlphaScalar; 325 uint16_t spare8; 326 SMU7_HystController_Data HystControllerData; 327}; 328 329typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard; 330 331#define SMU7_MAX_VOLTAGE_CLIENTS 12 332 333typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t); 334 335#define VDDC_MASK 0x00007FFF 336#define VDDC_SHIFT 0 337#define VDDCI_MASK 0x3FFF8000 338#define VDDCI_SHIFT 15 339#define PHASES_MASK 0xC0000000 340#define PHASES_SHIFT 30 341 342typedef uint32_t SMU_VoltageLevel; 343 344struct SMU7_VoltageScoreboard { 345 346 SMU_VoltageLevel TargetVoltage; 347 uint16_t MaxVid; 348 uint8_t HighestVidOffset; 349 uint8_t CurrentVidOffset; 350 351 uint16_t CurrentVddc; 352 uint16_t CurrentVddci; 353 354 355 uint8_t ControllerBusy; 356 uint8_t CurrentVid; 357 uint8_t CurrentVddciVid; 358 uint8_t padding; 359 360 SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS]; 361 SMU_VoltageLevel TargetVoltageState; 362 uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS]; 363 364 uint8_t padding2; 365 uint8_t padding3; 366 uint8_t ControllerEnable; 367 uint8_t ControllerRunning; 368 uint16_t CurrentStdVoltageHiSidd; 369 uint16_t CurrentStdVoltageLoSidd; 370 uint8_t OverrideVoltage; 371 uint8_t padding4; 372 uint8_t padding5; 373 uint8_t CurrentPhases; 374 375 VoltageChangeHandler_t ChangeVddc; 376 377 VoltageChangeHandler_t ChangeVddci; 378 VoltageChangeHandler_t ChangePhase; 379 VoltageChangeHandler_t ChangeMvdd; 380 381 VoltageChangeHandler_t functionLinks[6]; 382 383 uint16_t *VddcFollower1; 384 385 int16_t Driver_OD_RequestedVidOffset1; 386 int16_t Driver_OD_RequestedVidOffset2; 387}; 388 389typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard; 390 391#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ 392 393struct SMU7_PCIeLinkSpeedScoreboard { 394 uint8_t DpmEnable; 395 uint8_t DpmRunning; 396 uint8_t DpmForce; 397 uint8_t DpmForceLevel; 398 399 uint8_t CurrentLinkSpeed; 400 uint8_t EnabledLevelsChange; 401 uint16_t AutoDpmInterval; 402 403 uint16_t AutoDpmRange; 404 uint16_t AutoDpmCount; 405 406 uint8_t DpmMode; 407 uint8_t AcpiReq; 408 uint8_t AcpiAck; 409 uint8_t CurrentLinkLevel; 410 411}; 412 413typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard; 414 415#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 416#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 417 418#define SMU7_SCALE_I 7 419#define SMU7_SCALE_R 12 420 421struct SMU7_PowerScoreboard { 422 PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT]; 423 424 uint32_t TotalGpuPower; 425 uint32_t TdcCurrent; 426 427 uint16_t VddciTotalPower; 428 uint16_t sparesasfsdfd; 429 uint16_t Vddr1Power; 430 uint16_t RocPower; 431 432 uint16_t CalcMeasPowerBlend; 433 uint8_t SidOptionPower; 434 uint8_t SidOptionCurrent; 435 436 uint32_t WinTime; 437 438 uint16_t Telemetry_1_slope; 439 uint16_t Telemetry_2_slope; 440 int32_t Telemetry_1_offset; 441 int32_t Telemetry_2_offset; 442 443 uint32_t VddcCurrentTelemetry; 444 uint32_t VddGfxCurrentTelemetry; 445 uint32_t VddcPowerTelemetry; 446 uint32_t VddGfxPowerTelemetry; 447 uint32_t VddciPowerTelemetry; 448 449 uint32_t VddcPower; 450 uint32_t VddGfxPower; 451 uint32_t VddciPower; 452 453 uint32_t TelemetryCurrent[2]; 454 uint32_t TelemetryVoltage[2]; 455 uint32_t TelemetryPower[2]; 456}; 457 458typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard; 459 460struct SMU7_ThermalScoreboard { 461 int16_t GpuLimit; 462 int16_t GpuHyst; 463 uint16_t CurrGnbTemp; 464 uint16_t FilteredGnbTemp; 465 466 uint8_t ControllerEnable; 467 uint8_t ControllerRunning; 468 uint8_t AutoTmonCalInterval; 469 uint8_t AutoTmonCalEnable; 470 471 uint8_t ThermalDpmEnabled; 472 uint8_t SclkEnabledMask; 473 uint8_t spare[2]; 474 int32_t temperature_gradient; 475 476 SMU7_HystController_Data HystControllerData; 477 int32_t WeightedSensorTemperature; 478 uint16_t TemperatureLimit[SMU74_MAX_LEVELS_GRAPHICS]; 479 uint32_t Alpha; 480}; 481 482typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard; 483 484#define SMU7_SCLK_DPM_CONFIG_MASK 0x01 485#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 486#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 487#define SMU7_MCLK_DPM_CONFIG_MASK 0x08 488#define SMU7_UVD_DPM_CONFIG_MASK 0x10 489#define SMU7_VCE_DPM_CONFIG_MASK 0x20 490#define SMU7_ACP_DPM_CONFIG_MASK 0x40 491#define SMU7_SAMU_DPM_CONFIG_MASK 0x80 492#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 493 494#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 495#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 496#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 497#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 498#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 499#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 500 501/* All 'soft registers' should be uint32_t. */ 502struct SMU74_SoftRegisters { 503 uint32_t RefClockFrequency; 504 uint32_t PmTimerPeriod; 505 uint32_t FeatureEnables; 506 507 uint32_t PreVBlankGap; 508 uint32_t VBlankTimeout; 509 uint32_t TrainTimeGap; 510 511 uint32_t MvddSwitchTime; 512 uint32_t LongestAcpiTrainTime; 513 uint32_t AcpiDelay; 514 uint32_t G5TrainTime; 515 uint32_t DelayMpllPwron; 516 uint32_t VoltageChangeTimeout; 517 518 uint32_t HandshakeDisables; 519 520 uint8_t DisplayPhy1Config; 521 uint8_t DisplayPhy2Config; 522 uint8_t DisplayPhy3Config; 523 uint8_t DisplayPhy4Config; 524 525 uint8_t DisplayPhy5Config; 526 uint8_t DisplayPhy6Config; 527 uint8_t DisplayPhy7Config; 528 uint8_t DisplayPhy8Config; 529 530 uint32_t AverageGraphicsActivity; 531 uint32_t AverageMemoryActivity; 532 uint32_t AverageGioActivity; 533 534 uint8_t SClkDpmEnabledLevels; 535 uint8_t MClkDpmEnabledLevels; 536 uint8_t LClkDpmEnabledLevels; 537 uint8_t PCIeDpmEnabledLevels; 538 539 uint8_t UVDDpmEnabledLevels; 540 uint8_t SAMUDpmEnabledLevels; 541 uint8_t ACPDpmEnabledLevels; 542 uint8_t VCEDpmEnabledLevels; 543 544 uint32_t DRAM_LOG_ADDR_H; 545 uint32_t DRAM_LOG_ADDR_L; 546 uint32_t DRAM_LOG_PHY_ADDR_H; 547 uint32_t DRAM_LOG_PHY_ADDR_L; 548 uint32_t DRAM_LOG_BUFF_SIZE; 549 uint32_t UlvEnterCount; 550 uint32_t UlvTime; 551 uint32_t UcodeLoadStatus; 552 uint32_t AllowMvddSwitch; 553 uint8_t Activity_Weight; 554 uint8_t Reserved8[3]; 555}; 556 557typedef struct SMU74_SoftRegisters SMU74_SoftRegisters; 558 559struct SMU74_Firmware_Header { 560 uint32_t Digest[5]; 561 uint32_t Version; 562 uint32_t HeaderSize; 563 uint32_t Flags; 564 uint32_t EntryPoint; 565 uint32_t CodeSize; 566 uint32_t ImageSize; 567 568 uint32_t Rtos; 569 uint32_t SoftRegisters; 570 uint32_t DpmTable; 571 uint32_t FanTable; 572 uint32_t CacConfigTable; 573 uint32_t CacStatusTable; 574 575 uint32_t mcRegisterTable; 576 577 uint32_t mcArbDramTimingTable; 578 579 uint32_t PmFuseTable; 580 uint32_t Globals; 581 uint32_t ClockStretcherTable; 582 uint32_t VftTable; 583 uint32_t Reserved1; 584 uint32_t AvfsTable; 585 uint32_t AvfsCksOffGbvTable; 586 uint32_t AvfsMeanNSigma; 587 uint32_t AvfsSclkOffsetTable; 588 uint32_t Reserved[16]; 589 uint32_t Signature; 590}; 591 592typedef struct SMU74_Firmware_Header SMU74_Firmware_Header; 593 594#define SMU7_FIRMWARE_HEADER_LOCATION 0x20000 595 596enum DisplayConfig { 597 PowerDown = 1, 598 DP54x4, 599 DP54x2, 600 DP54x1, 601 DP27x4, 602 DP27x2, 603 DP27x1, 604 HDMI297, 605 HDMI162, 606 LVDS, 607 DP324x4, 608 DP324x2, 609 DP324x1 610}; 611 612 613#define MC_BLOCK_COUNT 1 614#define CPL_BLOCK_COUNT 5 615#define SE_BLOCK_COUNT 15 616#define GC_BLOCK_COUNT 24 617 618struct SMU7_Local_Cac { 619 uint8_t BlockId; 620 uint8_t SignalId; 621 uint8_t Threshold; 622 uint8_t Padding; 623}; 624 625typedef struct SMU7_Local_Cac SMU7_Local_Cac; 626 627struct SMU7_Local_Cac_Table { 628 629 SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT]; 630 SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT]; 631 SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT]; 632 SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT]; 633}; 634 635typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table; 636 637#pragma pack(pop) 638 639/* Description of Clock Gating bitmask for Tonga: 640 * System Clock Gating 641 */ 642#define CG_SYS_BITMASK_FIRST_BIT 0 /* First bit of Sys CG bitmask */ 643#define CG_SYS_BITMASK_LAST_BIT 9 /* Last bit of Sys CG bitmask */ 644#define CG_SYS_BIF_MGLS_SHIFT 0 645#define CG_SYS_ROM_SHIFT 1 646#define CG_SYS_MC_MGCG_SHIFT 2 647#define CG_SYS_MC_MGLS_SHIFT 3 648#define CG_SYS_SDMA_MGCG_SHIFT 4 649#define CG_SYS_SDMA_MGLS_SHIFT 5 650#define CG_SYS_DRM_MGCG_SHIFT 6 651#define CG_SYS_HDP_MGCG_SHIFT 7 652#define CG_SYS_HDP_MGLS_SHIFT 8 653#define CG_SYS_DRM_MGLS_SHIFT 9 654#define CG_SYS_BIF_MGCG_SHIFT 10 655 656#define CG_SYS_BIF_MGLS_MASK 0x1 657#define CG_SYS_ROM_MASK 0x2 658#define CG_SYS_MC_MGCG_MASK 0x4 659#define CG_SYS_MC_MGLS_MASK 0x8 660#define CG_SYS_SDMA_MGCG_MASK 0x10 661#define CG_SYS_SDMA_MGLS_MASK 0x20 662#define CG_SYS_DRM_MGCG_MASK 0x40 663#define CG_SYS_HDP_MGCG_MASK 0x80 664#define CG_SYS_HDP_MGLS_MASK 0x100 665#define CG_SYS_DRM_MGLS_MASK 0x200 666#define CG_SYS_BIF_MGCG_MASK 0x400 667 668/* Graphics Clock Gating */ 669#define CG_GFX_BITMASK_FIRST_BIT 16 /* First bit of Gfx CG bitmask */ 670#define CG_GFX_BITMASK_LAST_BIT 24 /* Last bit of Gfx CG bitmask */ 671 672#define CG_GFX_CGCG_SHIFT 16 673#define CG_GFX_CGLS_SHIFT 17 674#define CG_CPF_MGCG_SHIFT 18 675#define CG_RLC_MGCG_SHIFT 19 676#define CG_GFX_OTHERS_MGCG_SHIFT 20 677#define CG_GFX_3DCG_SHIFT 21 678#define CG_GFX_3DLS_SHIFT 22 679#define CG_GFX_RLC_LS_SHIFT 23 680#define CG_GFX_CP_LS_SHIFT 24 681 682#define CG_GFX_CGCG_MASK 0x00010000 683#define CG_GFX_CGLS_MASK 0x00020000 684#define CG_CPF_MGCG_MASK 0x00040000 685#define CG_RLC_MGCG_MASK 0x00080000 686#define CG_GFX_OTHERS_MGCG_MASK 0x00100000 687#define CG_GFX_3DCG_MASK 0x00200000 688#define CG_GFX_3DLS_MASK 0x00400000 689#define CG_GFX_RLC_LS_MASK 0x00800000 690#define CG_GFX_CP_LS_MASK 0x01000000 691 692 693/* Voltage Regulator Configuration 694VR Config info is contained in dpmTable.VRConfig */ 695 696#define VRCONF_VDDC_MASK 0x000000FF 697#define VRCONF_VDDC_SHIFT 0 698#define VRCONF_VDDGFX_MASK 0x0000FF00 699#define VRCONF_VDDGFX_SHIFT 8 700#define VRCONF_VDDCI_MASK 0x00FF0000 701#define VRCONF_VDDCI_SHIFT 16 702#define VRCONF_MVDD_MASK 0xFF000000 703#define VRCONF_MVDD_SHIFT 24 704 705#define VR_MERGED_WITH_VDDC 0 706#define VR_SVI2_PLANE_1 1 707#define VR_SVI2_PLANE_2 2 708#define VR_SMIO_PATTERN_1 3 709#define VR_SMIO_PATTERN_2 4 710#define VR_STATIC_VOLTAGE 5 711 712/* Clock Stretcher Configuration */ 713 714#define CLOCK_STRETCHER_MAX_ENTRIES 0x4 715#define CKS_LOOKUPTable_MAX_ENTRIES 0x4 716 717/* The 'settings' field is subdivided in the following way: */ 718#define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01 719#define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0 720#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E 721#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1 722#define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80 723#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7 724 725struct SMU_ClockStretcherDataTableEntry { 726 uint8_t minVID; 727 uint8_t maxVID; 728 uint16_t setting; 729}; 730typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry; 731 732struct SMU_ClockStretcherDataTable { 733 SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES]; 734}; 735typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable; 736 737struct SMU_CKS_LOOKUPTableEntry { 738 uint16_t minFreq; 739 uint16_t maxFreq; 740 741 uint8_t setting; 742 uint8_t padding[3]; 743}; 744typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry; 745 746struct SMU_CKS_LOOKUPTable { 747 SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES]; 748}; 749typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable; 750 751struct AgmAvfsData_t { 752 uint16_t avgPsmCount[28]; 753 uint16_t minPsmCount[28]; 754}; 755 756typedef struct AgmAvfsData_t AgmAvfsData_t; 757 758enum VFT_COLUMNS { 759 SCLK0, 760 SCLK1, 761 SCLK2, 762 SCLK3, 763 SCLK4, 764 SCLK5, 765 SCLK6, 766 SCLK7, 767 768 NUM_VFT_COLUMNS 769}; 770 771#define VFT_TABLE_DEFINED 772 773#define TEMP_RANGE_MAXSTEPS 12 774 775struct VFT_CELL_t { 776 uint16_t Voltage; 777}; 778 779typedef struct VFT_CELL_t VFT_CELL_t; 780 781struct VFT_TABLE_t { 782 VFT_CELL_t Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS]; 783 uint16_t AvfsGbv[NUM_VFT_COLUMNS]; 784 uint16_t BtcGbv[NUM_VFT_COLUMNS]; 785 uint16_t Temperature[TEMP_RANGE_MAXSTEPS]; 786 787 uint8_t NumTemperatureSteps; 788 uint8_t padding[3]; 789}; 790 791typedef struct VFT_TABLE_t VFT_TABLE_t; 792 793 794/* Total margin, root mean square of Fmax + DC + Platform */ 795struct AVFS_Margin_t { 796 VFT_CELL_t Cell[NUM_VFT_COLUMNS]; 797}; 798typedef struct AVFS_Margin_t AVFS_Margin_t; 799 800#define BTCGB_VDROOP_TABLE_MAX_ENTRIES 2 801#define AVFSGB_VDROOP_TABLE_MAX_ENTRIES 2 802 803struct GB_VDROOP_TABLE_t { 804 int32_t a0; 805 int32_t a1; 806 int32_t a2; 807 uint32_t spare; 808}; 809typedef struct GB_VDROOP_TABLE_t GB_VDROOP_TABLE_t; 810 811struct AVFS_CksOff_Gbv_t { 812 VFT_CELL_t Cell[NUM_VFT_COLUMNS]; 813}; 814typedef struct AVFS_CksOff_Gbv_t AVFS_CksOff_Gbv_t; 815 816struct AVFS_meanNsigma_t { 817 uint32_t Aconstant[3]; 818 uint16_t DC_tol_sigma; 819 uint16_t Platform_mean; 820 uint16_t Platform_sigma; 821 uint16_t PSM_Age_CompFactor; 822 uint8_t Static_Voltage_Offset[NUM_VFT_COLUMNS]; 823}; 824typedef struct AVFS_meanNsigma_t AVFS_meanNsigma_t; 825 826struct AVFS_Sclk_Offset_t { 827 uint16_t Sclk_Offset[8]; 828}; 829typedef struct AVFS_Sclk_Offset_t AVFS_Sclk_Offset_t; 830 831#endif 832 833