cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

smu8_fusion.h (4173B)

      1/*
      2 * Copyright 2014 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 */
     23
     24#ifndef SMU8_FUSION_H
     25#define SMU8_FUSION_H
     26
     27#include "smu8.h"
     28
     29#pragma pack(push, 1)
     30
     31#define SMU8_MAX_CUS 2
     32#define SMU8_PSMS_PER_CU 4
     33#define SMU8_CACS_PER_CU 4
     34
     35struct SMU8_GfxCuPgScoreboard {
     36    uint8_t Enabled;
     37    uint8_t spare[3];
     38};
     39
     40struct SMU8_Port80MonitorTable {
     41	uint32_t MmioAddress;
     42	uint32_t MemoryBaseHi;
     43	uint32_t MemoryBaseLo;
     44	uint16_t MemoryBufferSize;
     45	uint16_t MemoryPosition;
     46	uint16_t PollingInterval;
     47	uint8_t  EnableCsrShadow;
     48	uint8_t  EnableDramShadow;
     49};
     50
     51/*  Display specific power management parameters */
     52#define PWRMGT_SEPARATION_TIME_SHIFT            0
     53#define PWRMGT_SEPARATION_TIME_MASK             0xFFFF
     54#define PWRMGT_DISABLE_CPU_CSTATES_SHIFT        16
     55#define PWRMGT_DISABLE_CPU_CSTATES_MASK         0x1
     56#define PWRMGT_DISABLE_CPU_PSTATES_SHIFT        24
     57#define PWRMGT_DISABLE_CPU_PSTATES_MASK         0x1
     58
     59/* Clock Table Definitions */
     60#define NUM_SCLK_LEVELS     8
     61#define NUM_LCLK_LEVELS     8
     62#define NUM_UVD_LEVELS      8
     63#define NUM_ECLK_LEVELS     8
     64#define NUM_ACLK_LEVELS     8
     65
     66struct SMU8_Fusion_ClkLevel {
     67	uint8_t		GnbVid;
     68	uint8_t		GfxVid;
     69	uint8_t		DfsDid;
     70	uint8_t		DeepSleepDid;
     71	uint32_t	DfsBypass;
     72	uint32_t	Frequency;
     73};
     74
     75struct SMU8_Fusion_SclkBreakdownTable {
     76	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_SCLK_LEVELS];
     77	struct SMU8_Fusion_ClkLevel DpmOffLevel;
     78	/* SMU8_Fusion_ClkLevel PwrOffLevel; */
     79	uint32_t    SclkValidMask;
     80	uint32_t    MaxSclkIndex;
     81};
     82
     83struct SMU8_Fusion_LclkBreakdownTable {
     84	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_LCLK_LEVELS];
     85	struct SMU8_Fusion_ClkLevel DpmOffLevel;
     86    /* SMU8_Fusion_ClkLevel PwrOffLevel; */
     87	uint32_t    LclkValidMask;
     88	uint32_t    MaxLclkIndex;
     89};
     90
     91struct SMU8_Fusion_EclkBreakdownTable {
     92	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ECLK_LEVELS];
     93	struct SMU8_Fusion_ClkLevel DpmOffLevel;
     94	struct SMU8_Fusion_ClkLevel PwrOffLevel;
     95	uint32_t    EclkValidMask;
     96	uint32_t    MaxEclkIndex;
     97};
     98
     99struct SMU8_Fusion_VclkBreakdownTable {
    100	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS];
    101	struct SMU8_Fusion_ClkLevel DpmOffLevel;
    102	struct SMU8_Fusion_ClkLevel PwrOffLevel;
    103	uint32_t    VclkValidMask;
    104	uint32_t    MaxVclkIndex;
    105};
    106
    107struct SMU8_Fusion_DclkBreakdownTable {
    108	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS];
    109	struct SMU8_Fusion_ClkLevel DpmOffLevel;
    110	struct SMU8_Fusion_ClkLevel PwrOffLevel;
    111	uint32_t    DclkValidMask;
    112	uint32_t    MaxDclkIndex;
    113};
    114
    115struct SMU8_Fusion_AclkBreakdownTable {
    116	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ACLK_LEVELS];
    117	struct SMU8_Fusion_ClkLevel DpmOffLevel;
    118	struct SMU8_Fusion_ClkLevel PwrOffLevel;
    119	uint32_t    AclkValidMask;
    120	uint32_t    MaxAclkIndex;
    121};
    122
    123
    124struct SMU8_Fusion_ClkTable {
    125	struct SMU8_Fusion_SclkBreakdownTable SclkBreakdownTable;
    126	struct SMU8_Fusion_LclkBreakdownTable LclkBreakdownTable;
    127	struct SMU8_Fusion_EclkBreakdownTable EclkBreakdownTable;
    128	struct SMU8_Fusion_VclkBreakdownTable VclkBreakdownTable;
    129	struct SMU8_Fusion_DclkBreakdownTable DclkBreakdownTable;
    130	struct SMU8_Fusion_AclkBreakdownTable AclkBreakdownTable;
    131};
    132
    133#pragma pack(pop)
    134
    135#endif