smu9.h (6776B)
1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef SMU9_H 25#define SMU9_H 26 27#pragma pack(push, 1) 28 29#define ENABLE_DEBUG_FEATURES 30 31/* Feature Control Defines */ 32#define FEATURE_DPM_PREFETCHER_BIT 0 33#define FEATURE_DPM_GFXCLK_BIT 1 34#define FEATURE_DPM_UCLK_BIT 2 35#define FEATURE_DPM_SOCCLK_BIT 3 36#define FEATURE_DPM_UVD_BIT 4 37#define FEATURE_DPM_VCE_BIT 5 38#define FEATURE_ULV_BIT 6 39#define FEATURE_DPM_MP0CLK_BIT 7 40#define FEATURE_DPM_LINK_BIT 8 41#define FEATURE_DPM_DCEFCLK_BIT 9 42#define FEATURE_AVFS_BIT 10 43#define FEATURE_DS_GFXCLK_BIT 11 44#define FEATURE_DS_SOCCLK_BIT 12 45#define FEATURE_DS_LCLK_BIT 13 46#define FEATURE_PPT_BIT 14 47#define FEATURE_TDC_BIT 15 48#define FEATURE_THERMAL_BIT 16 49#define FEATURE_GFX_PER_CU_CG_BIT 17 50#define FEATURE_RM_BIT 18 51#define FEATURE_DS_DCEFCLK_BIT 19 52#define FEATURE_ACDC_BIT 20 53#define FEATURE_VR0HOT_BIT 21 54#define FEATURE_VR1HOT_BIT 22 55#define FEATURE_FW_CTF_BIT 23 56#define FEATURE_LED_DISPLAY_BIT 24 57#define FEATURE_FAN_CONTROL_BIT 25 58#define FEATURE_FAST_PPT_BIT 26 59#define FEATURE_GFX_EDC_BIT 27 60#define FEATURE_ACG_BIT 28 61#define FEATURE_PCC_LIMIT_CONTROL_BIT 29 62#define FEATURE_SPARE_30_BIT 30 63#define FEATURE_SPARE_31_BIT 31 64 65#define NUM_FEATURES 32 66 67#define FFEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT ) 68#define FFEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT ) 69#define FFEATURE_DPM_UCLK_MASK (1 << FEATURE_DPM_UCLK_BIT ) 70#define FFEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT ) 71#define FFEATURE_DPM_UVD_MASK (1 << FEATURE_DPM_UVD_BIT ) 72#define FFEATURE_DPM_VCE_MASK (1 << FEATURE_DPM_VCE_BIT ) 73#define FFEATURE_ULV_MASK (1 << FEATURE_ULV_BIT ) 74#define FFEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT ) 75#define FFEATURE_DPM_LINK_MASK (1 << FEATURE_DPM_LINK_BIT ) 76#define FFEATURE_DPM_DCEFCLK_MASK (1 << FEATURE_DPM_DCEFCLK_BIT ) 77#define FFEATURE_AVFS_MASK (1 << FEATURE_AVFS_BIT ) 78#define FFEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT ) 79#define FFEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT ) 80#define FFEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT ) 81#define FFEATURE_PPT_MASK (1 << FEATURE_PPT_BIT ) 82#define FFEATURE_TDC_MASK (1 << FEATURE_TDC_BIT ) 83#define FFEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT ) 84#define FFEATURE_GFX_PER_CU_CG_MASK (1 << FEATURE_GFX_PER_CU_CG_BIT ) 85#define FFEATURE_RM_MASK (1 << FEATURE_RM_BIT ) 86#define FFEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFCLK_BIT ) 87#define FFEATURE_ACDC_MASK (1 << FEATURE_ACDC_BIT ) 88#define FFEATURE_VR0HOT_MASK (1 << FEATURE_VR0HOT_BIT ) 89#define FFEATURE_VR1HOT_MASK (1 << FEATURE_VR1HOT_BIT ) 90#define FFEATURE_FW_CTF_MASK (1 << FEATURE_FW_CTF_BIT ) 91#define FFEATURE_LED_DISPLAY_MASK (1 << FEATURE_LED_DISPLAY_BIT ) 92#define FFEATURE_FAN_CONTROL_MASK (1 << FEATURE_FAN_CONTROL_BIT ) 93 94#define FEATURE_FAST_PPT_MASK (1 << FAST_PPT_BIT ) 95#define FEATURE_GFX_EDC_MASK (1 << FEATURE_GFX_EDC_BIT ) 96#define FEATURE_ACG_MASK (1 << FEATURE_ACG_BIT ) 97#define FEATURE_PCC_LIMIT_CONTROL_MASK (1 << FEATURE_PCC_LIMIT_CONTROL_BIT ) 98#define FFEATURE_SPARE_30_MASK (1 << FEATURE_SPARE_30_BIT ) 99#define FFEATURE_SPARE_31_MASK (1 << FEATURE_SPARE_31_BIT ) 100/* Workload types */ 101#define WORKLOAD_VR_BIT 0 102#define WORKLOAD_FRTC_BIT 1 103#define WORKLOAD_VIDEO_BIT 2 104#define WORKLOAD_COMPUTE_BIT 3 105#define NUM_WORKLOADS 4 106 107/* ULV Client Masks */ 108#define ULV_CLIENT_RLC_MASK 0x00000001 109#define ULV_CLIENT_UVD_MASK 0x00000002 110#define ULV_CLIENT_VCE_MASK 0x00000004 111#define ULV_CLIENT_SDMA0_MASK 0x00000008 112#define ULV_CLIENT_SDMA1_MASK 0x00000010 113#define ULV_CLIENT_JPEG_MASK 0x00000020 114#define ULV_CLIENT_GFXCLK_DPM_MASK 0x00000040 115#define ULV_CLIENT_UVD_DPM_MASK 0x00000080 116#define ULV_CLIENT_VCE_DPM_MASK 0x00000100 117#define ULV_CLIENT_MP0CLK_DPM_MASK 0x00000200 118#define ULV_CLIENT_UCLK_DPM_MASK 0x00000400 119#define ULV_CLIENT_SOCCLK_DPM_MASK 0x00000800 120#define ULV_CLIENT_DCEFCLK_DPM_MASK 0x00001000 121 122typedef struct { 123 /* MP1_EXT_SCRATCH0 */ 124 uint32_t CurrLevel_GFXCLK : 4; 125 uint32_t CurrLevel_UVD : 4; 126 uint32_t CurrLevel_VCE : 4; 127 uint32_t CurrLevel_LCLK : 4; 128 uint32_t CurrLevel_MP0CLK : 4; 129 uint32_t CurrLevel_UCLK : 4; 130 uint32_t CurrLevel_SOCCLK : 4; 131 uint32_t CurrLevel_DCEFCLK : 4; 132 /* MP1_EXT_SCRATCH1 */ 133 uint32_t TargLevel_GFXCLK : 4; 134 uint32_t TargLevel_UVD : 4; 135 uint32_t TargLevel_VCE : 4; 136 uint32_t TargLevel_LCLK : 4; 137 uint32_t TargLevel_MP0CLK : 4; 138 uint32_t TargLevel_UCLK : 4; 139 uint32_t TargLevel_SOCCLK : 4; 140 uint32_t TargLevel_DCEFCLK : 4; 141 /* MP1_EXT_SCRATCH2-7 */ 142 uint32_t Reserved[6]; 143} FwStatus_t; 144 145#pragma pack(pop) 146 147#endif 148