cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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polaris10_smumgr.h (2381B)

      1/*
      2 * Copyright 2015 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 */
     23
     24#ifndef _POLARIS10_SMUMANAGER_H
     25#define _POLARIS10_SMUMANAGER_H
     26
     27
     28#include <pp_endian.h>
     29#include "smu74.h"
     30#include "smu74_discrete.h"
     31#include "smu7_smumgr.h"
     32
     33#define SMC_RAM_END 0x40000
     34
     35struct polaris10_pt_defaults {
     36	uint8_t   SviLoadLineEn;
     37	uint8_t   SviLoadLineVddC;
     38	uint8_t   TDC_VDDC_ThrottleReleaseLimitPerc;
     39	uint8_t   TDC_MAWt;
     40	uint8_t   TdcWaterfallCtl;
     41	uint8_t   DTEAmbientTempBase;
     42
     43	uint32_t  DisplayCac;
     44	uint32_t  BAPM_TEMP_GRADIENT;
     45	uint16_t  BAPMTI_R[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
     46	uint16_t  BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
     47};
     48
     49struct polaris10_range_table {
     50	uint32_t trans_lower_frequency; /* in 10khz */
     51	uint32_t trans_upper_frequency;
     52};
     53
     54struct polaris10_smumgr {
     55	struct smu7_smumgr smu7_data;
     56	uint8_t protected_mode;
     57	SMU74_Discrete_DpmTable              smc_state_table;
     58	struct SMU74_Discrete_Ulv            ulv_setting;
     59	struct SMU74_Discrete_PmFuses  power_tune_table;
     60	struct polaris10_range_table                range_table[NUM_SCLK_RANGE];
     61	const struct polaris10_pt_defaults       *power_tune_defaults;
     62	uint32_t               bif_sclk_table[SMU74_MAX_LEVELS_LINK];
     63	pp_atomctrl_mc_reg_table             mc_reg_table;
     64};
     65
     66
     67#endif