cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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amdgpu_smu.h (41574B)


      1/*
      2 * Copyright 2019 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 */
     22#ifndef __AMDGPU_SMU_H__
     23#define __AMDGPU_SMU_H__
     24
     25#include "amdgpu.h"
     26#include "kgd_pp_interface.h"
     27#include "dm_pp_interface.h"
     28#include "dm_pp_smu.h"
     29#include "smu_types.h"
     30#include "linux/firmware.h"
     31
     32#define SMU_THERMAL_MINIMUM_ALERT_TEMP		0
     33#define SMU_THERMAL_MAXIMUM_ALERT_TEMP		255
     34#define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES	1000
     35#define SMU_FW_NAME_LEN			0x24
     36
     37#define SMU_DPM_USER_PROFILE_RESTORE (1 << 0)
     38#define SMU_CUSTOM_FAN_SPEED_RPM     (1 << 1)
     39#define SMU_CUSTOM_FAN_SPEED_PWM     (1 << 2)
     40
     41// Power Throttlers
     42#define SMU_THROTTLER_PPT0_BIT			0
     43#define SMU_THROTTLER_PPT1_BIT			1
     44#define SMU_THROTTLER_PPT2_BIT			2
     45#define SMU_THROTTLER_PPT3_BIT			3
     46#define SMU_THROTTLER_SPL_BIT			4
     47#define SMU_THROTTLER_FPPT_BIT			5
     48#define SMU_THROTTLER_SPPT_BIT			6
     49#define SMU_THROTTLER_SPPT_APU_BIT		7
     50
     51// Current Throttlers
     52#define SMU_THROTTLER_TDC_GFX_BIT		16
     53#define SMU_THROTTLER_TDC_SOC_BIT		17
     54#define SMU_THROTTLER_TDC_MEM_BIT		18
     55#define SMU_THROTTLER_TDC_VDD_BIT		19
     56#define SMU_THROTTLER_TDC_CVIP_BIT		20
     57#define SMU_THROTTLER_EDC_CPU_BIT		21
     58#define SMU_THROTTLER_EDC_GFX_BIT		22
     59#define SMU_THROTTLER_APCC_BIT			23
     60
     61// Temperature
     62#define SMU_THROTTLER_TEMP_GPU_BIT		32
     63#define SMU_THROTTLER_TEMP_CORE_BIT		33
     64#define SMU_THROTTLER_TEMP_MEM_BIT		34
     65#define SMU_THROTTLER_TEMP_EDGE_BIT		35
     66#define SMU_THROTTLER_TEMP_HOTSPOT_BIT		36
     67#define SMU_THROTTLER_TEMP_SOC_BIT		37
     68#define SMU_THROTTLER_TEMP_VR_GFX_BIT		38
     69#define SMU_THROTTLER_TEMP_VR_SOC_BIT		39
     70#define SMU_THROTTLER_TEMP_VR_MEM0_BIT		40
     71#define SMU_THROTTLER_TEMP_VR_MEM1_BIT		41
     72#define SMU_THROTTLER_TEMP_LIQUID0_BIT		42
     73#define SMU_THROTTLER_TEMP_LIQUID1_BIT		43
     74#define SMU_THROTTLER_VRHOT0_BIT		44
     75#define SMU_THROTTLER_VRHOT1_BIT		45
     76#define SMU_THROTTLER_PROCHOT_CPU_BIT		46
     77#define SMU_THROTTLER_PROCHOT_GFX_BIT		47
     78
     79// Other
     80#define SMU_THROTTLER_PPM_BIT			56
     81#define SMU_THROTTLER_FIT_BIT			57
     82
     83struct smu_hw_power_state {
     84	unsigned int magic;
     85};
     86
     87struct smu_power_state;
     88
     89enum smu_state_ui_label {
     90	SMU_STATE_UI_LABEL_NONE,
     91	SMU_STATE_UI_LABEL_BATTERY,
     92	SMU_STATE_UI_TABEL_MIDDLE_LOW,
     93	SMU_STATE_UI_LABEL_BALLANCED,
     94	SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
     95	SMU_STATE_UI_LABEL_PERFORMANCE,
     96	SMU_STATE_UI_LABEL_BACO,
     97};
     98
     99enum smu_state_classification_flag {
    100	SMU_STATE_CLASSIFICATION_FLAG_BOOT                     = 0x0001,
    101	SMU_STATE_CLASSIFICATION_FLAG_THERMAL                  = 0x0002,
    102	SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE      = 0x0004,
    103	SMU_STATE_CLASSIFICATION_FLAG_RESET                    = 0x0008,
    104	SMU_STATE_CLASSIFICATION_FLAG_FORCED                   = 0x0010,
    105	SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE      = 0x0020,
    106	SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE      = 0x0040,
    107	SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE           = 0x0080,
    108	SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE   = 0x0100,
    109	SMU_STATE_CLASSIFICATION_FLAG_UVD                      = 0x0200,
    110	SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW       = 0x0400,
    111	SMU_STATE_CLASSIFICATION_FLAG_ACPI                     = 0x0800,
    112	SMU_STATE_CLASSIFICATION_FLAG_HD2                      = 0x1000,
    113	SMU_STATE_CLASSIFICATION_FLAG_UVD_HD                   = 0x2000,
    114	SMU_STATE_CLASSIFICATION_FLAG_UVD_SD                   = 0x4000,
    115	SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE      = 0x8000,
    116	SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE   = 0x10000,
    117	SMU_STATE_CLASSIFICATION_FLAG_BACO                     = 0x20000,
    118	SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2      = 0x40000,
    119	SMU_STATE_CLASSIFICATION_FLAG_ULV                      = 0x80000,
    120	SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC                  = 0x100000,
    121};
    122
    123struct smu_state_classification_block {
    124	enum smu_state_ui_label         ui_label;
    125	enum smu_state_classification_flag  flags;
    126	int                          bios_index;
    127	bool                      temporary_state;
    128	bool                      to_be_deleted;
    129};
    130
    131struct smu_state_pcie_block {
    132	unsigned int lanes;
    133};
    134
    135enum smu_refreshrate_source {
    136	SMU_REFRESHRATE_SOURCE_EDID,
    137	SMU_REFRESHRATE_SOURCE_EXPLICIT
    138};
    139
    140struct smu_state_display_block {
    141	bool              disable_frame_modulation;
    142	bool              limit_refreshrate;
    143	enum smu_refreshrate_source refreshrate_source;
    144	int                  explicit_refreshrate;
    145	int                  edid_refreshrate_index;
    146	bool              enable_vari_bright;
    147};
    148
    149struct smu_state_memory_block {
    150	bool              dll_off;
    151	uint8_t                 m3arb;
    152	uint8_t                 unused[3];
    153};
    154
    155struct smu_state_software_algorithm_block {
    156	bool disable_load_balancing;
    157	bool enable_sleep_for_timestamps;
    158};
    159
    160struct smu_temperature_range {
    161	int min;
    162	int max;
    163	int edge_emergency_max;
    164	int hotspot_min;
    165	int hotspot_crit_max;
    166	int hotspot_emergency_max;
    167	int mem_min;
    168	int mem_crit_max;
    169	int mem_emergency_max;
    170	int software_shutdown_temp;
    171};
    172
    173struct smu_state_validation_block {
    174	bool single_display_only;
    175	bool disallow_on_dc;
    176	uint8_t supported_power_levels;
    177};
    178
    179struct smu_uvd_clocks {
    180	uint32_t vclk;
    181	uint32_t dclk;
    182};
    183
    184/**
    185* Structure to hold a SMU Power State.
    186*/
    187struct smu_power_state {
    188	uint32_t                                      id;
    189	struct list_head                              ordered_list;
    190	struct list_head                              all_states_list;
    191
    192	struct smu_state_classification_block         classification;
    193	struct smu_state_validation_block             validation;
    194	struct smu_state_pcie_block                   pcie;
    195	struct smu_state_display_block                display;
    196	struct smu_state_memory_block                 memory;
    197	struct smu_state_software_algorithm_block     software;
    198	struct smu_uvd_clocks                         uvd_clocks;
    199	struct smu_hw_power_state                     hardware;
    200};
    201
    202enum smu_power_src_type
    203{
    204	SMU_POWER_SOURCE_AC,
    205	SMU_POWER_SOURCE_DC,
    206	SMU_POWER_SOURCE_COUNT,
    207};
    208
    209enum smu_ppt_limit_type
    210{
    211	SMU_DEFAULT_PPT_LIMIT = 0,
    212	SMU_FAST_PPT_LIMIT,
    213};
    214
    215enum smu_ppt_limit_level
    216{
    217	SMU_PPT_LIMIT_MIN = -1,
    218	SMU_PPT_LIMIT_CURRENT,
    219	SMU_PPT_LIMIT_DEFAULT,
    220	SMU_PPT_LIMIT_MAX,
    221};
    222
    223enum smu_memory_pool_size
    224{
    225    SMU_MEMORY_POOL_SIZE_ZERO   = 0,
    226    SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
    227    SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
    228    SMU_MEMORY_POOL_SIZE_1_GB   = 0x40000000,
    229    SMU_MEMORY_POOL_SIZE_2_GB   = 0x80000000,
    230};
    231
    232struct smu_user_dpm_profile {
    233	uint32_t fan_mode;
    234	uint32_t power_limit;
    235	uint32_t fan_speed_pwm;
    236	uint32_t fan_speed_rpm;
    237	uint32_t flags;
    238	uint32_t user_od;
    239
    240	/* user clock state information */
    241	uint32_t clk_mask[SMU_CLK_COUNT];
    242	uint32_t clk_dependency;
    243};
    244
    245#define SMU_TABLE_INIT(tables, table_id, s, a, d)	\
    246	do {						\
    247		tables[table_id].size = s;		\
    248		tables[table_id].align = a;		\
    249		tables[table_id].domain = d;		\
    250	} while (0)
    251
    252struct smu_table {
    253	uint64_t size;
    254	uint32_t align;
    255	uint8_t domain;
    256	uint64_t mc_address;
    257	void *cpu_addr;
    258	struct amdgpu_bo *bo;
    259};
    260
    261enum smu_perf_level_designation {
    262	PERF_LEVEL_ACTIVITY,
    263	PERF_LEVEL_POWER_CONTAINMENT,
    264};
    265
    266struct smu_performance_level {
    267	uint32_t core_clock;
    268	uint32_t memory_clock;
    269	uint32_t vddc;
    270	uint32_t vddci;
    271	uint32_t non_local_mem_freq;
    272	uint32_t non_local_mem_width;
    273};
    274
    275struct smu_clock_info {
    276	uint32_t min_mem_clk;
    277	uint32_t max_mem_clk;
    278	uint32_t min_eng_clk;
    279	uint32_t max_eng_clk;
    280	uint32_t min_bus_bandwidth;
    281	uint32_t max_bus_bandwidth;
    282};
    283
    284struct smu_bios_boot_up_values
    285{
    286	uint32_t			revision;
    287	uint32_t			gfxclk;
    288	uint32_t			uclk;
    289	uint32_t			socclk;
    290	uint32_t			dcefclk;
    291	uint32_t			eclk;
    292	uint32_t			vclk;
    293	uint32_t			dclk;
    294	uint16_t			vddc;
    295	uint16_t			vddci;
    296	uint16_t			mvddc;
    297	uint16_t			vdd_gfx;
    298	uint8_t				cooling_id;
    299	uint32_t			pp_table_id;
    300	uint32_t			format_revision;
    301	uint32_t			content_revision;
    302	uint32_t			fclk;
    303	uint32_t			lclk;
    304	uint32_t			firmware_caps;
    305};
    306
    307enum smu_table_id
    308{
    309	SMU_TABLE_PPTABLE = 0,
    310	SMU_TABLE_WATERMARKS,
    311	SMU_TABLE_CUSTOM_DPM,
    312	SMU_TABLE_DPMCLOCKS,
    313	SMU_TABLE_AVFS,
    314	SMU_TABLE_AVFS_PSM_DEBUG,
    315	SMU_TABLE_AVFS_FUSE_OVERRIDE,
    316	SMU_TABLE_PMSTATUSLOG,
    317	SMU_TABLE_SMU_METRICS,
    318	SMU_TABLE_DRIVER_SMU_CONFIG,
    319	SMU_TABLE_ACTIVITY_MONITOR_COEFF,
    320	SMU_TABLE_OVERDRIVE,
    321	SMU_TABLE_I2C_COMMANDS,
    322	SMU_TABLE_PACE,
    323	SMU_TABLE_ECCINFO,
    324	SMU_TABLE_COMBO_PPTABLE,
    325	SMU_TABLE_COUNT,
    326};
    327
    328struct smu_table_context
    329{
    330	void				*power_play_table;
    331	uint32_t			power_play_table_size;
    332	void				*hardcode_pptable;
    333	unsigned long			metrics_time;
    334	void				*metrics_table;
    335	void				*clocks_table;
    336	void				*watermarks_table;
    337
    338	void				*max_sustainable_clocks;
    339	struct smu_bios_boot_up_values	boot_values;
    340	void				*driver_pptable;
    341	void				*combo_pptable;
    342	void                            *ecc_table;
    343	void				*driver_smu_config_table;
    344	struct smu_table		tables[SMU_TABLE_COUNT];
    345	/*
    346	 * The driver table is just a staging buffer for
    347	 * uploading/downloading content from the SMU.
    348	 *
    349	 * And the table_id for SMU_MSG_TransferTableSmu2Dram/
    350	 * SMU_MSG_TransferTableDram2Smu instructs SMU
    351	 * which content driver is interested.
    352	 */
    353	struct smu_table		driver_table;
    354	struct smu_table		memory_pool;
    355	struct smu_table		dummy_read_1_table;
    356	uint8_t                         thermal_controller_type;
    357
    358	void				*overdrive_table;
    359	void                            *boot_overdrive_table;
    360	void				*user_overdrive_table;
    361
    362	uint32_t			gpu_metrics_table_size;
    363	void				*gpu_metrics_table;
    364};
    365
    366struct smu_dpm_context {
    367	uint32_t dpm_context_size;
    368	void *dpm_context;
    369	void *golden_dpm_context;
    370	enum amd_dpm_forced_level dpm_level;
    371	enum amd_dpm_forced_level saved_dpm_level;
    372	enum amd_dpm_forced_level requested_dpm_level;
    373	struct smu_power_state *dpm_request_power_state;
    374	struct smu_power_state *dpm_current_power_state;
    375	struct mclock_latency_table *mclk_latency_table;
    376};
    377
    378struct smu_power_gate {
    379	bool uvd_gated;
    380	bool vce_gated;
    381	atomic_t vcn_gated;
    382	atomic_t jpeg_gated;
    383};
    384
    385struct smu_power_context {
    386	void *power_context;
    387	uint32_t power_context_size;
    388	struct smu_power_gate power_gate;
    389};
    390
    391#define SMU_FEATURE_MAX	(64)
    392struct smu_feature
    393{
    394	uint32_t feature_num;
    395	DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
    396	DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
    397};
    398
    399struct smu_clocks {
    400	uint32_t engine_clock;
    401	uint32_t memory_clock;
    402	uint32_t bus_bandwidth;
    403	uint32_t engine_clock_in_sr;
    404	uint32_t dcef_clock;
    405	uint32_t dcef_clock_in_sr;
    406};
    407
    408#define MAX_REGULAR_DPM_NUM 16
    409struct mclk_latency_entries {
    410	uint32_t  frequency;
    411	uint32_t  latency;
    412};
    413struct mclock_latency_table {
    414	uint32_t  count;
    415	struct mclk_latency_entries  entries[MAX_REGULAR_DPM_NUM];
    416};
    417
    418enum smu_reset_mode
    419{
    420    SMU_RESET_MODE_0,
    421    SMU_RESET_MODE_1,
    422    SMU_RESET_MODE_2,
    423};
    424
    425enum smu_baco_state
    426{
    427	SMU_BACO_STATE_ENTER = 0,
    428	SMU_BACO_STATE_EXIT,
    429};
    430
    431struct smu_baco_context
    432{
    433	uint32_t state;
    434	bool platform_support;
    435};
    436
    437struct smu_freq_info {
    438	uint32_t min;
    439	uint32_t max;
    440	uint32_t freq_level;
    441};
    442
    443struct pstates_clk_freq {
    444	uint32_t			min;
    445	uint32_t			standard;
    446	uint32_t			peak;
    447	struct smu_freq_info		custom;
    448	struct smu_freq_info		curr;
    449};
    450
    451struct smu_umd_pstate_table {
    452	struct pstates_clk_freq		gfxclk_pstate;
    453	struct pstates_clk_freq		socclk_pstate;
    454	struct pstates_clk_freq		uclk_pstate;
    455	struct pstates_clk_freq		vclk_pstate;
    456	struct pstates_clk_freq		dclk_pstate;
    457	struct pstates_clk_freq		fclk_pstate;
    458};
    459
    460struct cmn2asic_msg_mapping {
    461	int	valid_mapping;
    462	int	map_to;
    463	int	valid_in_vf;
    464};
    465
    466struct cmn2asic_mapping {
    467	int	valid_mapping;
    468	int	map_to;
    469};
    470
    471struct stb_context {
    472	uint32_t stb_buf_size;
    473	bool enabled;
    474	spinlock_t lock;
    475};
    476
    477#define WORKLOAD_POLICY_MAX 7
    478
    479struct smu_context
    480{
    481	struct amdgpu_device            *adev;
    482	struct amdgpu_irq_src		irq_source;
    483
    484	const struct pptable_funcs	*ppt_funcs;
    485	const struct cmn2asic_msg_mapping	*message_map;
    486	const struct cmn2asic_mapping	*clock_map;
    487	const struct cmn2asic_mapping	*feature_map;
    488	const struct cmn2asic_mapping	*table_map;
    489	const struct cmn2asic_mapping	*pwr_src_map;
    490	const struct cmn2asic_mapping	*workload_map;
    491	struct mutex			message_lock;
    492	uint64_t pool_size;
    493
    494	struct smu_table_context	smu_table;
    495	struct smu_dpm_context		smu_dpm;
    496	struct smu_power_context	smu_power;
    497	struct smu_feature		smu_feature;
    498	struct amd_pp_display_configuration  *display_config;
    499	struct smu_baco_context		smu_baco;
    500	struct smu_temperature_range	thermal_range;
    501	void *od_settings;
    502
    503	struct smu_umd_pstate_table	pstate_table;
    504	uint32_t pstate_sclk;
    505	uint32_t pstate_mclk;
    506
    507	bool od_enabled;
    508	uint32_t current_power_limit;
    509	uint32_t default_power_limit;
    510	uint32_t max_power_limit;
    511
    512	/* soft pptable */
    513	uint32_t ppt_offset_bytes;
    514	uint32_t ppt_size_bytes;
    515	uint8_t  *ppt_start_addr;
    516
    517	bool support_power_containment;
    518	bool disable_watermark;
    519
    520#define WATERMARKS_EXIST	(1 << 0)
    521#define WATERMARKS_LOADED	(1 << 1)
    522	uint32_t watermarks_bitmap;
    523	uint32_t hard_min_uclk_req_from_dal;
    524	bool disable_uclk_switch;
    525
    526	uint32_t workload_mask;
    527	uint32_t workload_prority[WORKLOAD_POLICY_MAX];
    528	uint32_t workload_setting[WORKLOAD_POLICY_MAX];
    529	uint32_t power_profile_mode;
    530	uint32_t default_power_profile_mode;
    531	bool pm_enabled;
    532	bool is_apu;
    533
    534	uint32_t smc_driver_if_version;
    535	uint32_t smc_fw_if_version;
    536	uint32_t smc_fw_version;
    537
    538	bool uploading_custom_pp_table;
    539	bool dc_controlled_by_gpio;
    540
    541	struct work_struct throttling_logging_work;
    542	atomic64_t throttle_int_counter;
    543	struct work_struct interrupt_work;
    544
    545	unsigned fan_max_rpm;
    546	unsigned manual_fan_speed_pwm;
    547
    548	uint32_t gfx_default_hard_min_freq;
    549	uint32_t gfx_default_soft_max_freq;
    550	uint32_t gfx_actual_hard_min_freq;
    551	uint32_t gfx_actual_soft_max_freq;
    552
    553	/* APU only */
    554	uint32_t cpu_default_soft_min_freq;
    555	uint32_t cpu_default_soft_max_freq;
    556	uint32_t cpu_actual_soft_min_freq;
    557	uint32_t cpu_actual_soft_max_freq;
    558	uint32_t cpu_core_id_select;
    559	uint16_t cpu_core_num;
    560
    561	struct smu_user_dpm_profile user_dpm_profile;
    562
    563	struct stb_context stb_context;
    564
    565	struct firmware pptable_firmware;
    566};
    567
    568struct i2c_adapter;
    569
    570/**
    571 * struct pptable_funcs - Callbacks used to interact with the SMU.
    572 */
    573struct pptable_funcs {
    574	/**
    575	 * @run_btc: Calibrate voltage/frequency curve to fit the system's
    576	 *           power delivery and voltage margins. Required for adaptive
    577	 *           voltage frequency scaling (AVFS).
    578	 */
    579	int (*run_btc)(struct smu_context *smu);
    580
    581	/**
    582	 * @get_allowed_feature_mask: Get allowed feature mask.
    583	 * &feature_mask: Array to store feature mask.
    584	 * &num: Elements in &feature_mask.
    585	 */
    586	int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
    587
    588	/**
    589	 * @get_current_power_state: Get the current power state.
    590	 *
    591	 * Return: Current power state on success, negative errno on failure.
    592	 */
    593	enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
    594
    595	/**
    596	 * @set_default_dpm_table: Retrieve the default overdrive settings from
    597	 *                         the SMU.
    598	 */
    599	int (*set_default_dpm_table)(struct smu_context *smu);
    600
    601	int (*set_power_state)(struct smu_context *smu);
    602
    603	/**
    604	 * @populate_umd_state_clk: Populate the UMD power state table with
    605	 *                          defaults.
    606	 */
    607	int (*populate_umd_state_clk)(struct smu_context *smu);
    608
    609	/**
    610	 * @print_clk_levels: Print DPM clock levels for a clock domain
    611	 *                    to buffer. Star current level.
    612	 *
    613	 * Used for sysfs interfaces.
    614	 * Return: Number of characters written to the buffer
    615	 */
    616	int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
    617
    618	/**
    619	 * @emit_clk_levels: Print DPM clock levels for a clock domain
    620	 *                    to buffer using sysfs_emit_at. Star current level.
    621	 *
    622	 * Used for sysfs interfaces.
    623	 * &buf: sysfs buffer
    624	 * &offset: offset within buffer to start printing, which is updated by the
    625	 * function.
    626	 *
    627	 * Return: 0 on Success or Negative to indicate an error occurred.
    628	 */
    629	int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset);
    630
    631	/**
    632	 * @force_clk_levels: Set a range of allowed DPM levels for a clock
    633	 *                    domain.
    634	 * &clk_type: Clock domain.
    635	 * &mask: Range of allowed DPM levels.
    636	 */
    637	int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
    638
    639	/**
    640	 * @od_edit_dpm_table: Edit the custom overdrive DPM table.
    641	 * &type: Type of edit.
    642	 * &input: Edit parameters.
    643	 * &size: Size of &input.
    644	 */
    645	int (*od_edit_dpm_table)(struct smu_context *smu,
    646				 enum PP_OD_DPM_TABLE_COMMAND type,
    647				 long *input, uint32_t size);
    648
    649	/**
    650	 * @restore_user_od_settings: Restore the user customized
    651	 *                            OD settings on S3/S4/Runpm resume.
    652	 */
    653	int (*restore_user_od_settings)(struct smu_context *smu);
    654
    655	/**
    656	 * @get_clock_by_type_with_latency: Get the speed and latency of a clock
    657	 *                                  domain.
    658	 */
    659	int (*get_clock_by_type_with_latency)(struct smu_context *smu,
    660					      enum smu_clk_type clk_type,
    661					      struct
    662					      pp_clock_levels_with_latency
    663					      *clocks);
    664	/**
    665	 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock
    666	 *                                  domain.
    667	 */
    668	int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
    669					      enum amd_pp_clock_type type,
    670					      struct
    671					      pp_clock_levels_with_voltage
    672					      *clocks);
    673
    674	/**
    675	 * @get_power_profile_mode: Print all power profile modes to
    676	 *                          buffer. Star current mode.
    677	 */
    678	int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
    679
    680	/**
    681	 * @set_power_profile_mode: Set a power profile mode. Also used to
    682	 *                          create/set custom power profile modes.
    683	 * &input: Power profile mode parameters.
    684	 * &size: Size of &input.
    685	 */
    686	int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
    687
    688	/**
    689	 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power
    690	 *                      management.
    691	 */
    692	int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable);
    693
    694	/**
    695	 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power
    696	 *                       management.
    697	 */
    698	int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
    699
    700	/**
    701	 * @read_sensor: Read data from a sensor.
    702	 * &sensor: Sensor to read data from.
    703	 * &data: Sensor reading.
    704	 * &size: Size of &data.
    705	 */
    706	int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
    707			   void *data, uint32_t *size);
    708
    709	/**
    710	 * @pre_display_config_changed: Prepare GPU for a display configuration
    711	 *                              change.
    712	 *
    713	 * Disable display tracking and pin memory clock speed to maximum. Used
    714	 * in display component synchronization.
    715	 */
    716	int (*pre_display_config_changed)(struct smu_context *smu);
    717
    718	/**
    719	 * @display_config_changed: Notify the SMU of the current display
    720	 *                          configuration.
    721	 *
    722	 * Allows SMU to properly track blanking periods for memory clock
    723	 * adjustment. Used in display component synchronization.
    724	 */
    725	int (*display_config_changed)(struct smu_context *smu);
    726
    727	int (*apply_clocks_adjust_rules)(struct smu_context *smu);
    728
    729	/**
    730	 * @notify_smc_display_config: Applies display requirements to the
    731	 *                             current power state.
    732	 *
    733	 * Optimize deep sleep DCEFclk and mclk for the current display
    734	 * configuration. Used in display component synchronization.
    735	 */
    736	int (*notify_smc_display_config)(struct smu_context *smu);
    737
    738	/**
    739	 * @is_dpm_running: Check if DPM is running.
    740	 *
    741	 * Return: True if DPM is running, false otherwise.
    742	 */
    743	bool (*is_dpm_running)(struct smu_context *smu);
    744
    745	/**
    746	 * @get_fan_speed_pwm: Get the current fan speed in PWM.
    747	 */
    748	int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed);
    749
    750	/**
    751	 * @get_fan_speed_rpm: Get the current fan speed in rpm.
    752	 */
    753	int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
    754
    755	/**
    756	 * @set_watermarks_table: Configure and upload the watermarks tables to
    757	 *                        the SMU.
    758	 */
    759	int (*set_watermarks_table)(struct smu_context *smu,
    760				    struct pp_smu_wm_range_sets *clock_ranges);
    761
    762	/**
    763	 * @get_thermal_temperature_range: Get safe thermal limits in Celcius.
    764	 */
    765	int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
    766
    767	/**
    768	 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz.
    769	 * &clocks_in_khz: Array of DPM levels.
    770	 * &num_states: Elements in &clocks_in_khz.
    771	 */
    772	int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
    773
    774	/**
    775	 * @set_default_od_settings: Set the overdrive tables to defaults.
    776	 */
    777	int (*set_default_od_settings)(struct smu_context *smu);
    778
    779	/**
    780	 * @set_performance_level: Set a performance level.
    781	 */
    782	int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
    783
    784	/**
    785	 * @display_disable_memory_clock_switch: Enable/disable dynamic memory
    786	 *                                       clock switching.
    787	 *
    788	 * Disabling this feature forces memory clock speed to maximum.
    789	 * Enabling sets the minimum memory clock capable of driving the
    790	 * current display configuration.
    791	 */
    792	int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
    793
    794	/**
    795	 * @dump_pptable: Print the power play table to the system log.
    796	 */
    797	void (*dump_pptable)(struct smu_context *smu);
    798
    799	/**
    800	 * @get_power_limit: Get the device's power limits.
    801	 */
    802	int (*get_power_limit)(struct smu_context *smu,
    803			       uint32_t *current_power_limit,
    804			       uint32_t *default_power_limit,
    805			       uint32_t *max_power_limit);
    806
    807	/**
    808	 * @get_ppt_limit: Get the device's ppt limits.
    809	 */
    810	int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit,
    811			enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level);
    812
    813	/**
    814	 * @set_df_cstate: Set data fabric cstate.
    815	 */
    816	int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
    817
    818	/**
    819	 * @allow_xgmi_power_down: Enable/disable external global memory
    820	 *                         interconnect power down.
    821	 */
    822	int (*allow_xgmi_power_down)(struct smu_context *smu, bool en);
    823
    824	/**
    825	 * @update_pcie_parameters: Update and upload the system's PCIe
    826	 *                          capabilites to the SMU.
    827	 * &pcie_gen_cap: Maximum allowed PCIe generation.
    828	 * &pcie_width_cap: Maximum allowed PCIe width.
    829	 */
    830	int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
    831
    832	/**
    833	 * @i2c_init: Initialize i2c.
    834	 *
    835	 * The i2c bus is used internally by the SMU voltage regulators and
    836	 * other devices. The i2c's EEPROM also stores bad page tables on boards
    837	 * with ECC.
    838	 */
    839	int (*i2c_init)(struct smu_context *smu);
    840
    841	/**
    842	 * @i2c_fini: Tear down i2c.
    843	 */
    844	void (*i2c_fini)(struct smu_context *smu);
    845
    846	/**
    847	 * @get_unique_id: Get the GPU's unique id. Used for asset tracking.
    848	 */
    849	void (*get_unique_id)(struct smu_context *smu);
    850
    851	/**
    852	 * @get_dpm_clock_table: Get a copy of the DPM clock table.
    853	 *
    854	 * Used by display component in bandwidth and watermark calculations.
    855	 */
    856	int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
    857
    858	/**
    859	 * @init_microcode: Request the SMU's firmware from the kernel.
    860	 */
    861	int (*init_microcode)(struct smu_context *smu);
    862
    863	/**
    864	 * @load_microcode: Load firmware onto the SMU.
    865	 */
    866	int (*load_microcode)(struct smu_context *smu);
    867
    868	/**
    869	 * @fini_microcode: Release the SMU's firmware.
    870	 */
    871	void (*fini_microcode)(struct smu_context *smu);
    872
    873	/**
    874	 * @init_smc_tables: Initialize the SMU tables.
    875	 */
    876	int (*init_smc_tables)(struct smu_context *smu);
    877
    878	/**
    879	 * @fini_smc_tables: Release the SMU tables.
    880	 */
    881	int (*fini_smc_tables)(struct smu_context *smu);
    882
    883	/**
    884	 * @init_power: Initialize the power gate table context.
    885	 */
    886	int (*init_power)(struct smu_context *smu);
    887
    888	/**
    889	 * @fini_power: Release the power gate table context.
    890	 */
    891	int (*fini_power)(struct smu_context *smu);
    892
    893	/**
    894	 * @check_fw_status: Check the SMU's firmware status.
    895	 *
    896	 * Return: Zero if check passes, negative errno on failure.
    897	 */
    898	int (*check_fw_status)(struct smu_context *smu);
    899
    900	/**
    901	 * @set_mp1_state: put SMU into a correct state for comming
    902	 *                 resume from runpm or gpu reset.
    903	 */
    904	int (*set_mp1_state)(struct smu_context *smu,
    905			     enum pp_mp1_state mp1_state);
    906
    907	/**
    908	 * @setup_pptable: Initialize the power play table and populate it with
    909	 *                 default values.
    910	 */
    911	int (*setup_pptable)(struct smu_context *smu);
    912
    913	/**
    914	 * @get_vbios_bootup_values: Get default boot values from the VBIOS.
    915	 */
    916	int (*get_vbios_bootup_values)(struct smu_context *smu);
    917
    918	/**
    919	 * @check_fw_version: Print driver and SMU interface versions to the
    920	 *                    system log.
    921	 *
    922	 * Interface mismatch is not a critical failure.
    923	 */
    924	int (*check_fw_version)(struct smu_context *smu);
    925
    926	/**
    927	 * @powergate_sdma: Power up/down system direct memory access.
    928	 */
    929	int (*powergate_sdma)(struct smu_context *smu, bool gate);
    930
    931	/**
    932	 * @set_gfx_cgpg: Enable/disable graphics engine course grain power
    933	 *                gating.
    934	 */
    935	int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
    936
    937	/**
    938	 * @write_pptable: Write the power play table to the SMU.
    939	 */
    940	int (*write_pptable)(struct smu_context *smu);
    941
    942	/**
    943	 * @set_driver_table_location: Send the location of the driver table to
    944	 *                             the SMU.
    945	 */
    946	int (*set_driver_table_location)(struct smu_context *smu);
    947
    948	/**
    949	 * @set_tool_table_location: Send the location of the tool table to the
    950	 *                           SMU.
    951	 */
    952	int (*set_tool_table_location)(struct smu_context *smu);
    953
    954	/**
    955	 * @notify_memory_pool_location: Send the location of the memory pool to
    956	 *                               the SMU.
    957	 */
    958	int (*notify_memory_pool_location)(struct smu_context *smu);
    959
    960	/**
    961	 * @system_features_control: Enable/disable all SMU features.
    962	 */
    963	int (*system_features_control)(struct smu_context *smu, bool en);
    964
    965	/**
    966	 * @send_smc_msg_with_param: Send a message with a parameter to the SMU.
    967	 * &msg: Type of message.
    968	 * &param: Message parameter.
    969	 * &read_arg: SMU response (optional).
    970	 */
    971	int (*send_smc_msg_with_param)(struct smu_context *smu,
    972				       enum smu_message_type msg, uint32_t param, uint32_t *read_arg);
    973
    974	/**
    975	 * @send_smc_msg: Send a message to the SMU.
    976	 * &msg: Type of message.
    977	 * &read_arg: SMU response (optional).
    978	 */
    979	int (*send_smc_msg)(struct smu_context *smu,
    980			    enum smu_message_type msg,
    981			    uint32_t *read_arg);
    982
    983	/**
    984	 * @init_display_count: Notify the SMU of the number of display
    985	 *                      components in current display configuration.
    986	 */
    987	int (*init_display_count)(struct smu_context *smu, uint32_t count);
    988
    989	/**
    990	 * @set_allowed_mask: Notify the SMU of the features currently allowed
    991	 *                    by the driver.
    992	 */
    993	int (*set_allowed_mask)(struct smu_context *smu);
    994
    995	/**
    996	 * @get_enabled_mask: Get a mask of features that are currently enabled
    997	 *                    on the SMU.
    998	 * &feature_mask: Enabled feature mask.
    999	 */
   1000	int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask);
   1001
   1002	/**
   1003	 * @feature_is_enabled: Test if a feature is enabled.
   1004	 *
   1005	 * Return: One if enabled, zero if disabled.
   1006	 */
   1007	int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask);
   1008
   1009	/**
   1010	 * @disable_all_features_with_exception: Disable all features with
   1011	 *                                       exception to those in &mask.
   1012	 */
   1013	int (*disable_all_features_with_exception)(struct smu_context *smu,
   1014						   enum smu_feature_mask mask);
   1015
   1016	/**
   1017	 * @notify_display_change: Enable fast memory clock switching.
   1018	 *
   1019	 * Allows for fine grained memory clock switching but has more stringent
   1020	 * timing requirements.
   1021	 */
   1022	int (*notify_display_change)(struct smu_context *smu);
   1023
   1024	/**
   1025	 * @set_power_limit: Set power limit in watts.
   1026	 */
   1027	int (*set_power_limit)(struct smu_context *smu,
   1028			       enum smu_ppt_limit_type limit_type,
   1029			       uint32_t limit);
   1030
   1031	/**
   1032	 * @init_max_sustainable_clocks: Populate max sustainable clock speed
   1033	 *                               table with values from the SMU.
   1034	 */
   1035	int (*init_max_sustainable_clocks)(struct smu_context *smu);
   1036
   1037	/**
   1038	 * @enable_thermal_alert: Enable thermal alert interrupts.
   1039	 */
   1040	int (*enable_thermal_alert)(struct smu_context *smu);
   1041
   1042	/**
   1043	 * @disable_thermal_alert: Disable thermal alert interrupts.
   1044	 */
   1045	int (*disable_thermal_alert)(struct smu_context *smu);
   1046
   1047	/**
   1048	 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep
   1049	 *                           clock speed in MHz.
   1050	 */
   1051	int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk);
   1052
   1053	/**
   1054	 * @display_clock_voltage_request: Set a hard minimum frequency
   1055	 * for a clock domain.
   1056	 */
   1057	int (*display_clock_voltage_request)(struct smu_context *smu, struct
   1058					     pp_display_clock_request
   1059					     *clock_req);
   1060
   1061	/**
   1062	 * @get_fan_control_mode: Get the current fan control mode.
   1063	 */
   1064	uint32_t (*get_fan_control_mode)(struct smu_context *smu);
   1065
   1066	/**
   1067	 * @set_fan_control_mode: Set the fan control mode.
   1068	 */
   1069	int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
   1070
   1071	/**
   1072	 * @set_fan_speed_pwm: Set a static fan speed in PWM.
   1073	 */
   1074	int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed);
   1075
   1076	/**
   1077	 * @set_fan_speed_rpm: Set a static fan speed in rpm.
   1078	 */
   1079	int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
   1080
   1081	/**
   1082	 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate.
   1083	 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise.
   1084	 */
   1085	int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
   1086
   1087	/**
   1088	 * @gfx_off_control: Enable/disable graphics engine poweroff.
   1089	 */
   1090	int (*gfx_off_control)(struct smu_context *smu, bool enable);
   1091
   1092
   1093	/**
   1094	 * @get_gfx_off_status: Get graphics engine poweroff status.
   1095	 *
   1096	 * Return:
   1097	 * 0 - GFXOFF(default).
   1098	 * 1 - Transition out of GFX State.
   1099	 * 2 - Not in GFXOFF.
   1100	 * 3 - Transition into GFXOFF.
   1101	 */
   1102	uint32_t (*get_gfx_off_status)(struct smu_context *smu);
   1103
   1104	/**
   1105	 * @register_irq_handler: Register interupt request handlers.
   1106	 */
   1107	int (*register_irq_handler)(struct smu_context *smu);
   1108
   1109	/**
   1110	 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep.
   1111	 */
   1112	int (*set_azalia_d3_pme)(struct smu_context *smu);
   1113
   1114	/**
   1115	 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable
   1116	 *                                    clock speeds table.
   1117	 *
   1118	 * Provides a way for the display component (DC) to get the max
   1119	 * sustainable clocks from the SMU.
   1120	 */
   1121	int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
   1122
   1123	/**
   1124	 * @baco_is_support: Check if GPU supports BACO (Bus Active, Chip Off).
   1125	 */
   1126	bool (*baco_is_support)(struct smu_context *smu);
   1127
   1128	/**
   1129	 * @baco_get_state: Get the current BACO state.
   1130	 *
   1131	 * Return: Current BACO state.
   1132	 */
   1133	enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
   1134
   1135	/**
   1136	 * @baco_set_state: Enter/exit BACO.
   1137	 */
   1138	int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
   1139
   1140	/**
   1141	 * @baco_enter: Enter BACO.
   1142	 */
   1143	int (*baco_enter)(struct smu_context *smu);
   1144
   1145	/**
   1146	 * @baco_exit: Exit Baco.
   1147	 */
   1148	int (*baco_exit)(struct smu_context *smu);
   1149
   1150	/**
   1151	 * @mode1_reset_is_support: Check if GPU supports mode1 reset.
   1152	 */
   1153	bool (*mode1_reset_is_support)(struct smu_context *smu);
   1154	/**
   1155	 * @mode2_reset_is_support: Check if GPU supports mode2 reset.
   1156	 */
   1157	bool (*mode2_reset_is_support)(struct smu_context *smu);
   1158
   1159	/**
   1160	 * @mode1_reset: Perform mode1 reset.
   1161	 *
   1162	 * Complete GPU reset.
   1163	 */
   1164	int (*mode1_reset)(struct smu_context *smu);
   1165
   1166	/**
   1167	 * @mode2_reset: Perform mode2 reset.
   1168	 *
   1169	 * Mode2 reset generally does not reset as many IPs as mode1 reset. The
   1170	 * IPs reset varies by asic.
   1171	 */
   1172	int (*mode2_reset)(struct smu_context *smu);
   1173
   1174	/**
   1175	 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock
   1176	 *                         domain in MHz.
   1177	 */
   1178	int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
   1179
   1180	/**
   1181	 * @set_soft_freq_limited_range: Set the soft frequency range of a clock
   1182	 *                               domain in MHz.
   1183	 */
   1184	int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
   1185
   1186	/**
   1187	 * @set_power_source: Notify the SMU of the current power source.
   1188	 */
   1189	int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);
   1190
   1191	/**
   1192	 * @log_thermal_throttling_event: Print a thermal throttling warning to
   1193	 *                                the system's log.
   1194	 */
   1195	void (*log_thermal_throttling_event)(struct smu_context *smu);
   1196
   1197	/**
   1198	 * @get_pp_feature_mask: Print a human readable table of enabled
   1199	 *                       features to buffer.
   1200	 */
   1201	size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf);
   1202
   1203	/**
   1204	 * @set_pp_feature_mask: Request the SMU enable/disable features to
   1205	 *                       match those enabled in &new_mask.
   1206	 */
   1207	int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);
   1208
   1209	/**
   1210	 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU.
   1211	 *
   1212	 * Return: Size of &table
   1213	 */
   1214	ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);
   1215
   1216	/**
   1217	 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost.
   1218	 */
   1219	int (*enable_mgpu_fan_boost)(struct smu_context *smu);
   1220
   1221	/**
   1222	 * @gfx_ulv_control: Enable/disable ultra low voltage.
   1223	 */
   1224	int (*gfx_ulv_control)(struct smu_context *smu, bool enablement);
   1225
   1226	/**
   1227	 * @deep_sleep_control: Enable/disable deep sleep.
   1228	 */
   1229	int (*deep_sleep_control)(struct smu_context *smu, bool enablement);
   1230
   1231	/**
   1232	 * @get_fan_parameters: Get fan parameters.
   1233	 *
   1234	 * Get maximum fan speed from the power play table.
   1235	 */
   1236	int (*get_fan_parameters)(struct smu_context *smu);
   1237
   1238	/**
   1239	 * @post_init: Helper function for asic specific workarounds.
   1240	 */
   1241	int (*post_init)(struct smu_context *smu);
   1242
   1243	/**
   1244	 * @interrupt_work: Work task scheduled from SMU interrupt handler.
   1245	 */
   1246	void (*interrupt_work)(struct smu_context *smu);
   1247
   1248	/**
   1249	 * @gpo_control: Enable/disable graphics power optimization if supported.
   1250	 */
   1251	int (*gpo_control)(struct smu_context *smu, bool enablement);
   1252
   1253	/**
   1254	 * @gfx_state_change_set: Send the current graphics state to the SMU.
   1255	 */
   1256	int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state);
   1257
   1258	/**
   1259	 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock
   1260	 *                                      parameters to defaults.
   1261	 */
   1262	int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu);
   1263
   1264	/**
   1265	 * @smu_handle_passthrough_sbr:  Send message to SMU about special handling for SBR.
   1266	 */
   1267	int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable);
   1268
   1269	/**
   1270	 * @wait_for_event:  Wait for events from SMU.
   1271	 */
   1272	int (*wait_for_event)(struct smu_context *smu,
   1273			      enum smu_event_type event, uint64_t event_arg);
   1274
   1275	/**
   1276	 * @sned_hbm_bad_pages_num:  message SMU to update bad page number
   1277	 *										of SMUBUS table.
   1278	 */
   1279	int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size);
   1280
   1281	/**
   1282	 * @get_ecc_table:  message SMU to get ECC INFO table.
   1283	 */
   1284	ssize_t (*get_ecc_info)(struct smu_context *smu, void *table);
   1285	
   1286	
   1287	/**
   1288	 * @stb_collect_info: Collects Smart Trace Buffers data.
   1289	 */
   1290	int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size);
   1291
   1292	/**
   1293	 * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings.
   1294	 */
   1295	int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table);
   1296
   1297	/**
   1298	 * @set_config_table: Apply the input DriverSmuConfig table settings.
   1299	 */
   1300	int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table);
   1301
   1302	/**
   1303	 * @sned_hbm_bad_channel_flag:  message SMU to update bad channel info
   1304	 *										of SMUBUS table.
   1305	 */
   1306	int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size);
   1307
   1308	/**
   1309	 * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP
   1310	 */
   1311	int (*init_pptable_microcode)(struct smu_context *smu);
   1312};
   1313
   1314typedef enum {
   1315	METRICS_CURR_GFXCLK,
   1316	METRICS_CURR_SOCCLK,
   1317	METRICS_CURR_UCLK,
   1318	METRICS_CURR_VCLK,
   1319	METRICS_CURR_VCLK1,
   1320	METRICS_CURR_DCLK,
   1321	METRICS_CURR_DCLK1,
   1322	METRICS_CURR_FCLK,
   1323	METRICS_CURR_DCEFCLK,
   1324	METRICS_AVERAGE_CPUCLK,
   1325	METRICS_AVERAGE_GFXCLK,
   1326	METRICS_AVERAGE_SOCCLK,
   1327	METRICS_AVERAGE_FCLK,
   1328	METRICS_AVERAGE_UCLK,
   1329	METRICS_AVERAGE_VCLK,
   1330	METRICS_AVERAGE_DCLK,
   1331	METRICS_AVERAGE_VCLK1,
   1332	METRICS_AVERAGE_DCLK1,
   1333	METRICS_AVERAGE_GFXACTIVITY,
   1334	METRICS_AVERAGE_MEMACTIVITY,
   1335	METRICS_AVERAGE_VCNACTIVITY,
   1336	METRICS_AVERAGE_SOCKETPOWER,
   1337	METRICS_TEMPERATURE_EDGE,
   1338	METRICS_TEMPERATURE_HOTSPOT,
   1339	METRICS_TEMPERATURE_MEM,
   1340	METRICS_TEMPERATURE_VRGFX,
   1341	METRICS_TEMPERATURE_VRSOC,
   1342	METRICS_TEMPERATURE_VRMEM,
   1343	METRICS_THROTTLER_STATUS,
   1344	METRICS_CURR_FANSPEED,
   1345	METRICS_VOLTAGE_VDDSOC,
   1346	METRICS_VOLTAGE_VDDGFX,
   1347	METRICS_SS_APU_SHARE,
   1348	METRICS_SS_DGPU_SHARE,
   1349	METRICS_UNIQUE_ID_UPPER32,
   1350	METRICS_UNIQUE_ID_LOWER32,
   1351	METRICS_PCIE_RATE,
   1352	METRICS_PCIE_WIDTH,
   1353	METRICS_CURR_FANPWM,
   1354} MetricsMember_t;
   1355
   1356enum smu_cmn2asic_mapping_type {
   1357	CMN2ASIC_MAPPING_MSG,
   1358	CMN2ASIC_MAPPING_CLK,
   1359	CMN2ASIC_MAPPING_FEATURE,
   1360	CMN2ASIC_MAPPING_TABLE,
   1361	CMN2ASIC_MAPPING_PWR,
   1362	CMN2ASIC_MAPPING_WORKLOAD,
   1363};
   1364
   1365#define MSG_MAP(msg, index, valid_in_vf) \
   1366	[SMU_MSG_##msg] = {1, (index), (valid_in_vf)}
   1367
   1368#define CLK_MAP(clk, index) \
   1369	[SMU_##clk] = {1, (index)}
   1370
   1371#define FEA_MAP(fea) \
   1372	[SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
   1373
   1374#define FEA_MAP_REVERSE(fea) \
   1375	[SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT}
   1376
   1377#define FEA_MAP_HALF_REVERSE(fea) \
   1378	[SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT}
   1379
   1380#define TAB_MAP(tab) \
   1381	[SMU_TABLE_##tab] = {1, TABLE_##tab}
   1382
   1383#define TAB_MAP_VALID(tab) \
   1384	[SMU_TABLE_##tab] = {1, TABLE_##tab}
   1385
   1386#define TAB_MAP_INVALID(tab) \
   1387	[SMU_TABLE_##tab] = {0, TABLE_##tab}
   1388
   1389#define PWR_MAP(tab) \
   1390	[SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
   1391
   1392#define WORKLOAD_MAP(profile, workload) \
   1393	[profile] = {1, (workload)}
   1394
   1395/**
   1396 * smu_memcpy_trailing - Copy the end of one structure into the middle of another
   1397 *
   1398 * @dst: Pointer to destination struct
   1399 * @first_dst_member: The member name in @dst where the overwrite begins
   1400 * @last_dst_member: The member name in @dst where the overwrite ends after
   1401 * @src: Pointer to the source struct
   1402 * @first_src_member: The member name in @src where the copy begins
   1403 *
   1404 */
   1405#define smu_memcpy_trailing(dst, first_dst_member, last_dst_member,	   \
   1406			    src, first_src_member)			   \
   1407({									   \
   1408	size_t __src_offset = offsetof(typeof(*(src)), first_src_member);  \
   1409	size_t __src_size = sizeof(*(src)) - __src_offset;		   \
   1410	size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member);  \
   1411	size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \
   1412			    __dst_offset;				   \
   1413	BUILD_BUG_ON(__src_size != __dst_size);				   \
   1414	__builtin_memcpy((u8 *)(dst) + __dst_offset,			   \
   1415			 (u8 *)(src) + __src_offset,			   \
   1416			 __dst_size);					   \
   1417})
   1418
   1419#if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
   1420int smu_get_power_limit(void *handle,
   1421			uint32_t *limit,
   1422			enum pp_power_limit_level pp_limit_level,
   1423			enum pp_power_type pp_power_type);
   1424
   1425bool smu_mode1_reset_is_support(struct smu_context *smu);
   1426bool smu_mode2_reset_is_support(struct smu_context *smu);
   1427int smu_mode1_reset(struct smu_context *smu);
   1428
   1429extern const struct amd_ip_funcs smu_ip_funcs;
   1430
   1431bool is_support_sw_smu(struct amdgpu_device *adev);
   1432bool is_support_cclk_dpm(struct amdgpu_device *adev);
   1433int smu_write_watermarks_table(struct smu_context *smu);
   1434
   1435int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
   1436			   uint32_t *min, uint32_t *max);
   1437
   1438int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
   1439			    uint32_t min, uint32_t max);
   1440
   1441int smu_set_ac_dc(struct smu_context *smu);
   1442
   1443int smu_allow_xgmi_power_down(struct smu_context *smu, bool en);
   1444
   1445int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value);
   1446
   1447int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable);
   1448
   1449int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
   1450		       uint64_t event_arg);
   1451int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc);
   1452int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size);
   1453void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev);
   1454int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size);
   1455int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size);
   1456#endif
   1457#endif