cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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arcturus_ppsmc.h (5294B)


      1/*
      2 * Copyright 2019 Advanced Micro Devices, Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 */
     23
     24#ifndef ARCTURUS_PP_SMC_H
     25#define ARCTURUS_PP_SMC_H
     26
     27#pragma pack(push, 1)
     28
     29// SMU Response Codes:
     30#define PPSMC_Result_OK                    0x1
     31#define PPSMC_Result_Failed                0xFF
     32#define PPSMC_Result_UnknownCmd            0xFE
     33#define PPSMC_Result_CmdRejectedPrereq     0xFD
     34#define PPSMC_Result_CmdRejectedBusy       0xFC
     35
     36// Message Definitions:
     37// BASIC
     38#define PPSMC_MSG_TestMessage                    0x1
     39#define PPSMC_MSG_GetSmuVersion                  0x2
     40#define PPSMC_MSG_GetDriverIfVersion             0x3
     41#define PPSMC_MSG_SetAllowedFeaturesMaskLow      0x4
     42#define PPSMC_MSG_SetAllowedFeaturesMaskHigh     0x5
     43#define PPSMC_MSG_EnableAllSmuFeatures           0x6
     44#define PPSMC_MSG_DisableAllSmuFeatures          0x7
     45#define PPSMC_MSG_EnableSmuFeaturesLow           0x8
     46#define PPSMC_MSG_EnableSmuFeaturesHigh          0x9
     47#define PPSMC_MSG_DisableSmuFeaturesLow          0xA
     48#define PPSMC_MSG_DisableSmuFeaturesHigh         0xB
     49#define PPSMC_MSG_GetEnabledSmuFeaturesLow       0xC
     50#define PPSMC_MSG_GetEnabledSmuFeaturesHigh      0xD
     51#define PPSMC_MSG_SetDriverDramAddrHigh          0xE
     52#define PPSMC_MSG_SetDriverDramAddrLow           0xF
     53#define PPSMC_MSG_SetToolsDramAddrHigh           0x10
     54#define PPSMC_MSG_SetToolsDramAddrLow            0x11
     55#define PPSMC_MSG_TransferTableSmu2Dram          0x12
     56#define PPSMC_MSG_TransferTableDram2Smu          0x13
     57#define PPSMC_MSG_UseDefaultPPTable              0x14
     58#define PPSMC_MSG_UseBackupPPTable               0x15
     59#define PPSMC_MSG_SetSystemVirtualDramAddrHigh   0x16
     60#define PPSMC_MSG_SetSystemVirtualDramAddrLow    0x17
     61
     62//BACO/BAMACO/BOMACO
     63#define PPSMC_MSG_EnterBaco                      0x18
     64#define PPSMC_MSG_ExitBaco                       0x19
     65#define PPSMC_MSG_ArmD3                          0x1A
     66
     67//DPM
     68#define PPSMC_MSG_SetSoftMinByFreq               0x1B
     69#define PPSMC_MSG_SetSoftMaxByFreq               0x1C
     70#define PPSMC_MSG_SetHardMinByFreq               0x1D
     71#define PPSMC_MSG_SetHardMaxByFreq               0x1E
     72#define PPSMC_MSG_GetMinDpmFreq                  0x1F
     73#define PPSMC_MSG_GetMaxDpmFreq                  0x20
     74#define PPSMC_MSG_GetDpmFreqByIndex              0x21
     75
     76#define PPSMC_MSG_SetWorkloadMask                0x22
     77#define PPSMC_MSG_SetDfSwitchType                0x23
     78#define PPSMC_MSG_GetVoltageByDpm                0x24
     79#define PPSMC_MSG_GetVoltageByDpmOverdrive       0x25
     80
     81#define PPSMC_MSG_SetPptLimit                    0x26
     82#define PPSMC_MSG_GetPptLimit                    0x27
     83
     84//Power Gating
     85#define PPSMC_MSG_PowerUpVcn0                    0x28
     86#define PPSMC_MSG_PowerDownVcn0                  0x29
     87#define PPSMC_MSG_PowerUpVcn1                    0x2A
     88#define PPSMC_MSG_PowerDownVcn1                  0x2B
     89
     90//Resets and reload
     91#define PPSMC_MSG_PrepareMp1ForUnload            0x2C
     92#define PPSMC_MSG_PrepareMp1ForReset             0x2D
     93#define PPSMC_MSG_PrepareMp1ForShutdown          0x2E
     94#define PPSMC_MSG_SoftReset                      0x2F
     95
     96//BTC
     97#define PPSMC_MSG_RunAfllBtc                     0x30
     98#define PPSMC_MSG_RunDcBtc                       0x31
     99
    100//Debug
    101#define PPSMC_MSG_DramLogSetDramAddrHigh         0x33
    102#define PPSMC_MSG_DramLogSetDramAddrLow          0x34
    103#define PPSMC_MSG_DramLogSetDramSize             0x35
    104#define PPSMC_MSG_GetDebugData                   0x36
    105
    106//WAFL and XGMI
    107#define PPSMC_MSG_WaflTest                       0x37
    108#define PPSMC_MSG_SetXgmiMode                    0x38
    109
    110//Others
    111#define PPSMC_MSG_SetMemoryChannelEnable         0x39
    112
    113//OOB
    114#define PPSMC_MSG_SetNumBadHbmPagesRetired	 0x3A
    115
    116#define PPSMC_MSG_DFCstateControl		 0x3B
    117#define PPSMC_MSG_GmiPwrDnControl                0x3D
    118#define PPSMC_Message_Count                      0x3E
    119
    120#define PPSMC_MSG_ReadSerialNumTop32		 0x40
    121#define PPSMC_MSG_ReadSerialNumBottom32		 0x41
    122
    123/* paramater for MSG_LightSBR
    124 * 1 -- Enable light secondary bus reset, only do nbio respond without further handling,
    125 *      leave driver to handle the real reset
    126 * 0 -- Disable LightSBR, default behavior, SMU will pass the reset to PSP
    127 */
    128#define PPSMC_MSG_LightSBR			 0x42
    129
    130typedef uint32_t PPSMC_Result;
    131typedef uint32_t PPSMC_Msg;
    132#pragma pack(pop)
    133
    134#endif