smu_v13_0.h (9221B)
1/* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23#ifndef __SMU_V13_0_H__ 24#define __SMU_V13_0_H__ 25 26#include "amdgpu_smu.h" 27 28#define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF 29#define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x04 30#define SMU13_DRIVER_IF_VERSION_ALDE 0x08 31#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x04 32#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04 33#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x28 34#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x28 35 36#define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms 37 38/* MP Apertures */ 39#define MP0_Public 0x03800000 40#define MP0_SRAM 0x03900000 41#define MP1_Public 0x03b00000 42#define MP1_SRAM 0x03c00004 43 44/* address block */ 45#define smnMP1_FIRMWARE_FLAGS 0x3010024 46#define smnMP0_FW_INTF 0x30101c0 47#define smnMP1_PUB_CTRL 0x3010b14 48 49#define TEMP_RANGE_MIN (0) 50#define TEMP_RANGE_MAX (80 * 1000) 51 52#define SMU13_TOOL_SIZE 0x19000 53 54#define MAX_DPM_LEVELS 16 55#define MAX_PCIE_CONF 3 56 57#define CTF_OFFSET_EDGE 5 58#define CTF_OFFSET_HOTSPOT 5 59#define CTF_OFFSET_MEM 5 60 61struct smu_13_0_max_sustainable_clocks { 62 uint32_t display_clock; 63 uint32_t phy_clock; 64 uint32_t pixel_clock; 65 uint32_t uclock; 66 uint32_t dcef_clock; 67 uint32_t soc_clock; 68}; 69 70struct smu_13_0_dpm_clk_level { 71 bool enabled; 72 uint32_t value; 73}; 74 75struct smu_13_0_dpm_table { 76 uint32_t min; /* MHz */ 77 uint32_t max; /* MHz */ 78 uint32_t count; 79 bool is_fine_grained; 80 struct smu_13_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; 81}; 82 83struct smu_13_0_pcie_table { 84 uint8_t pcie_gen[MAX_PCIE_CONF]; 85 uint8_t pcie_lane[MAX_PCIE_CONF]; 86 uint16_t clk_freq[MAX_PCIE_CONF]; 87 uint32_t num_of_link_levels; 88}; 89 90struct smu_13_0_dpm_tables { 91 struct smu_13_0_dpm_table soc_table; 92 struct smu_13_0_dpm_table gfx_table; 93 struct smu_13_0_dpm_table uclk_table; 94 struct smu_13_0_dpm_table eclk_table; 95 struct smu_13_0_dpm_table vclk_table; 96 struct smu_13_0_dpm_table dclk_table; 97 struct smu_13_0_dpm_table dcef_table; 98 struct smu_13_0_dpm_table pixel_table; 99 struct smu_13_0_dpm_table display_table; 100 struct smu_13_0_dpm_table phy_table; 101 struct smu_13_0_dpm_table fclk_table; 102 struct smu_13_0_pcie_table pcie_table; 103}; 104 105struct smu_13_0_dpm_context { 106 struct smu_13_0_dpm_tables dpm_tables; 107 uint32_t workload_policy_mask; 108 uint32_t dcef_min_ds_clk; 109}; 110 111enum smu_13_0_power_state { 112 SMU_13_0_POWER_STATE__D0 = 0, 113 SMU_13_0_POWER_STATE__D1, 114 SMU_13_0_POWER_STATE__D3, /* Sleep*/ 115 SMU_13_0_POWER_STATE__D4, /* Hibernate*/ 116 SMU_13_0_POWER_STATE__D5, /* Power off*/ 117}; 118 119struct smu_13_0_power_context { 120 uint32_t power_source; 121 uint8_t in_power_limit_boost_mode; 122 enum smu_13_0_power_state power_state; 123}; 124 125enum smu_v13_0_baco_seq { 126 BACO_SEQ_BACO = 0, 127 BACO_SEQ_MSR, 128 BACO_SEQ_BAMACO, 129 BACO_SEQ_ULPS, 130 BACO_SEQ_COUNT, 131}; 132 133#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) 134 135int smu_v13_0_init_microcode(struct smu_context *smu); 136 137void smu_v13_0_fini_microcode(struct smu_context *smu); 138 139int smu_v13_0_load_microcode(struct smu_context *smu); 140 141int smu_v13_0_init_smc_tables(struct smu_context *smu); 142 143int smu_v13_0_fini_smc_tables(struct smu_context *smu); 144 145int smu_v13_0_init_power(struct smu_context *smu); 146 147int smu_v13_0_fini_power(struct smu_context *smu); 148 149int smu_v13_0_check_fw_status(struct smu_context *smu); 150 151int smu_v13_0_setup_pptable(struct smu_context *smu); 152 153int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu); 154 155int smu_v13_0_check_fw_version(struct smu_context *smu); 156 157int smu_v13_0_set_driver_table_location(struct smu_context *smu); 158 159int smu_v13_0_set_tool_table_location(struct smu_context *smu); 160 161int smu_v13_0_notify_memory_pool_location(struct smu_context *smu); 162 163int smu_v13_0_system_features_control(struct smu_context *smu, 164 bool en); 165 166int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count); 167 168int smu_v13_0_set_allowed_mask(struct smu_context *smu); 169 170int smu_v13_0_notify_display_change(struct smu_context *smu); 171 172int smu_v13_0_get_current_power_limit(struct smu_context *smu, 173 uint32_t *power_limit); 174 175int smu_v13_0_set_power_limit(struct smu_context *smu, 176 enum smu_ppt_limit_type limit_type, 177 uint32_t limit); 178 179int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu); 180 181int smu_v13_0_enable_thermal_alert(struct smu_context *smu); 182 183int smu_v13_0_disable_thermal_alert(struct smu_context *smu); 184 185int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value); 186 187int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk); 188 189int 190smu_v13_0_display_clock_voltage_request(struct smu_context *smu, 191 struct pp_display_clock_request 192 *clock_req); 193 194uint32_t 195smu_v13_0_get_fan_control_mode(struct smu_context *smu); 196 197int 198smu_v13_0_set_fan_control_mode(struct smu_context *smu, 199 uint32_t mode); 200 201int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu, 202 uint32_t speed); 203 204int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu, 205 uint32_t speed); 206 207int smu_v13_0_set_xgmi_pstate(struct smu_context *smu, 208 uint32_t pstate); 209 210int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable); 211 212int smu_v13_0_register_irq_handler(struct smu_context *smu); 213 214int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu); 215 216int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 217 struct pp_smu_nv_clock_table *max_clocks); 218 219bool smu_v13_0_baco_is_support(struct smu_context *smu); 220 221enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu); 222 223int smu_v13_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state); 224 225int smu_v13_0_baco_enter(struct smu_context *smu); 226int smu_v13_0_baco_exit(struct smu_context *smu); 227 228int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 229 uint32_t *min, uint32_t *max); 230 231int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, 232 uint32_t min, uint32_t max); 233 234int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu, 235 enum smu_clk_type clk_type, 236 uint32_t min, 237 uint32_t max); 238 239int smu_v13_0_set_performance_level(struct smu_context *smu, 240 enum amd_dpm_forced_level level); 241 242int smu_v13_0_set_power_source(struct smu_context *smu, 243 enum smu_power_src_type power_src); 244 245int smu_v13_0_set_single_dpm_table(struct smu_context *smu, 246 enum smu_clk_type clk_type, 247 struct smu_13_0_dpm_table *single_dpm_table); 248 249int smu_v13_0_get_dpm_level_range(struct smu_context *smu, 250 enum smu_clk_type clk_type, 251 uint32_t *min_value, 252 uint32_t *max_value); 253 254int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu); 255 256int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu); 257 258int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu); 259 260int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu); 261 262int smu_v13_0_gfx_ulv_control(struct smu_context *smu, 263 bool enablement); 264 265int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 266 uint64_t event_arg); 267 268int smu_v13_0_set_vcn_enable(struct smu_context *smu, 269 bool enable); 270 271int smu_v13_0_set_jpeg_enable(struct smu_context *smu, 272 bool enable); 273 274int smu_v13_0_init_pptable_microcode(struct smu_context *smu); 275 276int smu_v13_0_run_btc(struct smu_context *smu); 277 278int smu_v13_0_deep_sleep_control(struct smu_context *smu, 279 bool enablement); 280 281int smu_v13_0_gfx_ulv_control(struct smu_context *smu, 282 bool enablement); 283 284bool smu_v13_0_baco_is_support(struct smu_context *smu); 285 286enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu); 287 288int smu_v13_0_baco_set_state(struct smu_context *smu, 289 enum smu_baco_state state); 290 291int smu_v13_0_baco_enter(struct smu_context *smu); 292 293int smu_v13_0_baco_exit(struct smu_context *smu); 294 295int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, 296 enum PP_OD_DPM_TABLE_COMMAND type, 297 long input[], 298 uint32_t size); 299 300int smu_v13_0_set_default_dpm_tables(struct smu_context *smu); 301#endif 302#endif