anx7625.h (13823B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 7#ifndef __ANX7625_H__ 8#define __ANX7625_H__ 9 10#define ANX7625_DRV_VERSION "0.1.04" 11 12/* Loading OCM re-trying times */ 13#define OCM_LOADING_TIME 10 14 15/********* ANX7625 Register **********/ 16#define TX_P0_ADDR 0x70 17#define TX_P1_ADDR 0x7A 18#define TX_P2_ADDR 0x72 19 20#define RX_P0_ADDR 0x7e 21#define RX_P1_ADDR 0x84 22#define RX_P2_ADDR 0x54 23 24#define RSVD_00_ADDR 0x00 25#define RSVD_D1_ADDR 0xD1 26#define RSVD_60_ADDR 0x60 27#define RSVD_39_ADDR 0x39 28#define RSVD_7F_ADDR 0x7F 29 30#define TCPC_INTERFACE_ADDR 0x58 31 32/* Clock frequency in Hz */ 33#define XTAL_FRQ (27 * 1000000) 34 35#define POST_DIVIDER_MIN 1 36#define POST_DIVIDER_MAX 16 37#define PLL_OUT_FREQ_MIN 520000000UL 38#define PLL_OUT_FREQ_MAX 730000000UL 39#define PLL_OUT_FREQ_ABS_MIN 300000000UL 40#define PLL_OUT_FREQ_ABS_MAX 800000000UL 41#define MAX_UNSIGNED_24BIT 16777215UL 42 43/***************************************************************/ 44/* Register definition of device address 0x58 */ 45 46#define PRODUCT_ID_L 0x02 47#define PRODUCT_ID_H 0x03 48 49#define INTR_ALERT_1 0xCC 50#define INTR_SOFTWARE_INT BIT(3) 51#define INTR_RECEIVED_MSG BIT(5) 52 53#define SYSTEM_STSTUS 0x45 54#define INTERFACE_CHANGE_INT 0x44 55#define HPD_STATUS_CHANGE 0x80 56#define HPD_STATUS 0x80 57 58/******** END of I2C Address 0x58 ********/ 59 60/***************************************************************/ 61/* Register definition of device address 0x70 */ 62#define TX_HDCP_CTRL0 0x01 63#define STORE_AN BIT(7) 64#define RX_REPEATER BIT(6) 65#define RE_AUTHEN BIT(5) 66#define SW_AUTH_OK BIT(4) 67#define HARD_AUTH_EN BIT(3) 68#define ENC_EN BIT(2) 69#define BKSV_SRM_PASS BIT(1) 70#define KSVLIST_VLD BIT(0) 71 72#define SP_TX_WAIT_R0_TIME 0x40 73#define SP_TX_WAIT_KSVR_TIME 0x42 74#define SP_TX_SYS_CTRL1_REG 0x80 75#define HDCP2TX_FW_EN BIT(4) 76 77#define SP_TX_LINK_BW_SET_REG 0xA0 78#define SP_TX_LANE_COUNT_SET_REG 0xA1 79 80#define M_VID_0 0xC0 81#define M_VID_1 0xC1 82#define M_VID_2 0xC2 83#define N_VID_0 0xC3 84#define N_VID_1 0xC4 85#define N_VID_2 0xC5 86 87#define KEY_START_ADDR 0x9000 88#define KEY_RESERVED 416 89 90#define HDCP14KEY_START_ADDR (KEY_START_ADDR + KEY_RESERVED) 91#define HDCP14KEY_SIZE 624 92 93/***************************************************************/ 94/* Register definition of device address 0x72 */ 95#define AUX_RST 0x04 96#define RST_CTRL2 0x07 97 98#define SP_TX_TOTAL_LINE_STA_L 0x24 99#define SP_TX_TOTAL_LINE_STA_H 0x25 100#define SP_TX_ACT_LINE_STA_L 0x26 101#define SP_TX_ACT_LINE_STA_H 0x27 102#define SP_TX_V_F_PORCH_STA 0x28 103#define SP_TX_V_SYNC_STA 0x29 104#define SP_TX_V_B_PORCH_STA 0x2A 105#define SP_TX_TOTAL_PIXEL_STA_L 0x2B 106#define SP_TX_TOTAL_PIXEL_STA_H 0x2C 107#define SP_TX_ACT_PIXEL_STA_L 0x2D 108#define SP_TX_ACT_PIXEL_STA_H 0x2E 109#define SP_TX_H_F_PORCH_STA_L 0x2F 110#define SP_TX_H_F_PORCH_STA_H 0x30 111#define SP_TX_H_SYNC_STA_L 0x31 112#define SP_TX_H_SYNC_STA_H 0x32 113#define SP_TX_H_B_PORCH_STA_L 0x33 114#define SP_TX_H_B_PORCH_STA_H 0x34 115 116#define SP_TX_VID_CTRL 0x84 117#define SP_TX_BPC_MASK 0xE0 118#define SP_TX_BPC_6 0x00 119#define SP_TX_BPC_8 0x20 120#define SP_TX_BPC_10 0x40 121#define SP_TX_BPC_12 0x60 122 123#define VIDEO_BIT_MATRIX_12 0x4c 124 125#define AUDIO_CHANNEL_STATUS_1 0xd0 126#define AUDIO_CHANNEL_STATUS_2 0xd1 127#define AUDIO_CHANNEL_STATUS_3 0xd2 128#define AUDIO_CHANNEL_STATUS_4 0xd3 129#define AUDIO_CHANNEL_STATUS_5 0xd4 130#define AUDIO_CHANNEL_STATUS_6 0xd5 131#define TDM_SLAVE_MODE 0x10 132#define I2S_SLAVE_MODE 0x08 133#define AUDIO_LAYOUT 0x01 134 135#define AUDIO_CONTROL_REGISTER 0xe6 136#define TDM_TIMING_MODE 0x08 137 138#define I2C_ADDR_72_DPTX 0x72 139 140#define HP_MIN 8 141#define HBLANKING_MIN 80 142#define SYNC_LEN_DEF 32 143#define HFP_HBP_DEF ((HBLANKING_MIN - SYNC_LEN_DEF) / 2) 144#define VIDEO_CONTROL_0 0x08 145 146#define ACTIVE_LINES_L 0x14 147#define ACTIVE_LINES_H 0x15 /* Bit[7:6] are reserved */ 148#define VERTICAL_FRONT_PORCH 0x16 149#define VERTICAL_SYNC_WIDTH 0x17 150#define VERTICAL_BACK_PORCH 0x18 151 152#define HORIZONTAL_TOTAL_PIXELS_L 0x19 153#define HORIZONTAL_TOTAL_PIXELS_H 0x1A /* Bit[7:6] are reserved */ 154#define HORIZONTAL_ACTIVE_PIXELS_L 0x1B 155#define HORIZONTAL_ACTIVE_PIXELS_H 0x1C /* Bit[7:6] are reserved */ 156#define HORIZONTAL_FRONT_PORCH_L 0x1D 157#define HORIZONTAL_FRONT_PORCH_H 0x1E /* Bit[7:4] are reserved */ 158#define HORIZONTAL_SYNC_WIDTH_L 0x1F 159#define HORIZONTAL_SYNC_WIDTH_H 0x20 /* Bit[7:4] are reserved */ 160#define HORIZONTAL_BACK_PORCH_L 0x21 161#define HORIZONTAL_BACK_PORCH_H 0x22 /* Bit[7:4] are reserved */ 162 163/******** END of I2C Address 0x72 *********/ 164 165/***************************************************************/ 166/* Register definition of device address 0x7a */ 167#define DP_TX_SWING_REG_CNT 0x14 168#define DP_TX_LANE0_SWING_REG0 0x00 169#define DP_TX_LANE1_SWING_REG0 0x14 170/******** END of I2C Address 0x7a *********/ 171 172/***************************************************************/ 173/* Register definition of device address 0x7e */ 174 175#define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E 176 177#define R_BOOT_RETRY 0x00 178#define R_RAM_ADDR_H 0x01 179#define R_RAM_ADDR_L 0x02 180#define R_RAM_LEN_H 0x03 181#define R_RAM_LEN_L 0x04 182#define FLASH_LOAD_STA 0x05 183#define FLASH_LOAD_STA_CHK BIT(7) 184 185#define R_RAM_CTRL 0x05 186/* bit positions */ 187#define FLASH_DONE BIT(7) 188#define BOOT_LOAD_DONE BIT(6) 189#define CRC_OK BIT(5) 190#define LOAD_DONE BIT(4) 191#define O_RW_DONE BIT(3) 192#define FUSE_BUSY BIT(2) 193#define DECRYPT_EN BIT(1) 194#define LOAD_START BIT(0) 195 196#define FLASH_ADDR_HIGH 0x0F 197#define FLASH_ADDR_LOW 0x10 198#define FLASH_LEN_HIGH 0x31 199#define FLASH_LEN_LOW 0x32 200#define R_FLASH_RW_CTRL 0x33 201/* bit positions */ 202#define READ_DELAY_SELECT BIT(7) 203#define GENERAL_INSTRUCTION_EN BIT(6) 204#define FLASH_ERASE_EN BIT(5) 205#define RDID_READ_EN BIT(4) 206#define REMS_READ_EN BIT(3) 207#define WRITE_STATUS_EN BIT(2) 208#define FLASH_READ BIT(1) 209#define FLASH_WRITE BIT(0) 210 211#define FLASH_BUF_BASE_ADDR 0x60 212#define FLASH_BUF_LEN 0x20 213 214#define XTAL_FRQ_SEL 0x3F 215/* bit field positions */ 216#define XTAL_FRQ_SEL_POS 5 217/* bit field values */ 218#define XTAL_FRQ_19M2 (0 << XTAL_FRQ_SEL_POS) 219#define XTAL_FRQ_27M (4 << XTAL_FRQ_SEL_POS) 220 221#define R_DSC_CTRL_0 0x40 222#define READ_STATUS_EN 7 223#define CLK_1MEG_RB 6 /* 1MHz clock reset; 0=reset, 0=reset release */ 224#define DSC_BIST_DONE 1 /* Bit[5:1]: 1=DSC MBIST pass */ 225#define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */ 226 227#define OCM_FW_VERSION 0x31 228#define OCM_FW_REVERSION 0x32 229 230#define AP_AUX_ADDR_7_0 0x11 231#define AP_AUX_ADDR_15_8 0x12 232#define AP_AUX_ADDR_19_16 0x13 233 234/* Bit[0:3] AUX status, bit 4 op_en, bit 5 address only */ 235#define AP_AUX_CTRL_STATUS 0x14 236#define AP_AUX_CTRL_OP_EN 0x10 237#define AP_AUX_CTRL_ADDRONLY 0x20 238 239#define AP_AUX_BUFF_START 0x15 240#define PIXEL_CLOCK_L 0x25 241#define PIXEL_CLOCK_H 0x26 242 243#define AP_AUX_COMMAND 0x27 /* com+len */ 244#define LENGTH_SHIFT 4 245#define DPCD_CMD(len, cmd) ((((len) - 1) << LENGTH_SHIFT) | (cmd)) 246 247/* Bit 0&1: 3D video structure */ 248/* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */ 249#define AP_AV_STATUS 0x28 250#define AP_VIDEO_CHG BIT(2) 251#define AP_AUDIO_CHG BIT(3) 252#define AP_MIPI_MUTE BIT(4) /* 1:MIPI input mute, 0: ummute */ 253#define AP_MIPI_RX_EN BIT(5) /* 1: MIPI RX input in 0: no RX in */ 254#define AP_DISABLE_PD BIT(6) 255#define AP_DISABLE_DISPLAY BIT(7) 256/***************************************************************/ 257/* Register definition of device address 0x84 */ 258#define MIPI_PHY_CONTROL_3 0x03 259#define MIPI_HS_PWD_CLK 7 260#define MIPI_HS_RT_CLK 6 261#define MIPI_PD_CLK 5 262#define MIPI_CLK_RT_MANUAL_PD_EN 4 263#define MIPI_CLK_HS_MANUAL_PD_EN 3 264#define MIPI_CLK_DET_DET_BYPASS 2 265#define MIPI_CLK_MISS_CTRL 1 266#define MIPI_PD_LPTX_CH_MANUAL_PD_EN 0 267 268#define MIPI_LANE_CTRL_0 0x05 269#define MIPI_TIME_HS_PRPR 0x08 270 271/* 272 * After MIPI RX protocol layer received video frames, 273 * Protocol layer starts to reconstruct video stream from PHY 274 */ 275#define MIPI_VIDEO_STABLE_CNT 0x0A 276 277#define MIPI_LANE_CTRL_10 0x0F 278#define MIPI_DIGITAL_ADJ_1 0x1B 279#define IVO_MID0 0x26 280#define IVO_MID1 0xCF 281 282#define MIPI_PLL_M_NUM_23_16 0x1E 283#define MIPI_PLL_M_NUM_15_8 0x1F 284#define MIPI_PLL_M_NUM_7_0 0x20 285#define MIPI_PLL_N_NUM_23_16 0x21 286#define MIPI_PLL_N_NUM_15_8 0x22 287#define MIPI_PLL_N_NUM_7_0 0x23 288 289#define MIPI_DIGITAL_PLL_6 0x2A 290/* Bit[7:6]: VCO band control, only effective */ 291#define MIPI_M_NUM_READY 0x10 292#define MIPI_N_NUM_READY 0x08 293#define STABLE_INTEGER_CNT_EN 0x04 294#define MIPI_PLL_TEST_BIT 0 295/* Bit[1:0]: test point output select - */ 296/* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */ 297 298#define MIPI_DIGITAL_PLL_7 0x2B 299#define MIPI_PLL_FORCE_N_EN 7 300#define MIPI_PLL_FORCE_BAND_EN 6 301 302#define MIPI_PLL_VCO_TUNE_REG 4 303/* Bit[5:4]: VCO metal capacitance - */ 304/* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */ 305#define MIPI_PLL_VCO_TUNE_REG_VAL 0x30 306 307#define MIPI_PLL_PLL_LDO_BIT 2 308/* Bit[3:2]: vco_v2i power - */ 309/* 00: 1.40V, 01: 1.45V (default), 10: 1.50V, 11: 1.55V */ 310#define MIPI_PLL_RESET_N 0x02 311#define MIPI_FRQ_FORCE_NDET 0 312 313#define MIPI_ALERT_CLR_0 0x2D 314#define HS_link_error_clear 7 315/* This bit itself is S/C, and it clears 0x84:0x31[7] */ 316 317#define MIPI_ALERT_OUT_0 0x31 318#define check_sum_err_hs_sync 7 319/* This bit is cleared by 0x84:0x2D[7] */ 320 321#define MIPI_DIGITAL_PLL_8 0x33 322#define MIPI_POST_DIV_VAL 4 323/* N means divided by (n+1), n = 0~15 */ 324#define MIPI_EN_LOCK_FRZ 3 325#define MIPI_FRQ_COUNTER_RST 2 326#define MIPI_FRQ_SET_REG_8 1 327/* Bit 0 is reserved */ 328 329#define MIPI_DIGITAL_PLL_9 0x34 330 331#define MIPI_DIGITAL_PLL_16 0x3B 332#define MIPI_FRQ_FREEZE_NDET 7 333#define MIPI_FRQ_REG_SET_ENABLE 6 334#define MIPI_REG_FORCE_SEL_EN 5 335#define MIPI_REG_SEL_DIV_REG 4 336#define MIPI_REG_FORCE_PRE_DIV_EN 3 337/* Bit 2 is reserved */ 338#define MIPI_FREF_D_IND 1 339#define REF_CLK_27000KHZ 1 340#define REF_CLK_19200KHZ 0 341#define MIPI_REG_PLL_PLL_TEST_ENABLE 0 342 343#define MIPI_DIGITAL_PLL_18 0x3D 344#define FRQ_COUNT_RB_SEL 7 345#define REG_FORCE_POST_DIV_EN 6 346#define MIPI_DPI_SELECT 5 347#define SELECT_DSI 1 348#define SELECT_DPI 0 349#define REG_BAUD_DIV_RATIO 0 350 351#define H_BLANK_L 0x3E 352/* For DSC only */ 353#define H_BLANK_H 0x3F 354/* For DSC only; note: bit[7:6] are reserved */ 355#define MIPI_SWAP 0x4A 356#define MIPI_SWAP_CH0 7 357#define MIPI_SWAP_CH1 6 358#define MIPI_SWAP_CH2 5 359#define MIPI_SWAP_CH3 4 360#define MIPI_SWAP_CLK 3 361/* Bit[2:0] are reserved */ 362 363/******** END of I2C Address 0x84 *********/ 364 365/* DPCD regs */ 366#define DPCD_DPCD_REV 0x00 367#define DPCD_MAX_LINK_RATE 0x01 368#define DPCD_MAX_LANE_COUNT 0x02 369 370/********* ANX7625 Register End **********/ 371 372/***************** Display *****************/ 373enum audio_fs { 374 AUDIO_FS_441K = 0x00, 375 AUDIO_FS_48K = 0x02, 376 AUDIO_FS_32K = 0x03, 377 AUDIO_FS_882K = 0x08, 378 AUDIO_FS_96K = 0x0a, 379 AUDIO_FS_1764K = 0x0c, 380 AUDIO_FS_192K = 0x0e 381}; 382 383enum audio_wd_len { 384 AUDIO_W_LEN_16_20MAX = 0x02, 385 AUDIO_W_LEN_18_20MAX = 0x04, 386 AUDIO_W_LEN_17_20MAX = 0x0c, 387 AUDIO_W_LEN_19_20MAX = 0x08, 388 AUDIO_W_LEN_20_20MAX = 0x0a, 389 AUDIO_W_LEN_20_24MAX = 0x03, 390 AUDIO_W_LEN_22_24MAX = 0x05, 391 AUDIO_W_LEN_21_24MAX = 0x0d, 392 AUDIO_W_LEN_23_24MAX = 0x09, 393 AUDIO_W_LEN_24_24MAX = 0x0b 394}; 395 396#define I2S_CH_2 0x01 397#define TDM_CH_4 0x03 398#define TDM_CH_6 0x05 399#define TDM_CH_8 0x07 400 401#define MAX_DPCD_BUFFER_SIZE 16 402 403#define ONE_BLOCK_SIZE 128 404#define FOUR_BLOCK_SIZE (128 * 4) 405 406#define MAX_EDID_BLOCK 3 407#define EDID_TRY_CNT 3 408#define SUPPORT_PIXEL_CLOCK 300000 409 410struct s_edid_data { 411 int edid_block_num; 412 u8 edid_raw_data[FOUR_BLOCK_SIZE]; 413}; 414 415/***************** Display End *****************/ 416 417#define MAX_LANES_SUPPORT 4 418 419struct anx7625_platform_data { 420 struct gpio_desc *gpio_p_on; 421 struct gpio_desc *gpio_reset; 422 struct regulator_bulk_data supplies[3]; 423 struct drm_bridge *panel_bridge; 424 int intp_irq; 425 int is_dpi; 426 int mipi_lanes; 427 int audio_en; 428 int dp_lane0_swing_reg_cnt; 429 u8 lane0_reg_data[DP_TX_SWING_REG_CNT]; 430 int dp_lane1_swing_reg_cnt; 431 u8 lane1_reg_data[DP_TX_SWING_REG_CNT]; 432 u32 low_power_mode; 433 struct device_node *mipi_host_node; 434}; 435 436struct anx7625_i2c_client { 437 struct i2c_client *tx_p0_client; 438 struct i2c_client *tx_p1_client; 439 struct i2c_client *tx_p2_client; 440 struct i2c_client *rx_p0_client; 441 struct i2c_client *rx_p1_client; 442 struct i2c_client *rx_p2_client; 443 struct i2c_client *tcpc_client; 444}; 445 446struct anx7625_data { 447 struct anx7625_platform_data pdata; 448 struct platform_device *audio_pdev; 449 int hpd_status; 450 int hpd_high_cnt; 451 int dp_en; 452 int hdcp_cp; 453 /* Lock for work queue */ 454 struct mutex lock; 455 struct i2c_client *client; 456 struct anx7625_i2c_client i2c; 457 struct i2c_client *last_client; 458 struct timer_list hdcp_timer; 459 struct s_edid_data slimport_edid_p; 460 struct device *codec_dev; 461 hdmi_codec_plugged_cb plugged_cb; 462 struct work_struct work; 463 struct workqueue_struct *workqueue; 464 struct delayed_work hdcp_work; 465 struct workqueue_struct *hdcp_workqueue; 466 /* Lock for hdcp work queue */ 467 struct mutex hdcp_wq_lock; 468 char edid_block; 469 struct display_timing dt; 470 u8 display_timing_valid; 471 struct drm_bridge bridge; 472 u8 bridge_attached; 473 struct drm_connector *connector; 474 struct mipi_dsi_device *dsi; 475 struct drm_dp_aux aux; 476}; 477 478#endif /* __ANX7625_H__ */