sil-sii8620.h (52162B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Registers of Silicon Image SiI8620 Mobile HD Transmitter 4 * 5 * Copyright (C) 2015, Samsung Electronics Co., Ltd. 6 * Andrzej Hajda <a.hajda@samsung.com> 7 * 8 * Based on MHL driver for Android devices. 9 * Copyright (C) 2013-2014 Silicon Image, Inc. 10 */ 11 12#ifndef __SIL_SII8620_H__ 13#define __SIL_SII8620_H__ 14 15/* Vendor ID Low byte, default value: 0x01 */ 16#define REG_VND_IDL 0x0000 17 18/* Vendor ID High byte, default value: 0x00 */ 19#define REG_VND_IDH 0x0001 20 21/* Device ID Low byte, default value: 0x60 */ 22#define REG_DEV_IDL 0x0002 23 24/* Device ID High byte, default value: 0x86 */ 25#define REG_DEV_IDH 0x0003 26 27/* Device Revision, default value: 0x10 */ 28#define REG_DEV_REV 0x0004 29 30/* OTP DBYTE510, default value: 0x00 */ 31#define REG_OTP_DBYTE510 0x0006 32 33/* System Control #1, default value: 0x00 */ 34#define REG_SYS_CTRL1 0x0008 35#define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7) 36#define BIT_SYS_CTRL1_VSYNCPIN BIT(6) 37#define BIT_SYS_CTRL1_OTPADROPOVR_SET BIT(5) 38#define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4) 39#define BIT_SYS_CTRL1_OTP2XVOVR_EN BIT(3) 40#define BIT_SYS_CTRL1_OTP2XAOVR_EN BIT(2) 41#define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1) 42#define BIT_SYS_CTRL1_OTPAMUTEOVR_SET BIT(0) 43 44/* System Control DPD, default value: 0x90 */ 45#define REG_DPD 0x000b 46#define BIT_DPD_PWRON_PLL BIT(7) 47#define BIT_DPD_PDNTX12 BIT(6) 48#define BIT_DPD_PDNRX12 BIT(5) 49#define BIT_DPD_OSC_EN BIT(4) 50#define BIT_DPD_PWRON_HSIC BIT(3) 51#define BIT_DPD_PDIDCK_N BIT(2) 52#define BIT_DPD_PD_MHL_CLK_N BIT(1) 53 54/* Dual link Control, default value: 0x00 */ 55#define REG_DCTL 0x000d 56#define BIT_DCTL_TDM_LCLK_PHASE BIT(7) 57#define BIT_DCTL_HSIC_CLK_PHASE BIT(6) 58#define BIT_DCTL_CTS_TCK_PHASE BIT(5) 59#define BIT_DCTL_EXT_DDC_SEL BIT(4) 60#define BIT_DCTL_TRANSCODE BIT(3) 61#define BIT_DCTL_HSIC_RX_STROBE_PHASE BIT(2) 62#define BIT_DCTL_HSIC_TX_BIST_START_SEL BIT(1) 63#define BIT_DCTL_TCLKNX_PHASE BIT(0) 64 65/* PWD Software Reset, default value: 0x20 */ 66#define REG_PWD_SRST 0x000e 67#define BIT_PWD_SRST_COC_DOC_RST BIT(7) 68#define BIT_PWD_SRST_CBUS_RST_SW BIT(6) 69#define BIT_PWD_SRST_CBUS_RST_SW_EN BIT(5) 70#define BIT_PWD_SRST_MHLFIFO_RST BIT(4) 71#define BIT_PWD_SRST_CBUS_RST BIT(3) 72#define BIT_PWD_SRST_SW_RST_AUTO BIT(2) 73#define BIT_PWD_SRST_HDCP2X_SW_RST BIT(1) 74#define BIT_PWD_SRST_SW_RST BIT(0) 75 76/* AKSV_1, default value: 0x00 */ 77#define REG_AKSV_1 0x001d 78 79/* Video H Resolution #1, default value: 0x00 */ 80#define REG_H_RESL 0x003a 81 82/* Video Mode, default value: 0x00 */ 83#define REG_VID_MODE 0x004a 84#define BIT_VID_MODE_M1080P BIT(6) 85 86/* Video Input Mode, default value: 0xc0 */ 87#define REG_VID_OVRRD 0x0051 88#define BIT_VID_OVRRD_PP_AUTO_DISABLE BIT(7) 89#define BIT_VID_OVRRD_M1080P_OVRRD BIT(6) 90#define BIT_VID_OVRRD_MINIVSYNC_ON BIT(5) 91#define BIT_VID_OVRRD_3DCONV_EN_FRAME_PACK BIT(4) 92#define BIT_VID_OVRRD_ENABLE_AUTO_PATH_EN BIT(3) 93#define BIT_VID_OVRRD_ENRGB2YCBCR_OVRRD BIT(2) 94#define BIT_VID_OVRRD_ENDOWNSAMPLE_OVRRD BIT(0) 95 96/* I2C Address reassignment, default value: 0x00 */ 97#define REG_PAGE_MHLSPEC_ADDR 0x0057 98#define REG_PAGE7_ADDR 0x0058 99#define REG_PAGE8_ADDR 0x005c 100 101/* Fast Interrupt Status, default value: 0x00 */ 102#define REG_FAST_INTR_STAT 0x005f 103#define LEN_FAST_INTR_STAT 7 104#define BIT_FAST_INTR_STAT_TIMR 8 105#define BIT_FAST_INTR_STAT_INT2 9 106#define BIT_FAST_INTR_STAT_DDC 10 107#define BIT_FAST_INTR_STAT_SCDT 11 108#define BIT_FAST_INTR_STAT_INFR 13 109#define BIT_FAST_INTR_STAT_EDID 14 110#define BIT_FAST_INTR_STAT_HDCP 15 111#define BIT_FAST_INTR_STAT_MSC 16 112#define BIT_FAST_INTR_STAT_MERR 17 113#define BIT_FAST_INTR_STAT_G2WB 18 114#define BIT_FAST_INTR_STAT_G2WB_ERR 19 115#define BIT_FAST_INTR_STAT_DISC 28 116#define BIT_FAST_INTR_STAT_BLOCK 30 117#define BIT_FAST_INTR_STAT_LTRN 31 118#define BIT_FAST_INTR_STAT_HDCP2 32 119#define BIT_FAST_INTR_STAT_TDM 42 120#define BIT_FAST_INTR_STAT_COC 51 121 122/* GPIO Control, default value: 0x15 */ 123#define REG_GPIO_CTRL1 0x006e 124#define BIT_CTRL1_GPIO_I_8 BIT(5) 125#define BIT_CTRL1_GPIO_OEN_8 BIT(4) 126#define BIT_CTRL1_GPIO_I_7 BIT(3) 127#define BIT_CTRL1_GPIO_OEN_7 BIT(2) 128#define BIT_CTRL1_GPIO_I_6 BIT(1) 129#define BIT_CTRL1_GPIO_OEN_6 BIT(0) 130 131/* Interrupt Control, default value: 0x06 */ 132#define REG_INT_CTRL 0x006f 133#define BIT_INT_CTRL_SOFTWARE_WP BIT(7) 134#define BIT_INT_CTRL_INTR_OD BIT(2) 135#define BIT_INT_CTRL_INTR_POLARITY BIT(1) 136 137/* Interrupt State, default value: 0x00 */ 138#define REG_INTR_STATE 0x0070 139#define BIT_INTR_STATE_INTR_STATE BIT(0) 140 141/* Interrupt Source #1, default value: 0x00 */ 142#define REG_INTR1 0x0071 143 144/* Interrupt Source #2, default value: 0x00 */ 145#define REG_INTR2 0x0072 146 147/* Interrupt Source #3, default value: 0x01 */ 148#define REG_INTR3 0x0073 149#define BIT_DDC_CMD_DONE BIT(3) 150 151/* Interrupt Source #5, default value: 0x00 */ 152#define REG_INTR5 0x0074 153 154/* Interrupt #1 Mask, default value: 0x00 */ 155#define REG_INTR1_MASK 0x0075 156 157/* Interrupt #2 Mask, default value: 0x00 */ 158#define REG_INTR2_MASK 0x0076 159 160/* Interrupt #3 Mask, default value: 0x00 */ 161#define REG_INTR3_MASK 0x0077 162 163/* Interrupt #5 Mask, default value: 0x00 */ 164#define REG_INTR5_MASK 0x0078 165#define BIT_INTR_SCDT_CHANGE BIT(0) 166 167/* Hot Plug Connection Control, default value: 0x45 */ 168#define REG_HPD_CTRL 0x0079 169#define BIT_HPD_CTRL_HPD_DS_SIGNAL BIT(7) 170#define BIT_HPD_CTRL_HPD_OUT_OD_EN BIT(6) 171#define BIT_HPD_CTRL_HPD_HIGH BIT(5) 172#define BIT_HPD_CTRL_HPD_OUT_OVR_EN BIT(4) 173#define BIT_HPD_CTRL_GPIO_I_1 BIT(3) 174#define BIT_HPD_CTRL_GPIO_OEN_1 BIT(2) 175#define BIT_HPD_CTRL_GPIO_I_0 BIT(1) 176#define BIT_HPD_CTRL_GPIO_OEN_0 BIT(0) 177 178/* GPIO Control, default value: 0x55 */ 179#define REG_GPIO_CTRL 0x007a 180#define BIT_CTRL_GPIO_I_5 BIT(7) 181#define BIT_CTRL_GPIO_OEN_5 BIT(6) 182#define BIT_CTRL_GPIO_I_4 BIT(5) 183#define BIT_CTRL_GPIO_OEN_4 BIT(4) 184#define BIT_CTRL_GPIO_I_3 BIT(3) 185#define BIT_CTRL_GPIO_OEN_3 BIT(2) 186#define BIT_CTRL_GPIO_I_2 BIT(1) 187#define BIT_CTRL_GPIO_OEN_2 BIT(0) 188 189/* Interrupt Source 7, default value: 0x00 */ 190#define REG_INTR7 0x007b 191 192/* Interrupt Source 8, default value: 0x00 */ 193#define REG_INTR8 0x007c 194 195/* Interrupt #7 Mask, default value: 0x00 */ 196#define REG_INTR7_MASK 0x007d 197 198/* Interrupt #8 Mask, default value: 0x00 */ 199#define REG_INTR8_MASK 0x007e 200#define BIT_CEA_NEW_VSI BIT(2) 201#define BIT_CEA_NEW_AVI BIT(1) 202 203/* IEEE, default value: 0x10 */ 204#define REG_TMDS_CCTRL 0x0080 205#define BIT_TMDS_CCTRL_TMDS_OE BIT(4) 206 207/* TMDS Control #4, default value: 0x02 */ 208#define REG_TMDS_CTRL4 0x0085 209#define BIT_TMDS_CTRL4_SCDT_CKDT_SEL BIT(1) 210#define BIT_TMDS_CTRL4_TX_EN_BY_SCDT BIT(0) 211 212/* BIST CNTL, default value: 0x00 */ 213#define REG_BIST_CTRL 0x00bb 214#define BIT_RXBIST_VGB_EN BIT(7) 215#define BIT_TXBIST_VGB_EN BIT(6) 216#define BIT_BIST_START_SEL BIT(5) 217#define BIT_BIST_START_BIT BIT(4) 218#define BIT_BIST_ALWAYS_ON BIT(3) 219#define BIT_BIST_TRANS BIT(2) 220#define BIT_BIST_RESET BIT(1) 221#define BIT_BIST_EN BIT(0) 222 223/* BIST DURATION0, default value: 0x00 */ 224#define REG_BIST_TEST_SEL 0x00bd 225#define MSK_BIST_TEST_SEL_BIST_PATT_SEL 0x0f 226 227/* BIST VIDEO_MODE, default value: 0x00 */ 228#define REG_BIST_VIDEO_MODE 0x00be 229#define MSK_BIST_VIDEO_MODE_BIST_VIDEO_MODE_3_0 0x0f 230 231/* BIST DURATION0, default value: 0x00 */ 232#define REG_BIST_DURATION_0 0x00bf 233 234/* BIST DURATION1, default value: 0x00 */ 235#define REG_BIST_DURATION_1 0x00c0 236 237/* BIST DURATION2, default value: 0x00 */ 238#define REG_BIST_DURATION_2 0x00c1 239 240/* BIST 8BIT_PATTERN, default value: 0x00 */ 241#define REG_BIST_8BIT_PATTERN 0x00c2 242 243/* LM DDC, default value: 0x80 */ 244#define REG_LM_DDC 0x00c7 245#define BIT_LM_DDC_SW_TPI_EN_DISABLED BIT(7) 246 247#define BIT_LM_DDC_VIDEO_MUTE_EN BIT(5) 248#define BIT_LM_DDC_DDC_TPI_SW BIT(2) 249#define BIT_LM_DDC_DDC_GRANT BIT(1) 250#define BIT_LM_DDC_DDC_GPU_REQUEST BIT(0) 251 252/* DDC I2C Manual, default value: 0x03 */ 253#define REG_DDC_MANUAL 0x00ec 254#define BIT_DDC_MANUAL_MAN_DDC BIT(7) 255#define BIT_DDC_MANUAL_VP_SEL BIT(6) 256#define BIT_DDC_MANUAL_DSDA BIT(5) 257#define BIT_DDC_MANUAL_DSCL BIT(4) 258#define BIT_DDC_MANUAL_GCP_HW_CTL_EN BIT(3) 259#define BIT_DDC_MANUAL_DDCM_ABORT_WP BIT(2) 260#define BIT_DDC_MANUAL_IO_DSDA BIT(1) 261#define BIT_DDC_MANUAL_IO_DSCL BIT(0) 262 263/* DDC I2C Target Slave Address, default value: 0x00 */ 264#define REG_DDC_ADDR 0x00ed 265#define MSK_DDC_ADDR_DDC_ADDR 0xfe 266 267/* DDC I2C Target Segment Address, default value: 0x00 */ 268#define REG_DDC_SEGM 0x00ee 269 270/* DDC I2C Target Offset Address, default value: 0x00 */ 271#define REG_DDC_OFFSET 0x00ef 272 273/* DDC I2C Data In count #1, default value: 0x00 */ 274#define REG_DDC_DIN_CNT1 0x00f0 275 276/* DDC I2C Data In count #2, default value: 0x00 */ 277#define REG_DDC_DIN_CNT2 0x00f1 278#define MSK_DDC_DIN_CNT2_DDC_DIN_CNT_9_8 0x03 279 280/* DDC I2C Status, default value: 0x04 */ 281#define REG_DDC_STATUS 0x00f2 282#define BIT_DDC_STATUS_DDC_BUS_LOW BIT(6) 283#define BIT_DDC_STATUS_DDC_NO_ACK BIT(5) 284#define BIT_DDC_STATUS_DDC_I2C_IN_PROG BIT(4) 285#define BIT_DDC_STATUS_DDC_FIFO_FULL BIT(3) 286#define BIT_DDC_STATUS_DDC_FIFO_EMPTY BIT(2) 287#define BIT_DDC_STATUS_DDC_FIFO_READ_IN_SUE BIT(1) 288#define BIT_DDC_STATUS_DDC_FIFO_WRITE_IN_USE BIT(0) 289 290/* DDC I2C Command, default value: 0x70 */ 291#define REG_DDC_CMD 0x00f3 292#define BIT_DDC_CMD_HDCP_DDC_EN BIT(6) 293#define BIT_DDC_CMD_SDA_DEL_EN BIT(5) 294#define BIT_DDC_CMD_DDC_FLT_EN BIT(4) 295 296#define MSK_DDC_CMD_DDC_CMD 0x0f 297#define VAL_DDC_CMD_ENH_DDC_READ_NO_ACK 0x04 298#define VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO 0x09 299#define VAL_DDC_CMD_DDC_CMD_ABORT 0x0f 300 301/* DDC I2C FIFO Data In/Out, default value: 0x00 */ 302#define REG_DDC_DATA 0x00f4 303 304/* DDC I2C Data Out Counter, default value: 0x00 */ 305#define REG_DDC_DOUT_CNT 0x00f5 306#define BIT_DDC_DOUT_CNT_DDC_DELAY_CNT_8 BIT(7) 307#define MSK_DDC_DOUT_CNT_DDC_DATA_OUT_CNT 0x1f 308 309/* DDC I2C Delay Count, default value: 0x14 */ 310#define REG_DDC_DELAY_CNT 0x00f6 311 312/* Test Control, default value: 0x80 */ 313#define REG_TEST_TXCTRL 0x00f7 314#define BIT_TEST_TXCTRL_RCLK_REF_SEL BIT(7) 315#define BIT_TEST_TXCTRL_PCLK_REF_SEL BIT(6) 316#define MSK_TEST_TXCTRL_BYPASS_PLL_CLK 0x3c 317#define BIT_TEST_TXCTRL_HDMI_MODE BIT(1) 318#define BIT_TEST_TXCTRL_TST_PLLCK BIT(0) 319 320/* CBUS Address, default value: 0x00 */ 321#define REG_PAGE_CBUS_ADDR 0x00f8 322 323/* I2C Device Address re-assignment */ 324#define REG_PAGE1_ADDR 0x00fc 325#define REG_PAGE2_ADDR 0x00fd 326#define REG_PAGE3_ADDR 0x00fe 327#define REG_HW_TPI_ADDR 0x00ff 328 329/* USBT CTRL0, default value: 0x00 */ 330#define REG_UTSRST 0x0100 331#define BIT_UTSRST_FC_SRST BIT(5) 332#define BIT_UTSRST_KEEPER_SRST BIT(4) 333#define BIT_UTSRST_HTX_SRST BIT(3) 334#define BIT_UTSRST_TRX_SRST BIT(2) 335#define BIT_UTSRST_TTX_SRST BIT(1) 336#define BIT_UTSRST_HRX_SRST BIT(0) 337 338/* HSIC RX Control3, default value: 0x07 */ 339#define REG_HRXCTRL3 0x0104 340#define MSK_HRXCTRL3_HRX_AFFCTRL 0xf0 341#define BIT_HRXCTRL3_HRX_OUT_EN BIT(2) 342#define BIT_HRXCTRL3_STATUS_EN BIT(1) 343#define BIT_HRXCTRL3_HRX_STAY_RESET BIT(0) 344 345/* HSIC RX INT Registers */ 346#define REG_HRXINTL 0x0111 347#define REG_HRXINTH 0x0112 348 349/* TDM TX NUMBITS, default value: 0x0c */ 350#define REG_TTXNUMB 0x0116 351#define MSK_TTXNUMB_TTX_AFFCTRL_3_0 0xf0 352#define BIT_TTXNUMB_TTX_COM1_AT_SYNC_WAIT BIT(3) 353#define MSK_TTXNUMB_TTX_NUMBPS 0x07 354 355/* TDM TX NUMSPISYM, default value: 0x04 */ 356#define REG_TTXSPINUMS 0x0117 357 358/* TDM TX NUMHSICSYM, default value: 0x14 */ 359#define REG_TTXHSICNUMS 0x0118 360 361/* TDM TX NUMTOTSYM, default value: 0x18 */ 362#define REG_TTXTOTNUMS 0x0119 363 364/* TDM TX INT Low, default value: 0x00 */ 365#define REG_TTXINTL 0x0136 366#define BIT_TTXINTL_TTX_INTR7 BIT(7) 367#define BIT_TTXINTL_TTX_INTR6 BIT(6) 368#define BIT_TTXINTL_TTX_INTR5 BIT(5) 369#define BIT_TTXINTL_TTX_INTR4 BIT(4) 370#define BIT_TTXINTL_TTX_INTR3 BIT(3) 371#define BIT_TTXINTL_TTX_INTR2 BIT(2) 372#define BIT_TTXINTL_TTX_INTR1 BIT(1) 373#define BIT_TTXINTL_TTX_INTR0 BIT(0) 374 375/* TDM TX INT High, default value: 0x00 */ 376#define REG_TTXINTH 0x0137 377#define BIT_TTXINTH_TTX_INTR15 BIT(7) 378#define BIT_TTXINTH_TTX_INTR14 BIT(6) 379#define BIT_TTXINTH_TTX_INTR13 BIT(5) 380#define BIT_TTXINTH_TTX_INTR12 BIT(4) 381#define BIT_TTXINTH_TTX_INTR11 BIT(3) 382#define BIT_TTXINTH_TTX_INTR10 BIT(2) 383#define BIT_TTXINTH_TTX_INTR9 BIT(1) 384#define BIT_TTXINTH_TTX_INTR8 BIT(0) 385 386/* TDM RX Control, default value: 0x1c */ 387#define REG_TRXCTRL 0x013b 388#define BIT_TRXCTRL_TRX_CLR_WVALLOW BIT(4) 389#define BIT_TRXCTRL_TRX_FROM_SE_COC BIT(3) 390#define MSK_TRXCTRL_TRX_NUMBPS_2_0 0x07 391 392/* TDM RX NUMSPISYM, default value: 0x04 */ 393#define REG_TRXSPINUMS 0x013c 394 395/* TDM RX NUMHSICSYM, default value: 0x14 */ 396#define REG_TRXHSICNUMS 0x013d 397 398/* TDM RX NUMTOTSYM, default value: 0x18 */ 399#define REG_TRXTOTNUMS 0x013e 400 401/* TDM RX Status 2nd, default value: 0x00 */ 402#define REG_TRXSTA2 0x015c 403#define MSK_TDM_SYNCHRONIZED 0xc0 404#define VAL_TDM_SYNCHRONIZED 0x80 405 406/* TDM RX INT Low, default value: 0x00 */ 407#define REG_TRXINTL 0x0163 408 409/* TDM RX INT High, default value: 0x00 */ 410#define REG_TRXINTH 0x0164 411#define BIT_TDM_INTR_SYNC_DATA BIT(0) 412#define BIT_TDM_INTR_SYNC_WAIT BIT(1) 413 414/* TDM RX INTMASK High, default value: 0x00 */ 415#define REG_TRXINTMH 0x0166 416 417/* HSIC TX CRTL, default value: 0x00 */ 418#define REG_HTXCTRL 0x0169 419#define BIT_HTXCTRL_HTX_ALLSBE_SOP BIT(4) 420#define BIT_HTXCTRL_HTX_RGDINV_USB BIT(3) 421#define BIT_HTXCTRL_HTX_RSPTDM_BUSY BIT(2) 422#define BIT_HTXCTRL_HTX_DRVCONN1 BIT(1) 423#define BIT_HTXCTRL_HTX_DRVRST1 BIT(0) 424 425/* HSIC TX INT Low, default value: 0x00 */ 426#define REG_HTXINTL 0x017d 427 428/* HSIC TX INT High, default value: 0x00 */ 429#define REG_HTXINTH 0x017e 430 431/* HSIC Keeper, default value: 0x00 */ 432#define REG_KEEPER 0x0181 433#define MSK_KEEPER_MODE 0x03 434#define VAL_KEEPER_MODE_HOST 0 435#define VAL_KEEPER_MODE_DEVICE 2 436 437/* HSIC Flow Control General, default value: 0x02 */ 438#define REG_FCGC 0x0183 439#define BIT_FCGC_HSIC_HOSTMODE BIT(1) 440#define BIT_FCGC_HSIC_ENABLE BIT(0) 441 442/* HSIC Flow Control CTR13, default value: 0xfc */ 443#define REG_FCCTR13 0x0191 444 445/* HSIC Flow Control CTR14, default value: 0xff */ 446#define REG_FCCTR14 0x0192 447 448/* HSIC Flow Control CTR15, default value: 0xff */ 449#define REG_FCCTR15 0x0193 450 451/* HSIC Flow Control CTR50, default value: 0x03 */ 452#define REG_FCCTR50 0x01b6 453 454/* HSIC Flow Control INTR0, default value: 0x00 */ 455#define REG_FCINTR0 0x01ec 456#define REG_FCINTR1 0x01ed 457#define REG_FCINTR2 0x01ee 458#define REG_FCINTR3 0x01ef 459#define REG_FCINTR4 0x01f0 460#define REG_FCINTR5 0x01f1 461#define REG_FCINTR6 0x01f2 462#define REG_FCINTR7 0x01f3 463 464/* TDM Low Latency, default value: 0x20 */ 465#define REG_TDMLLCTL 0x01fc 466#define MSK_TDMLLCTL_TRX_LL_SEL_MANUAL 0xc0 467#define MSK_TDMLLCTL_TRX_LL_SEL_MODE 0x30 468#define MSK_TDMLLCTL_TTX_LL_SEL_MANUAL 0x0c 469#define BIT_TDMLLCTL_TTX_LL_TIE_LOW BIT(1) 470#define BIT_TDMLLCTL_TTX_LL_SEL_MODE BIT(0) 471 472/* TMDS 0 Clock Control, default value: 0x10 */ 473#define REG_TMDS0_CCTRL1 0x0210 474#define MSK_TMDS0_CCTRL1_TEST_SEL 0xc0 475#define MSK_TMDS0_CCTRL1_CLK1X_CTL 0x30 476 477/* TMDS Clock Enable, default value: 0x00 */ 478#define REG_TMDS_CLK_EN 0x0211 479#define BIT_TMDS_CLK_EN_CLK_EN BIT(0) 480 481/* TMDS Channel Enable, default value: 0x00 */ 482#define REG_TMDS_CH_EN 0x0212 483#define BIT_TMDS_CH_EN_CH0_EN BIT(4) 484#define BIT_TMDS_CH_EN_CH12_EN BIT(0) 485 486/* BGR_BIAS, default value: 0x07 */ 487#define REG_BGR_BIAS 0x0215 488#define BIT_BGR_BIAS_BGR_EN BIT(7) 489#define MSK_BGR_BIAS_BIAS_BGR_D 0x0f 490 491/* TMDS 0 Digital I2C BW, default value: 0x0a */ 492#define REG_ALICE0_BW_I2C 0x0231 493 494/* TMDS 0 Digital Zone Control, default value: 0xe0 */ 495#define REG_ALICE0_ZONE_CTRL 0x024c 496#define BIT_ALICE0_ZONE_CTRL_ICRST_N BIT(7) 497#define BIT_ALICE0_ZONE_CTRL_USE_INT_DIV20 BIT(6) 498#define MSK_ALICE0_ZONE_CTRL_SZONE_I2C 0x30 499#define MSK_ALICE0_ZONE_CTRL_ZONE_CTRL 0x0f 500 501/* TMDS 0 Digital PLL Mode Control, default value: 0x00 */ 502#define REG_ALICE0_MODE_CTRL 0x024d 503#define MSK_ALICE0_MODE_CTRL_PLL_MODE_I2C 0x0c 504#define MSK_ALICE0_MODE_CTRL_DIV20_CTRL 0x03 505 506/* MHL Tx Control 6th, default value: 0xa0 */ 507#define REG_MHLTX_CTL6 0x0285 508#define MSK_MHLTX_CTL6_EMI_SEL 0xe0 509#define MSK_MHLTX_CTL6_TX_CLK_SHAPE_9_8 0x03 510 511/* Packet Filter0, default value: 0x00 */ 512#define REG_PKT_FILTER_0 0x0290 513#define BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT BIT(7) 514#define BIT_PKT_FILTER_0_DROP_CEA_CP_PKT BIT(6) 515#define BIT_PKT_FILTER_0_DROP_MPEG_PKT BIT(5) 516#define BIT_PKT_FILTER_0_DROP_SPIF_PKT BIT(4) 517#define BIT_PKT_FILTER_0_DROP_AIF_PKT BIT(3) 518#define BIT_PKT_FILTER_0_DROP_AVI_PKT BIT(2) 519#define BIT_PKT_FILTER_0_DROP_CTS_PKT BIT(1) 520#define BIT_PKT_FILTER_0_DROP_GCP_PKT BIT(0) 521 522/* Packet Filter1, default value: 0x00 */ 523#define REG_PKT_FILTER_1 0x0291 524#define BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS BIT(7) 525#define BIT_PKT_FILTER_1_AVI_OVERRIDE_DIS BIT(6) 526#define BIT_PKT_FILTER_1_DROP_AUDIO_PKT BIT(3) 527#define BIT_PKT_FILTER_1_DROP_GEN2_PKT BIT(2) 528#define BIT_PKT_FILTER_1_DROP_GEN_PKT BIT(1) 529#define BIT_PKT_FILTER_1_DROP_VSIF_PKT BIT(0) 530 531/* TMDS Clock Status, default value: 0x10 */ 532#define REG_TMDS_CSTAT_P3 0x02a0 533#define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_CLR_MUTE BIT(7) 534#define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_SET_MUTE BIT(6) 535#define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_NEW_CP BIT(5) 536#define BIT_TMDS_CSTAT_P3_CLR_AVI BIT(3) 537#define BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS BIT(2) 538#define BIT_TMDS_CSTAT_P3_SCDT BIT(1) 539#define BIT_TMDS_CSTAT_P3_CKDT BIT(0) 540 541/* RX_HDMI Control, default value: 0x10 */ 542#define REG_RX_HDMI_CTRL0 0x02a1 543#define BIT_RX_HDMI_CTRL0_BYP_DVIFILT_SYNC BIT(5) 544#define BIT_RX_HDMI_CTRL0_HDMI_MODE_EN_ITSELF_CLR BIT(4) 545#define BIT_RX_HDMI_CTRL0_HDMI_MODE_SW_VALUE BIT(3) 546#define BIT_RX_HDMI_CTRL0_HDMI_MODE_OVERWRITE BIT(2) 547#define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE_EN BIT(1) 548#define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE BIT(0) 549 550/* RX_HDMI Control, default value: 0x38 */ 551#define REG_RX_HDMI_CTRL2 0x02a3 552#define MSK_RX_HDMI_CTRL2_IDLE_CNT 0xf0 553#define VAL_RX_HDMI_CTRL2_IDLE_CNT(n) ((n) << 4) 554#define BIT_RX_HDMI_CTRL2_USE_AV_MUTE BIT(3) 555#define BIT_RX_HDMI_CTRL2_VSI_MON_SEL_VSI BIT(0) 556 557/* RX_HDMI Control, default value: 0x0f */ 558#define REG_RX_HDMI_CTRL3 0x02a4 559#define MSK_RX_HDMI_CTRL3_PP_MODE_CLK_EN 0x0f 560 561/* rx_hdmi Clear Buffer, default value: 0x00 */ 562#define REG_RX_HDMI_CLR_BUFFER 0x02ac 563#define MSK_RX_HDMI_CLR_BUFFER_AIF4VSI_CMP 0xc0 564#define BIT_RX_HDMI_CLR_BUFFER_USE_AIF4VSI BIT(5) 565#define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_W_AVI BIT(4) 566#define BIT_RX_HDMI_CLR_BUFFER_VSI_IEEE_ID_CHK_EN BIT(3) 567#define BIT_RX_HDMI_CLR_BUFFER_SWAP_VSI_IEEE_ID BIT(2) 568#define BIT_RX_HDMI_CLR_BUFFER_AIF_CLR_EN BIT(1) 569#define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN BIT(0) 570 571/* RX_HDMI VSI Header1, default value: 0x00 */ 572#define REG_RX_HDMI_MON_PKT_HEADER1 0x02b8 573 574/* RX_HDMI VSI MHL Monitor, default value: 0x3c */ 575#define REG_RX_HDMI_VSIF_MHL_MON 0x02d7 576 577#define MSK_RX_HDMI_VSIF_MHL_MON_RX_HDMI_MHL_3D_FORMAT 0x3c 578#define MSK_RX_HDMI_VSIF_MHL_MON_RX_HDMI_MHL_VID_FORMAT 0x03 579 580/* Interrupt Source 9, default value: 0x00 */ 581#define REG_INTR9 0x02e0 582#define BIT_INTR9_EDID_ERROR BIT(6) 583#define BIT_INTR9_EDID_DONE BIT(5) 584#define BIT_INTR9_DEVCAP_DONE BIT(4) 585 586/* Interrupt 9 Mask, default value: 0x00 */ 587#define REG_INTR9_MASK 0x02e1 588 589/* TPI CBUS Start, default value: 0x00 */ 590#define REG_TPI_CBUS_START 0x02e2 591#define BIT_TPI_CBUS_START_RCP_REQ_START BIT(7) 592#define BIT_TPI_CBUS_START_RCPK_REPLY_START BIT(6) 593#define BIT_TPI_CBUS_START_RCPE_REPLY_START BIT(5) 594#define BIT_TPI_CBUS_START_PUT_LINK_MODE_START BIT(4) 595#define BIT_TPI_CBUS_START_PUT_DCAPCHG_START BIT(3) 596#define BIT_TPI_CBUS_START_PUT_DCAPRDY_START BIT(2) 597#define BIT_TPI_CBUS_START_GET_EDID_START_0 BIT(1) 598#define BIT_TPI_CBUS_START_GET_DEVCAP_START BIT(0) 599 600/* EDID Control, default value: 0x10 */ 601#define REG_EDID_CTRL 0x02e3 602#define BIT_EDID_CTRL_EDID_PRIME_VALID BIT(7) 603#define BIT_EDID_CTRL_XDEVCAP_EN BIT(6) 604#define BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP BIT(5) 605#define BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO BIT(4) 606#define BIT_EDID_CTRL_EDID_FIFO_ACCESS_ALWAYS_EN BIT(3) 607#define BIT_EDID_CTRL_EDID_FIFO_BLOCK_SEL BIT(2) 608#define BIT_EDID_CTRL_INVALID_BKSV BIT(1) 609#define BIT_EDID_CTRL_EDID_MODE_EN BIT(0) 610 611/* EDID FIFO Addr, default value: 0x00 */ 612#define REG_EDID_FIFO_ADDR 0x02e9 613 614/* EDID FIFO Write Data, default value: 0x00 */ 615#define REG_EDID_FIFO_WR_DATA 0x02ea 616 617/* EDID/DEVCAP FIFO Internal Addr, default value: 0x00 */ 618#define REG_EDID_FIFO_ADDR_MON 0x02eb 619 620/* EDID FIFO Read Data, default value: 0x00 */ 621#define REG_EDID_FIFO_RD_DATA 0x02ec 622 623/* EDID DDC Segment Pointer, default value: 0x00 */ 624#define REG_EDID_START_EXT 0x02ed 625 626/* TX IP BIST CNTL and Status, default value: 0x00 */ 627#define REG_TX_IP_BIST_CNTLSTA 0x02f2 628#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_QUARTER_CLK_SEL BIT(6) 629#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_DONE BIT(5) 630#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_ON BIT(4) 631#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_RUN BIT(3) 632#define BIT_TX_IP_BIST_CNTLSTA_TXCLK_HALF_SEL BIT(2) 633#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_EN BIT(1) 634#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_SEL BIT(0) 635 636/* TX IP BIST INST LOW, default value: 0x00 */ 637#define REG_TX_IP_BIST_INST_LOW 0x02f3 638#define REG_TX_IP_BIST_INST_HIGH 0x02f4 639 640/* TX IP BIST PATTERN LOW, default value: 0x00 */ 641#define REG_TX_IP_BIST_PAT_LOW 0x02f5 642#define REG_TX_IP_BIST_PAT_HIGH 0x02f6 643 644/* TX IP BIST CONFIGURE LOW, default value: 0x00 */ 645#define REG_TX_IP_BIST_CONF_LOW 0x02f7 646#define REG_TX_IP_BIST_CONF_HIGH 0x02f8 647 648/* E-MSC General Control, default value: 0x80 */ 649#define REG_GENCTL 0x0300 650#define BIT_GENCTL_SPEC_TRANS_DIS BIT(7) 651#define BIT_GENCTL_DIS_XMIT_ERR_STATE BIT(6) 652#define BIT_GENCTL_SPI_MISO_EDGE BIT(5) 653#define BIT_GENCTL_SPI_MOSI_EDGE BIT(4) 654#define BIT_GENCTL_CLR_EMSC_RFIFO BIT(3) 655#define BIT_GENCTL_CLR_EMSC_XFIFO BIT(2) 656#define BIT_GENCTL_START_TRAIN_SEQ BIT(1) 657#define BIT_GENCTL_EMSC_EN BIT(0) 658 659/* E-MSC Comma ErrorCNT, default value: 0x03 */ 660#define REG_COMMECNT 0x0305 661#define BIT_COMMECNT_I2C_TO_EMSC_EN BIT(7) 662#define MSK_COMMECNT_COMMA_CHAR_ERR_CNT 0x0f 663 664/* E-MSC RFIFO ByteCnt, default value: 0x00 */ 665#define REG_EMSCRFIFOBCNTL 0x031a 666#define REG_EMSCRFIFOBCNTH 0x031b 667 668/* SPI Burst Cnt Status, default value: 0x00 */ 669#define REG_SPIBURSTCNT 0x031e 670 671/* SPI Burst Status and SWRST, default value: 0x00 */ 672#define REG_SPIBURSTSTAT 0x0322 673#define BIT_SPIBURSTSTAT_SPI_HDCPRST BIT(7) 674#define BIT_SPIBURSTSTAT_SPI_CBUSRST BIT(6) 675#define BIT_SPIBURSTSTAT_SPI_SRST BIT(5) 676#define BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE BIT(0) 677 678/* E-MSC 1st Interrupt, default value: 0x00 */ 679#define REG_EMSCINTR 0x0323 680#define BIT_EMSCINTR_EMSC_XFIFO_EMPTY BIT(7) 681#define BIT_EMSCINTR_EMSC_XMIT_ACK_TOUT BIT(6) 682#define BIT_EMSCINTR_EMSC_RFIFO_READ_ERR BIT(5) 683#define BIT_EMSCINTR_EMSC_XFIFO_WRITE_ERR BIT(4) 684#define BIT_EMSCINTR_EMSC_COMMA_CHAR_ERR BIT(3) 685#define BIT_EMSCINTR_EMSC_XMIT_DONE BIT(2) 686#define BIT_EMSCINTR_EMSC_XMIT_GNT_TOUT BIT(1) 687#define BIT_EMSCINTR_SPI_DVLD BIT(0) 688 689/* E-MSC Interrupt Mask, default value: 0x00 */ 690#define REG_EMSCINTRMASK 0x0324 691 692/* I2C E-MSC XMIT FIFO Write Port, default value: 0x00 */ 693#define REG_EMSC_XMIT_WRITE_PORT 0x032a 694 695/* I2C E-MSC RCV FIFO Write Port, default value: 0x00 */ 696#define REG_EMSC_RCV_READ_PORT 0x032b 697 698/* E-MSC 2nd Interrupt, default value: 0x00 */ 699#define REG_EMSCINTR1 0x032c 700#define BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR BIT(0) 701 702/* E-MSC Interrupt Mask, default value: 0x00 */ 703#define REG_EMSCINTRMASK1 0x032d 704#define BIT_EMSCINTRMASK1_EMSC_INTRMASK1_0 BIT(0) 705 706/* MHL Top Ctl, default value: 0x00 */ 707#define REG_MHL_TOP_CTL 0x0330 708#define BIT_MHL_TOP_CTL_MHL3_DOC_SEL BIT(7) 709#define BIT_MHL_TOP_CTL_MHL_PP_SEL BIT(6) 710#define MSK_MHL_TOP_CTL_IF_TIMING_CTL 0x03 711 712/* MHL DataPath 1st Ctl, default value: 0xbc */ 713#define REG_MHL_DP_CTL0 0x0331 714#define BIT_MHL_DP_CTL0_DP_OE BIT(7) 715#define BIT_MHL_DP_CTL0_TX_OE_OVR BIT(6) 716#define MSK_MHL_DP_CTL0_TX_OE 0x3f 717 718/* MHL DataPath 2nd Ctl, default value: 0xbb */ 719#define REG_MHL_DP_CTL1 0x0332 720#define MSK_MHL_DP_CTL1_CK_SWING_CTL 0xf0 721#define MSK_MHL_DP_CTL1_DT_SWING_CTL 0x0f 722 723/* MHL DataPath 3rd Ctl, default value: 0x2f */ 724#define REG_MHL_DP_CTL2 0x0333 725#define BIT_MHL_DP_CTL2_CLK_BYPASS_EN BIT(7) 726#define MSK_MHL_DP_CTL2_DAMP_TERM_SEL 0x30 727#define MSK_MHL_DP_CTL2_CK_TERM_SEL 0x0c 728#define MSK_MHL_DP_CTL2_DT_TERM_SEL 0x03 729 730/* MHL DataPath 4th Ctl, default value: 0x48 */ 731#define REG_MHL_DP_CTL3 0x0334 732#define MSK_MHL_DP_CTL3_DT_DRV_VNBC_CTL 0xf0 733#define MSK_MHL_DP_CTL3_DT_DRV_VNB_CTL 0x0f 734 735/* MHL DataPath 5th Ctl, default value: 0x48 */ 736#define REG_MHL_DP_CTL4 0x0335 737#define MSK_MHL_DP_CTL4_CK_DRV_VNBC_CTL 0xf0 738#define MSK_MHL_DP_CTL4_CK_DRV_VNB_CTL 0x0f 739 740/* MHL DataPath 6th Ctl, default value: 0x3f */ 741#define REG_MHL_DP_CTL5 0x0336 742#define BIT_MHL_DP_CTL5_RSEN_EN_OVR BIT(7) 743#define BIT_MHL_DP_CTL5_RSEN_EN BIT(6) 744#define MSK_MHL_DP_CTL5_DAMP_TERM_VGS_CTL 0x30 745#define MSK_MHL_DP_CTL5_CK_TERM_VGS_CTL 0x0c 746#define MSK_MHL_DP_CTL5_DT_TERM_VGS_CTL 0x03 747 748/* MHL PLL 1st Ctl, default value: 0x05 */ 749#define REG_MHL_PLL_CTL0 0x0337 750#define BIT_MHL_PLL_CTL0_AUD_CLK_EN BIT(7) 751 752#define MSK_MHL_PLL_CTL0_AUD_CLK_RATIO 0x70 753#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_10 0x70 754#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_6 0x60 755#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_4 0x50 756#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_2 0x40 757#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_5 0x30 758#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_3 0x20 759#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_2_PRIME 0x10 760#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_1 0x00 761 762#define MSK_MHL_PLL_CTL0_HDMI_CLK_RATIO 0x0c 763#define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_4X 0x0c 764#define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_2X 0x08 765#define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 0x04 766#define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_HALF_X 0x00 767 768#define BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL BIT(1) 769#define BIT_MHL_PLL_CTL0_ZONE_MASK_OE BIT(0) 770 771/* MHL PLL 3rd Ctl, default value: 0x80 */ 772#define REG_MHL_PLL_CTL2 0x0339 773#define BIT_MHL_PLL_CTL2_CLKDETECT_EN BIT(7) 774#define BIT_MHL_PLL_CTL2_MEAS_FVCO BIT(3) 775#define BIT_MHL_PLL_CTL2_PLL_FAST_LOCK BIT(2) 776#define MSK_MHL_PLL_CTL2_PLL_LF_SEL 0x03 777 778/* MHL CBUS 1st Ctl, default value: 0x12 */ 779#define REG_MHL_CBUS_CTL0 0x0340 780#define BIT_MHL_CBUS_CTL0_CBUS_RGND_TEST_MODE BIT(7) 781 782#define MSK_MHL_CBUS_CTL0_CBUS_RGND_VTH_CTL 0x30 783#define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734 0x00 784#define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_747 0x10 785#define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_740 0x20 786#define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_754 0x30 787 788#define MSK_MHL_CBUS_CTL0_CBUS_RES_TEST_SEL 0x0c 789 790#define MSK_MHL_CBUS_CTL0_CBUS_DRV_SEL 0x03 791#define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_WEAKEST 0x00 792#define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_WEAK 0x01 793#define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG 0x02 794#define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONGEST 0x03 795 796/* MHL CBUS 2nd Ctl, default value: 0x03 */ 797#define REG_MHL_CBUS_CTL1 0x0341 798#define MSK_MHL_CBUS_CTL1_CBUS_RGND_RES_CTL 0x07 799#define VAL_MHL_CBUS_CTL1_0888_OHM 0x00 800#define VAL_MHL_CBUS_CTL1_1115_OHM 0x04 801#define VAL_MHL_CBUS_CTL1_1378_OHM 0x07 802 803/* MHL CoC 1st Ctl, default value: 0xc3 */ 804#define REG_MHL_COC_CTL0 0x0342 805#define BIT_MHL_COC_CTL0_COC_BIAS_EN BIT(7) 806#define MSK_MHL_COC_CTL0_COC_BIAS_CTL 0x70 807#define MSK_MHL_COC_CTL0_COC_TERM_CTL 0x07 808 809/* MHL CoC 2nd Ctl, default value: 0x87 */ 810#define REG_MHL_COC_CTL1 0x0343 811#define BIT_MHL_COC_CTL1_COC_EN BIT(7) 812#define MSK_MHL_COC_CTL1_COC_DRV_CTL 0x3f 813 814/* MHL CoC 4th Ctl, default value: 0x00 */ 815#define REG_MHL_COC_CTL3 0x0345 816#define BIT_MHL_COC_CTL3_COC_AECHO_EN BIT(0) 817 818/* MHL CoC 5th Ctl, default value: 0x28 */ 819#define REG_MHL_COC_CTL4 0x0346 820#define MSK_MHL_COC_CTL4_COC_IF_CTL 0xf0 821#define MSK_MHL_COC_CTL4_COC_SLEW_CTL 0x0f 822 823/* MHL CoC 6th Ctl, default value: 0x0d */ 824#define REG_MHL_COC_CTL5 0x0347 825 826/* MHL DoC 1st Ctl, default value: 0x18 */ 827#define REG_MHL_DOC_CTL0 0x0349 828#define BIT_MHL_DOC_CTL0_DOC_RXDATA_EN BIT(7) 829#define MSK_MHL_DOC_CTL0_DOC_DM_TERM 0x38 830#define MSK_MHL_DOC_CTL0_DOC_OPMODE 0x06 831#define BIT_MHL_DOC_CTL0_DOC_RXBIAS_EN BIT(0) 832 833/* MHL DataPath 7th Ctl, default value: 0x2a */ 834#define REG_MHL_DP_CTL6 0x0350 835#define BIT_MHL_DP_CTL6_DP_TAP2_SGN BIT(5) 836#define BIT_MHL_DP_CTL6_DP_TAP2_EN BIT(4) 837#define BIT_MHL_DP_CTL6_DP_TAP1_SGN BIT(3) 838#define BIT_MHL_DP_CTL6_DP_TAP1_EN BIT(2) 839#define BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN BIT(1) 840#define BIT_MHL_DP_CTL6_DP_PRE_POST_SEL BIT(0) 841 842/* MHL DataPath 8th Ctl, default value: 0x06 */ 843#define REG_MHL_DP_CTL7 0x0351 844#define MSK_MHL_DP_CTL7_DT_DRV_VBIAS_CASCTL 0xf0 845#define MSK_MHL_DP_CTL7_DT_DRV_IREF_CTL 0x0f 846 847#define REG_MHL_DP_CTL8 0x0352 848 849/* Tx Zone Ctl1, default value: 0x00 */ 850#define REG_TX_ZONE_CTL1 0x0361 851#define VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE 0x08 852 853/* MHL3 Tx Zone Ctl, default value: 0x00 */ 854#define REG_MHL3_TX_ZONE_CTL 0x0364 855#define BIT_MHL3_TX_ZONE_CTL_MHL2_INTPLT_ZONE_MANU_EN BIT(7) 856#define MSK_MHL3_TX_ZONE_CTL_MHL3_TX_ZONE 0x03 857 858#define MSK_TX_ZONE_CTL3_TX_ZONE 0x03 859#define VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS 0x00 860#define VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS 0x01 861#define VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS 0x02 862 863/* HDCP Polling Control and Status, default value: 0x70 */ 864#define REG_HDCP2X_POLL_CS 0x0391 865 866#define BIT_HDCP2X_POLL_CS_HDCP2X_MSG_SZ_CLR_OPTION BIT(6) 867#define BIT_HDCP2X_POLL_CS_HDCP2X_RPT_READY_CLR_OPTION BIT(5) 868#define BIT_HDCP2X_POLL_CS_HDCP2X_REAUTH_REQ_CLR_OPTION BIT(4) 869#define MSK_HDCP2X_POLL_CS_ 0x0c 870#define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_GNT BIT(1) 871#define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_EN BIT(0) 872 873/* HDCP Interrupt 0, default value: 0x00 */ 874#define REG_HDCP2X_INTR0 0x0398 875 876/* HDCP Interrupt 0 Mask, default value: 0x00 */ 877#define REG_HDCP2X_INTR0_MASK 0x0399 878 879/* HDCP General Control 0, default value: 0x02 */ 880#define REG_HDCP2X_CTRL_0 0x03a0 881#define BIT_HDCP2X_CTRL_0_HDCP2X_ENCRYPT_EN BIT(7) 882#define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_SEL BIT(6) 883#define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_OVR BIT(5) 884#define BIT_HDCP2X_CTRL_0_HDCP2X_PRECOMPUTE BIT(4) 885#define BIT_HDCP2X_CTRL_0_HDCP2X_HDMIMODE BIT(3) 886#define BIT_HDCP2X_CTRL_0_HDCP2X_REPEATER BIT(2) 887#define BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX BIT(1) 888#define BIT_HDCP2X_CTRL_0_HDCP2X_EN BIT(0) 889 890/* HDCP General Control 1, default value: 0x08 */ 891#define REG_HDCP2X_CTRL_1 0x03a1 892#define MSK_HDCP2X_CTRL_1_HDCP2X_REAUTH_MSK_3_0 0xf0 893#define BIT_HDCP2X_CTRL_1_HDCP2X_HPD_SW BIT(3) 894#define BIT_HDCP2X_CTRL_1_HDCP2X_HPD_OVR BIT(2) 895#define BIT_HDCP2X_CTRL_1_HDCP2X_CTL3MSK BIT(1) 896#define BIT_HDCP2X_CTRL_1_HDCP2X_REAUTH_SW BIT(0) 897 898/* HDCP Misc Control, default value: 0x00 */ 899#define REG_HDCP2X_MISC_CTRL 0x03a5 900#define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_XFER_START BIT(4) 901#define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR_START BIT(3) 902#define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR BIT(2) 903#define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD_START BIT(1) 904#define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD BIT(0) 905 906/* HDCP RPT SMNG K, default value: 0x00 */ 907#define REG_HDCP2X_RPT_SMNG_K 0x03a6 908 909/* HDCP RPT SMNG In, default value: 0x00 */ 910#define REG_HDCP2X_RPT_SMNG_IN 0x03a7 911 912/* HDCP Auth Status, default value: 0x00 */ 913#define REG_HDCP2X_AUTH_STAT 0x03aa 914 915/* HDCP RPT RCVID Out, default value: 0x00 */ 916#define REG_HDCP2X_RPT_RCVID_OUT 0x03ac 917 918/* HDCP TP1, default value: 0x62 */ 919#define REG_HDCP2X_TP1 0x03b4 920 921/* HDCP GP Out 0, default value: 0x00 */ 922#define REG_HDCP2X_GP_OUT0 0x03c7 923 924/* HDCP Repeater RCVR ID 0, default value: 0x00 */ 925#define REG_HDCP2X_RPT_RCVR_ID0 0x03d1 926 927/* HDCP DDCM Status, default value: 0x00 */ 928#define REG_HDCP2X_DDCM_STS 0x03d8 929#define MSK_HDCP2X_DDCM_STS_HDCP2X_DDCM_ERR_STS_3_0 0xf0 930#define MSK_HDCP2X_DDCM_STS_HDCP2X_DDCM_CTL_CS_3_0 0x0f 931 932/* HDMI2MHL3 Control, default value: 0x0a */ 933#define REG_M3_CTRL 0x03e0 934#define BIT_M3_CTRL_H2M_SWRST BIT(4) 935#define BIT_M3_CTRL_SW_MHL3_SEL BIT(3) 936#define BIT_M3_CTRL_M3AV_EN BIT(2) 937#define BIT_M3_CTRL_ENC_TMDS BIT(1) 938#define BIT_M3_CTRL_MHL3_MASTER_EN BIT(0) 939 940#define VAL_M3_CTRL_MHL1_2_VALUE (BIT_M3_CTRL_SW_MHL3_SEL \ 941 | BIT_M3_CTRL_ENC_TMDS) 942#define VAL_M3_CTRL_MHL3_VALUE (BIT_M3_CTRL_SW_MHL3_SEL \ 943 | BIT_M3_CTRL_M3AV_EN \ 944 | BIT_M3_CTRL_ENC_TMDS \ 945 | BIT_M3_CTRL_MHL3_MASTER_EN) 946 947/* HDMI2MHL3 Port0 Control, default value: 0x04 */ 948#define REG_M3_P0CTRL 0x03e1 949#define BIT_M3_P0CTRL_MHL3_P0_HDCP_ENC_EN BIT(4) 950#define BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN BIT(3) 951#define BIT_M3_P0CTRL_MHL3_P0_HDCP_EN BIT(2) 952#define BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED BIT(1) 953#define BIT_M3_P0CTRL_MHL3_P0_PORT_EN BIT(0) 954 955#define REG_M3_POSTM 0x03e2 956#define MSK_M3_POSTM_RRP_DECODE 0xf8 957#define MSK_M3_POSTM_MHL3_P0_STM_ID 0x07 958 959/* HDMI2MHL3 Scramble Control, default value: 0x41 */ 960#define REG_M3_SCTRL 0x03e6 961#define MSK_M3_SCTRL_MHL3_SR_LENGTH 0xf0 962#define BIT_M3_SCTRL_MHL3_SCRAMBLER_EN BIT(0) 963 964/* HSIC Div Ctl, default value: 0x05 */ 965#define REG_DIV_CTL_MAIN 0x03f2 966#define MSK_DIV_CTL_MAIN_PRE_DIV_CTL_MAIN 0x1c 967#define MSK_DIV_CTL_MAIN_FB_DIV_CTL_MAIN 0x03 968 969/* MHL Capability 1st Byte, default value: 0x00 */ 970#define REG_MHL_DEVCAP_0 0x0400 971 972/* MHL Interrupt 1st Byte, default value: 0x00 */ 973#define REG_MHL_INT_0 0x0420 974 975/* Device Status 1st byte, default value: 0x00 */ 976#define REG_MHL_STAT_0 0x0430 977 978/* CBUS Scratch Pad 1st Byte, default value: 0x00 */ 979#define REG_MHL_SCRPAD_0 0x0440 980 981/* MHL Extended Capability 1st Byte, default value: 0x00 */ 982#define REG_MHL_EXTDEVCAP_0 0x0480 983 984/* Device Extended Status 1st byte, default value: 0x00 */ 985#define REG_MHL_EXTSTAT_0 0x0490 986 987/* TPI DTD Byte2, default value: 0x00 */ 988#define REG_TPI_DTD_B2 0x0602 989 990#define VAL_TPI_QUAN_RANGE_LIMITED 0x01 991#define VAL_TPI_QUAN_RANGE_FULL 0x02 992#define VAL_TPI_FORMAT_RGB 0x00 993#define VAL_TPI_FORMAT_YCBCR444 0x01 994#define VAL_TPI_FORMAT_YCBCR422 0x02 995#define VAL_TPI_FORMAT_INTERNAL_RGB 0x03 996#define VAL_TPI_FORMAT(_fmt, _qr) \ 997 (VAL_TPI_FORMAT_##_fmt | (VAL_TPI_QUAN_RANGE_##_qr << 2)) 998 999/* Input Format, default value: 0x00 */ 1000#define REG_TPI_INPUT 0x0609 1001#define BIT_TPI_INPUT_EXTENDEDBITMODE BIT(7) 1002#define BIT_TPI_INPUT_ENDITHER BIT(6) 1003#define MSK_TPI_INPUT_INPUT_QUAN_RANGE 0x0c 1004#define MSK_TPI_INPUT_INPUT_FORMAT 0x03 1005 1006/* Output Format, default value: 0x00 */ 1007#define REG_TPI_OUTPUT 0x060a 1008#define BIT_TPI_OUTPUT_CSCMODE709 BIT(4) 1009#define MSK_TPI_OUTPUT_OUTPUT_QUAN_RANGE 0x0c 1010#define MSK_TPI_OUTPUT_OUTPUT_FORMAT 0x03 1011 1012/* TPI AVI Check Sum, default value: 0x00 */ 1013#define REG_TPI_AVI_CHSUM 0x060c 1014 1015/* TPI System Control, default value: 0x00 */ 1016#define REG_TPI_SC 0x061a 1017#define BIT_TPI_SC_TPI_UPDATE_FLG BIT(7) 1018#define BIT_TPI_SC_TPI_REAUTH_CTL BIT(6) 1019#define BIT_TPI_SC_TPI_OUTPUT_MODE_1 BIT(5) 1020#define BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN BIT(4) 1021#define BIT_TPI_SC_TPI_AV_MUTE BIT(3) 1022#define BIT_TPI_SC_DDC_GPU_REQUEST BIT(2) 1023#define BIT_TPI_SC_DDC_TPI_SW BIT(1) 1024#define BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI BIT(0) 1025 1026/* TPI COPP Query Data, default value: 0x00 */ 1027#define REG_TPI_COPP_DATA1 0x0629 1028#define BIT_TPI_COPP_DATA1_COPP_GPROT BIT(7) 1029#define BIT_TPI_COPP_DATA1_COPP_LPROT BIT(6) 1030#define MSK_TPI_COPP_DATA1_COPP_LINK_STATUS 0x30 1031#define VAL_TPI_COPP_LINK_STATUS_NORMAL 0x00 1032#define VAL_TPI_COPP_LINK_STATUS_LINK_LOST 0x10 1033#define VAL_TPI_COPP_LINK_STATUS_RENEGOTIATION_REQ 0x20 1034#define VAL_TPI_COPP_LINK_STATUS_LINK_SUSPENDED 0x30 1035#define BIT_TPI_COPP_DATA1_COPP_HDCP_REP BIT(3) 1036#define BIT_TPI_COPP_DATA1_COPP_CONNTYPE_0 BIT(2) 1037#define BIT_TPI_COPP_DATA1_COPP_PROTYPE BIT(1) 1038#define BIT_TPI_COPP_DATA1_COPP_CONNTYPE_1 BIT(0) 1039 1040/* TPI COPP Control Data, default value: 0x00 */ 1041#define REG_TPI_COPP_DATA2 0x062a 1042#define BIT_TPI_COPP_DATA2_INTR_ENCRYPTION BIT(5) 1043#define BIT_TPI_COPP_DATA2_KSV_FORWARD BIT(4) 1044#define BIT_TPI_COPP_DATA2_INTERM_RI_CHECK_EN BIT(3) 1045#define BIT_TPI_COPP_DATA2_DOUBLE_RI_CHECK BIT(2) 1046#define BIT_TPI_COPP_DATA2_DDC_SHORT_RI_RD BIT(1) 1047#define BIT_TPI_COPP_DATA2_COPP_PROTLEVEL BIT(0) 1048 1049/* TPI Interrupt Enable, default value: 0x00 */ 1050#define REG_TPI_INTR_EN 0x063c 1051 1052/* TPI Interrupt Status Low Byte, default value: 0x00 */ 1053#define REG_TPI_INTR_ST0 0x063d 1054#define BIT_TPI_INTR_ST0_TPI_AUTH_CHNGE_STAT BIT(7) 1055#define BIT_TPI_INTR_ST0_TPI_V_RDY_STAT BIT(6) 1056#define BIT_TPI_INTR_ST0_TPI_COPP_CHNGE_STAT BIT(5) 1057#define BIT_TPI_INTR_ST0_KSV_FIFO_FIRST_STAT BIT(3) 1058#define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_DONE_STAT BIT(2) 1059#define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_ERR_STAT BIT(1) 1060#define BIT_TPI_INTR_ST0_READ_BKSV_ERR_STAT BIT(0) 1061 1062/* TPI DS BCAPS Status, default value: 0x00 */ 1063#define REG_TPI_DS_BCAPS 0x0644 1064 1065/* TPI BStatus1, default value: 0x00 */ 1066#define REG_TPI_BSTATUS1 0x0645 1067#define BIT_TPI_BSTATUS1_DS_DEV_EXCEED BIT(7) 1068#define MSK_TPI_BSTATUS1_DS_DEV_CNT 0x7f 1069 1070/* TPI BStatus2, default value: 0x10 */ 1071#define REG_TPI_BSTATUS2 0x0646 1072#define MSK_TPI_BSTATUS2_DS_BSTATUS 0xe0 1073#define BIT_TPI_BSTATUS2_DS_HDMI_MODE BIT(4) 1074#define BIT_TPI_BSTATUS2_DS_CASC_EXCEED BIT(3) 1075#define MSK_TPI_BSTATUS2_DS_DEPTH 0x07 1076 1077/* TPI HW Optimization Control #3, default value: 0x00 */ 1078#define REG_TPI_HW_OPT3 0x06bb 1079#define BIT_TPI_HW_OPT3_DDC_DEBUG BIT(7) 1080#define BIT_TPI_HW_OPT3_RI_CHECK_SKIP BIT(3) 1081#define BIT_TPI_HW_OPT3_TPI_DDC_BURST_MODE BIT(2) 1082#define MSK_TPI_HW_OPT3_TPI_DDC_REQ_LEVEL 0x03 1083 1084/* TPI Info Frame Select, default value: 0x00 */ 1085#define REG_TPI_INFO_FSEL 0x06bf 1086#define BIT_TPI_INFO_FSEL_EN BIT(7) 1087#define BIT_TPI_INFO_FSEL_RPT BIT(6) 1088#define BIT_TPI_INFO_FSEL_READ_FLAG BIT(5) 1089#define MSK_TPI_INFO_FSEL_PKT 0x07 1090#define VAL_TPI_INFO_FSEL_AVI 0x00 1091#define VAL_TPI_INFO_FSEL_SPD 0x01 1092#define VAL_TPI_INFO_FSEL_AUD 0x02 1093#define VAL_TPI_INFO_FSEL_MPG 0x03 1094#define VAL_TPI_INFO_FSEL_GEN 0x04 1095#define VAL_TPI_INFO_FSEL_GEN2 0x05 1096#define VAL_TPI_INFO_FSEL_VSI 0x06 1097 1098/* TPI Info Byte #0, default value: 0x00 */ 1099#define REG_TPI_INFO_B0 0x06c0 1100 1101/* CoC Status, default value: 0x00 */ 1102#define REG_COC_STAT_0 0x0700 1103#define BIT_COC_STAT_0_PLL_LOCKED BIT(7) 1104#define MSK_COC_STAT_0_FSM_STATE 0x0f 1105 1106#define REG_COC_STAT_1 0x0701 1107#define REG_COC_STAT_2 0x0702 1108#define REG_COC_STAT_3 0x0703 1109#define REG_COC_STAT_4 0x0704 1110#define REG_COC_STAT_5 0x0705 1111 1112/* CoC 1st Ctl, default value: 0x40 */ 1113#define REG_COC_CTL0 0x0710 1114 1115/* CoC 2nd Ctl, default value: 0x0a */ 1116#define REG_COC_CTL1 0x0711 1117#define MSK_COC_CTL1_COC_CTRL1_7_6 0xc0 1118#define MSK_COC_CTL1_COC_CTRL1_5_0 0x3f 1119 1120/* CoC 3rd Ctl, default value: 0x14 */ 1121#define REG_COC_CTL2 0x0712 1122#define MSK_COC_CTL2_COC_CTRL2_7_6 0xc0 1123#define MSK_COC_CTL2_COC_CTRL2_5_0 0x3f 1124 1125/* CoC 4th Ctl, default value: 0x40 */ 1126#define REG_COC_CTL3 0x0713 1127#define BIT_COC_CTL3_COC_CTRL3_7 BIT(7) 1128#define MSK_COC_CTL3_COC_CTRL3_6_0 0x7f 1129 1130/* CoC 7th Ctl, default value: 0x00 */ 1131#define REG_COC_CTL6 0x0716 1132#define BIT_COC_CTL6_COC_CTRL6_7 BIT(7) 1133#define BIT_COC_CTL6_COC_CTRL6_6 BIT(6) 1134#define MSK_COC_CTL6_COC_CTRL6_5_0 0x3f 1135 1136/* CoC 8th Ctl, default value: 0x06 */ 1137#define REG_COC_CTL7 0x0717 1138#define BIT_COC_CTL7_COC_CTRL7_7 BIT(7) 1139#define BIT_COC_CTL7_COC_CTRL7_6 BIT(6) 1140#define BIT_COC_CTL7_COC_CTRL7_5 BIT(5) 1141#define MSK_COC_CTL7_COC_CTRL7_4_3 0x18 1142#define MSK_COC_CTL7_COC_CTRL7_2_0 0x07 1143 1144/* CoC 10th Ctl, default value: 0x00 */ 1145#define REG_COC_CTL9 0x0719 1146 1147/* CoC 11th Ctl, default value: 0x00 */ 1148#define REG_COC_CTLA 0x071a 1149 1150/* CoC 12th Ctl, default value: 0x00 */ 1151#define REG_COC_CTLB 0x071b 1152 1153/* CoC 13th Ctl, default value: 0x0f */ 1154#define REG_COC_CTLC 0x071c 1155 1156/* CoC 14th Ctl, default value: 0x0a */ 1157#define REG_COC_CTLD 0x071d 1158#define BIT_COC_CTLD_COC_CTRLD_7 BIT(7) 1159#define MSK_COC_CTLD_COC_CTRLD_6_0 0x7f 1160 1161/* CoC 15th Ctl, default value: 0x0a */ 1162#define REG_COC_CTLE 0x071e 1163#define BIT_COC_CTLE_COC_CTRLE_7 BIT(7) 1164#define MSK_COC_CTLE_COC_CTRLE_6_0 0x7f 1165 1166/* CoC 16th Ctl, default value: 0x00 */ 1167#define REG_COC_CTLF 0x071f 1168#define MSK_COC_CTLF_COC_CTRLF_7_3 0xf8 1169#define MSK_COC_CTLF_COC_CTRLF_2_0 0x07 1170 1171/* CoC 18th Ctl, default value: 0x32 */ 1172#define REG_COC_CTL11 0x0721 1173#define MSK_COC_CTL11_COC_CTRL11_7_4 0xf0 1174#define MSK_COC_CTL11_COC_CTRL11_3_0 0x0f 1175 1176/* CoC 21st Ctl, default value: 0x00 */ 1177#define REG_COC_CTL14 0x0724 1178#define MSK_COC_CTL14_COC_CTRL14_7_4 0xf0 1179#define MSK_COC_CTL14_COC_CTRL14_3_0 0x0f 1180 1181/* CoC 22nd Ctl, default value: 0x00 */ 1182#define REG_COC_CTL15 0x0725 1183#define BIT_COC_CTL15_COC_CTRL15_7 BIT(7) 1184#define MSK_COC_CTL15_COC_CTRL15_6_4 0x70 1185#define MSK_COC_CTL15_COC_CTRL15_3_0 0x0f 1186 1187/* CoC Interrupt, default value: 0x00 */ 1188#define REG_COC_INTR 0x0726 1189 1190/* CoC Interrupt Mask, default value: 0x00 */ 1191#define REG_COC_INTR_MASK 0x0727 1192#define BIT_COC_PLL_LOCK_STATUS_CHANGE BIT(0) 1193#define BIT_COC_CALIBRATION_DONE BIT(1) 1194 1195/* CoC Misc Ctl, default value: 0x00 */ 1196#define REG_COC_MISC_CTL0 0x0728 1197#define BIT_COC_MISC_CTL0_FSM_MON BIT(7) 1198 1199/* CoC 24th Ctl, default value: 0x00 */ 1200#define REG_COC_CTL17 0x072a 1201#define MSK_COC_CTL17_COC_CTRL17_7_4 0xf0 1202#define MSK_COC_CTL17_COC_CTRL17_3_0 0x0f 1203 1204/* CoC 25th Ctl, default value: 0x00 */ 1205#define REG_COC_CTL18 0x072b 1206#define MSK_COC_CTL18_COC_CTRL18_7_4 0xf0 1207#define MSK_COC_CTL18_COC_CTRL18_3_0 0x0f 1208 1209/* CoC 26th Ctl, default value: 0x00 */ 1210#define REG_COC_CTL19 0x072c 1211#define MSK_COC_CTL19_COC_CTRL19_7_4 0xf0 1212#define MSK_COC_CTL19_COC_CTRL19_3_0 0x0f 1213 1214/* CoC 27th Ctl, default value: 0x00 */ 1215#define REG_COC_CTL1A 0x072d 1216#define MSK_COC_CTL1A_COC_CTRL1A_7_2 0xfc 1217#define MSK_COC_CTL1A_COC_CTRL1A_1_0 0x03 1218 1219/* DoC 9th Status, default value: 0x00 */ 1220#define REG_DOC_STAT_8 0x0740 1221 1222/* DoC 10th Status, default value: 0x00 */ 1223#define REG_DOC_STAT_9 0x0741 1224 1225/* DoC 5th CFG, default value: 0x00 */ 1226#define REG_DOC_CFG4 0x074e 1227#define MSK_DOC_CFG4_DBG_STATE_DOC_FSM 0x0f 1228 1229/* DoC 1st Ctl, default value: 0x40 */ 1230#define REG_DOC_CTL0 0x0751 1231 1232/* DoC 7th Ctl, default value: 0x00 */ 1233#define REG_DOC_CTL6 0x0757 1234#define BIT_DOC_CTL6_DOC_CTRL6_7 BIT(7) 1235#define BIT_DOC_CTL6_DOC_CTRL6_6 BIT(6) 1236#define MSK_DOC_CTL6_DOC_CTRL6_5_4 0x30 1237#define MSK_DOC_CTL6_DOC_CTRL6_3_0 0x0f 1238 1239/* DoC 8th Ctl, default value: 0x00 */ 1240#define REG_DOC_CTL7 0x0758 1241#define BIT_DOC_CTL7_DOC_CTRL7_7 BIT(7) 1242#define BIT_DOC_CTL7_DOC_CTRL7_6 BIT(6) 1243#define BIT_DOC_CTL7_DOC_CTRL7_5 BIT(5) 1244#define MSK_DOC_CTL7_DOC_CTRL7_4_3 0x18 1245#define MSK_DOC_CTL7_DOC_CTRL7_2_0 0x07 1246 1247/* DoC 9th Ctl, default value: 0x00 */ 1248#define REG_DOC_CTL8 0x076c 1249#define BIT_DOC_CTL8_DOC_CTRL8_7 BIT(7) 1250#define MSK_DOC_CTL8_DOC_CTRL8_6_4 0x70 1251#define MSK_DOC_CTL8_DOC_CTRL8_3_2 0x0c 1252#define MSK_DOC_CTL8_DOC_CTRL8_1_0 0x03 1253 1254/* DoC 10th Ctl, default value: 0x00 */ 1255#define REG_DOC_CTL9 0x076d 1256 1257/* DoC 11th Ctl, default value: 0x00 */ 1258#define REG_DOC_CTLA 0x076e 1259 1260/* DoC 15th Ctl, default value: 0x00 */ 1261#define REG_DOC_CTLE 0x0772 1262#define BIT_DOC_CTLE_DOC_CTRLE_7 BIT(7) 1263#define BIT_DOC_CTLE_DOC_CTRLE_6 BIT(6) 1264#define MSK_DOC_CTLE_DOC_CTRLE_5_4 0x30 1265#define MSK_DOC_CTLE_DOC_CTRLE_3_0 0x0f 1266 1267/* Interrupt Mask 1st, default value: 0x00 */ 1268#define REG_MHL_INT_0_MASK 0x0580 1269 1270/* Interrupt Mask 2nd, default value: 0x00 */ 1271#define REG_MHL_INT_1_MASK 0x0581 1272 1273/* Interrupt Mask 3rd, default value: 0x00 */ 1274#define REG_MHL_INT_2_MASK 0x0582 1275 1276/* Interrupt Mask 4th, default value: 0x00 */ 1277#define REG_MHL_INT_3_MASK 0x0583 1278 1279/* MDT Receive Time Out, default value: 0x00 */ 1280#define REG_MDT_RCV_TIMEOUT 0x0584 1281 1282/* MDT Transmit Time Out, default value: 0x00 */ 1283#define REG_MDT_XMIT_TIMEOUT 0x0585 1284 1285/* MDT Receive Control, default value: 0x00 */ 1286#define REG_MDT_RCV_CTRL 0x0586 1287#define BIT_MDT_RCV_CTRL_MDT_RCV_EN BIT(7) 1288#define BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN BIT(6) 1289#define BIT_MDT_RCV_CTRL_MDT_RFIFO_OVER_WR_EN BIT(4) 1290#define BIT_MDT_RCV_CTRL_MDT_XFIFO_OVER_WR_EN BIT(3) 1291#define BIT_MDT_RCV_CTRL_MDT_DISABLE BIT(2) 1292#define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_ALL BIT(1) 1293#define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR BIT(0) 1294 1295/* MDT Receive Read Port, default value: 0x00 */ 1296#define REG_MDT_RCV_READ_PORT 0x0587 1297 1298/* MDT Transmit Control, default value: 0x70 */ 1299#define REG_MDT_XMIT_CTRL 0x0588 1300#define BIT_MDT_XMIT_CTRL_EN BIT(7) 1301#define BIT_MDT_XMIT_CTRL_CMD_MERGE_EN BIT(6) 1302#define BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN BIT(5) 1303#define BIT_MDT_XMIT_CTRL_FIXED_AID BIT(4) 1304#define BIT_MDT_XMIT_CTRL_SINGLE_RUN_EN BIT(3) 1305#define BIT_MDT_XMIT_CTRL_CLR_ABORT_WAIT BIT(2) 1306#define BIT_MDT_XMIT_CTRL_XFIFO_CLR_ALL BIT(1) 1307#define BIT_MDT_XMIT_CTRL_XFIFO_CLR_CUR BIT(0) 1308 1309/* MDT Receive WRITE Port, default value: 0x00 */ 1310#define REG_MDT_XMIT_WRITE_PORT 0x0589 1311 1312/* MDT RFIFO Status, default value: 0x00 */ 1313#define REG_MDT_RFIFO_STAT 0x058a 1314#define MSK_MDT_RFIFO_STAT_MDT_RFIFO_CNT 0xe0 1315#define MSK_MDT_RFIFO_STAT_MDT_RFIFO_CUR_BYTE_CNT 0x1f 1316 1317/* MDT XFIFO Status, default value: 0x80 */ 1318#define REG_MDT_XFIFO_STAT 0x058b 1319#define MSK_MDT_XFIFO_STAT_MDT_XFIFO_LEVEL_AVAIL 0xe0 1320#define BIT_MDT_XFIFO_STAT_MDT_XMIT_PRE_HS_EN BIT(4) 1321#define MSK_MDT_XFIFO_STAT_MDT_WRITE_BURST_LEN 0x0f 1322 1323/* MDT Interrupt 0, default value: 0x0c */ 1324#define REG_MDT_INT_0 0x058c 1325#define BIT_MDT_RFIFO_DATA_RDY BIT(0) 1326#define BIT_MDT_IDLE_AFTER_HAWB_DISABLE BIT(2) 1327#define BIT_MDT_XFIFO_EMPTY BIT(3) 1328 1329/* MDT Interrupt 0 Mask, default value: 0x00 */ 1330#define REG_MDT_INT_0_MASK 0x058d 1331 1332/* MDT Interrupt 1, default value: 0x00 */ 1333#define REG_MDT_INT_1 0x058e 1334#define BIT_MDT_RCV_TIMEOUT BIT(0) 1335#define BIT_MDT_RCV_SM_ABORT_PKT_RCVD BIT(1) 1336#define BIT_MDT_RCV_SM_ERROR BIT(2) 1337#define BIT_MDT_XMIT_TIMEOUT BIT(5) 1338#define BIT_MDT_XMIT_SM_ABORT_PKT_RCVD BIT(6) 1339#define BIT_MDT_XMIT_SM_ERROR BIT(7) 1340 1341/* MDT Interrupt 1 Mask, default value: 0x00 */ 1342#define REG_MDT_INT_1_MASK 0x058f 1343 1344/* CBUS Vendor ID, default value: 0x01 */ 1345#define REG_CBUS_VENDOR_ID 0x0590 1346 1347/* CBUS Connection Status, default value: 0x00 */ 1348#define REG_CBUS_STATUS 0x0591 1349#define BIT_CBUS_STATUS_MHL_CABLE_PRESENT BIT(4) 1350#define BIT_CBUS_STATUS_MSC_HB_SUCCESS BIT(3) 1351#define BIT_CBUS_STATUS_CBUS_HPD BIT(2) 1352#define BIT_CBUS_STATUS_MHL_MODE BIT(1) 1353#define BIT_CBUS_STATUS_CBUS_CONNECTED BIT(0) 1354 1355/* CBUS Interrupt 1st, default value: 0x00 */ 1356#define REG_CBUS_INT_0 0x0592 1357#define BIT_CBUS_MSC_MT_DONE_NACK BIT(7) 1358#define BIT_CBUS_MSC_MR_SET_INT BIT(6) 1359#define BIT_CBUS_MSC_MR_WRITE_BURST BIT(5) 1360#define BIT_CBUS_MSC_MR_MSC_MSG BIT(4) 1361#define BIT_CBUS_MSC_MR_WRITE_STAT BIT(3) 1362#define BIT_CBUS_HPD_CHG BIT(2) 1363#define BIT_CBUS_MSC_MT_DONE BIT(1) 1364#define BIT_CBUS_CNX_CHG BIT(0) 1365 1366/* CBUS Interrupt Mask 1st, default value: 0x00 */ 1367#define REG_CBUS_INT_0_MASK 0x0593 1368 1369/* CBUS Interrupt 2nd, default value: 0x00 */ 1370#define REG_CBUS_INT_1 0x0594 1371#define BIT_CBUS_CMD_ABORT BIT(6) 1372#define BIT_CBUS_MSC_ABORT_RCVD BIT(3) 1373#define BIT_CBUS_DDC_ABORT BIT(2) 1374#define BIT_CBUS_CEC_ABORT BIT(1) 1375 1376/* CBUS Interrupt Mask 2nd, default value: 0x00 */ 1377#define REG_CBUS_INT_1_MASK 0x0595 1378 1379/* CBUS DDC Abort Interrupt, default value: 0x00 */ 1380#define REG_DDC_ABORT_INT 0x0598 1381 1382/* CBUS DDC Abort Interrupt Mask, default value: 0x00 */ 1383#define REG_DDC_ABORT_INT_MASK 0x0599 1384 1385/* CBUS MSC Requester Abort Interrupt, default value: 0x00 */ 1386#define REG_MSC_MT_ABORT_INT 0x059a 1387 1388/* CBUS MSC Requester Abort Interrupt Mask, default value: 0x00 */ 1389#define REG_MSC_MT_ABORT_INT_MASK 0x059b 1390 1391/* CBUS MSC Responder Abort Interrupt, default value: 0x00 */ 1392#define REG_MSC_MR_ABORT_INT 0x059c 1393 1394/* CBUS MSC Responder Abort Interrupt Mask, default value: 0x00 */ 1395#define REG_MSC_MR_ABORT_INT_MASK 0x059d 1396 1397/* CBUS RX DISCOVERY interrupt, default value: 0x00 */ 1398#define REG_CBUS_RX_DISC_INT0 0x059e 1399 1400/* CBUS RX DISCOVERY Interrupt Mask, default value: 0x00 */ 1401#define REG_CBUS_RX_DISC_INT0_MASK 0x059f 1402 1403/* CBUS_Link_Layer Control #8, default value: 0x00 */ 1404#define REG_CBUS_LINK_CTRL_8 0x05a7 1405 1406/* MDT State Machine Status, default value: 0x00 */ 1407#define REG_MDT_SM_STAT 0x05b5 1408#define MSK_MDT_SM_STAT_MDT_RCV_STATE 0xf0 1409#define MSK_MDT_SM_STAT_MDT_XMIT_STATE 0x0f 1410 1411/* CBUS MSC command trigger, default value: 0x00 */ 1412#define REG_MSC_COMMAND_START 0x05b8 1413#define BIT_MSC_COMMAND_START_DEBUG BIT(5) 1414#define BIT_MSC_COMMAND_START_WRITE_BURST BIT(4) 1415#define BIT_MSC_COMMAND_START_WRITE_STAT BIT(3) 1416#define BIT_MSC_COMMAND_START_READ_DEVCAP BIT(2) 1417#define BIT_MSC_COMMAND_START_MSC_MSG BIT(1) 1418#define BIT_MSC_COMMAND_START_PEER BIT(0) 1419 1420/* CBUS MSC Command/Offset, default value: 0x00 */ 1421#define REG_MSC_CMD_OR_OFFSET 0x05b9 1422 1423/* CBUS MSC Transmit Data */ 1424#define REG_MSC_1ST_TRANSMIT_DATA 0x05ba 1425#define REG_MSC_2ND_TRANSMIT_DATA 0x05bb 1426 1427/* CBUS MSC Requester Received Data */ 1428#define REG_MSC_MT_RCVD_DATA0 0x05bc 1429#define REG_MSC_MT_RCVD_DATA1 0x05bd 1430 1431/* CBUS MSC Responder MSC_MSG Received Data */ 1432#define REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA 0x05bf 1433#define REG_MSC_MR_MSC_MSG_RCVD_2ND_DATA 0x05c0 1434 1435/* CBUS MSC Heartbeat Control, default value: 0x27 */ 1436#define REG_MSC_HEARTBEAT_CTRL 0x05c4 1437#define BIT_MSC_HEARTBEAT_CTRL_MSC_HB_EN BIT(7) 1438#define MSK_MSC_HEARTBEAT_CTRL_MSC_HB_FAIL_LIMIT 0x70 1439#define MSK_MSC_HEARTBEAT_CTRL_MSC_HB_PERIOD_MSB 0x0f 1440 1441/* CBUS MSC Compatibility Control, default value: 0x02 */ 1442#define REG_CBUS_MSC_COMPAT_CTRL 0x05c7 1443#define BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN BIT(7) 1444#define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_MSC_ON_CBUS BIT(6) 1445#define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_DDC_ON_CBUS BIT(5) 1446#define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_DDC_ERRORCODE BIT(3) 1447#define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_VS1_ERRORCODE BIT(2) 1448 1449/* CBUS3 Converter Control, default value: 0x24 */ 1450#define REG_CBUS3_CNVT 0x05dc 1451#define MSK_CBUS3_CNVT_CBUS3_RETRYLMT 0xf0 1452#define MSK_CBUS3_CNVT_CBUS3_PEERTOUT_SEL 0x0c 1453#define BIT_CBUS3_CNVT_TEARCBUS_EN BIT(1) 1454#define BIT_CBUS3_CNVT_CBUS3CNVT_EN BIT(0) 1455 1456/* Discovery Control1, default value: 0x24 */ 1457#define REG_DISC_CTRL1 0x05e0 1458#define BIT_DISC_CTRL1_CBUS_INTR_EN BIT(7) 1459#define BIT_DISC_CTRL1_HB_ONLY BIT(6) 1460#define MSK_DISC_CTRL1_DISC_ATT 0x30 1461#define MSK_DISC_CTRL1_DISC_CYC 0x0c 1462#define BIT_DISC_CTRL1_DISC_EN BIT(0) 1463 1464#define VAL_PUP_OFF 0 1465#define VAL_PUP_20K 1 1466#define VAL_PUP_5K 2 1467 1468/* Discovery Control4, default value: 0x80 */ 1469#define REG_DISC_CTRL4 0x05e3 1470#define MSK_DISC_CTRL4_CBUSDISC_PUP_SEL 0xc0 1471#define MSK_DISC_CTRL4_CBUSIDLE_PUP_SEL 0x30 1472#define VAL_DISC_CTRL4(pup_disc, pup_idle) (((pup_disc) << 6) | (pup_idle << 4)) 1473 1474/* Discovery Control5, default value: 0x03 */ 1475#define REG_DISC_CTRL5 0x05e4 1476#define BIT_DISC_CTRL5_DSM_OVRIDE BIT(3) 1477#define MSK_DISC_CTRL5_CBUSMHL_PUP_SEL 0x03 1478 1479/* Discovery Control8, default value: 0x81 */ 1480#define REG_DISC_CTRL8 0x05e7 1481#define BIT_DISC_CTRL8_NOMHLINT_CLR_BYPASS BIT(7) 1482#define BIT_DISC_CTRL8_DELAY_CBUS_INTR_EN BIT(0) 1483 1484/* Discovery Control9, default value: 0x54 */ 1485#define REG_DISC_CTRL9 0x05e8 1486#define BIT_DISC_CTRL9_MHL3_RSEN_BYP BIT(7) 1487#define BIT_DISC_CTRL9_MHL3DISC_EN BIT(6) 1488#define BIT_DISC_CTRL9_WAKE_DRVFLT BIT(4) 1489#define BIT_DISC_CTRL9_NOMHL_EST BIT(3) 1490#define BIT_DISC_CTRL9_DISC_PULSE_PROCEED BIT(2) 1491#define BIT_DISC_CTRL9_WAKE_PULSE_BYPASS BIT(1) 1492#define BIT_DISC_CTRL9_VBUS_OUTPUT_CAPABILITY_SRC BIT(0) 1493 1494/* Discovery Status1, default value: 0x00 */ 1495#define REG_DISC_STAT1 0x05eb 1496#define BIT_DISC_STAT1_PSM_OVRIDE BIT(5) 1497#define MSK_DISC_STAT1_DISC_SM 0x0f 1498 1499/* Discovery Status2, default value: 0x00 */ 1500#define REG_DISC_STAT2 0x05ec 1501#define BIT_DISC_STAT2_CBUS_OE_POL BIT(6) 1502#define BIT_DISC_STAT2_CBUS_SATUS BIT(5) 1503#define BIT_DISC_STAT2_RSEN BIT(4) 1504 1505#define MSK_DISC_STAT2_MHL_VRSN 0x0c 1506#define VAL_DISC_STAT2_DEFAULT 0x00 1507#define VAL_DISC_STAT2_MHL1_2 0x04 1508#define VAL_DISC_STAT2_MHL3 0x08 1509#define VAL_DISC_STAT2_RESERVED 0x0c 1510 1511#define MSK_DISC_STAT2_RGND 0x03 1512#define VAL_RGND_OPEN 0x00 1513#define VAL_RGND_2K 0x01 1514#define VAL_RGND_1K 0x02 1515#define VAL_RGND_SHORT 0x03 1516 1517/* Interrupt CBUS_reg1 INTR0, default value: 0x00 */ 1518#define REG_CBUS_DISC_INTR0 0x05ed 1519#define BIT_RGND_READY_INT BIT(6) 1520#define BIT_CBUS_MHL12_DISCON_INT BIT(5) 1521#define BIT_CBUS_MHL3_DISCON_INT BIT(4) 1522#define BIT_NOT_MHL_EST_INT BIT(3) 1523#define BIT_MHL_EST_INT BIT(2) 1524#define BIT_MHL3_EST_INT BIT(1) 1525#define VAL_CBUS_MHL_DISCON (BIT_CBUS_MHL12_DISCON_INT \ 1526 | BIT_CBUS_MHL3_DISCON_INT \ 1527 | BIT_NOT_MHL_EST_INT) 1528 1529/* Interrupt CBUS_reg1 INTR0 Mask, default value: 0x00 */ 1530#define REG_CBUS_DISC_INTR0_MASK 0x05ee 1531 1532#endif /* __SIL_SII8620_H__ */