cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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exynos_drm_drv.h (8012B)


      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/* exynos_drm_drv.h
      3 *
      4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
      5 * Authors:
      6 *	Inki Dae <inki.dae@samsung.com>
      7 *	Joonyoung Shim <jy0922.shim@samsung.com>
      8 *	Seung-Woo Kim <sw0312.kim@samsung.com>
      9 */
     10
     11#ifndef _EXYNOS_DRM_DRV_H_
     12#define _EXYNOS_DRM_DRV_H_
     13
     14#include <linux/module.h>
     15
     16#include <drm/drm_crtc.h>
     17#include <drm/drm_device.h>
     18#include <drm/drm_plane.h>
     19
     20#define MAX_CRTC	3
     21#define MAX_PLANE	5
     22#define MAX_FB_BUFFER	4
     23
     24#define DEFAULT_WIN	0
     25
     26struct drm_crtc_state;
     27struct drm_display_mode;
     28
     29#define to_exynos_crtc(x)	container_of(x, struct exynos_drm_crtc, base)
     30#define to_exynos_plane(x)	container_of(x, struct exynos_drm_plane, base)
     31
     32/* this enumerates display type. */
     33enum exynos_drm_output_type {
     34	EXYNOS_DISPLAY_TYPE_NONE,
     35	/* RGB or CPU Interface. */
     36	EXYNOS_DISPLAY_TYPE_LCD,
     37	/* HDMI Interface. */
     38	EXYNOS_DISPLAY_TYPE_HDMI,
     39	/* Virtual Display Interface. */
     40	EXYNOS_DISPLAY_TYPE_VIDI,
     41};
     42
     43struct exynos_drm_rect {
     44	unsigned int x, y;
     45	unsigned int w, h;
     46};
     47
     48/*
     49 * Exynos drm plane state structure.
     50 *
     51 * @base: plane_state object (contains drm_framebuffer pointer)
     52 * @src: rectangle of the source image data to be displayed (clipped to
     53 *       visible part).
     54 * @crtc: rectangle of the target image position on hardware screen
     55 *       (clipped to visible part).
     56 * @h_ratio: horizontal scaling ratio, 16.16 fixed point
     57 * @v_ratio: vertical scaling ratio, 16.16 fixed point
     58 *
     59 * this structure consists plane state data that will be applied to hardware
     60 * specific overlay info.
     61 */
     62
     63struct exynos_drm_plane_state {
     64	struct drm_plane_state base;
     65	struct exynos_drm_rect crtc;
     66	struct exynos_drm_rect src;
     67	unsigned int h_ratio;
     68	unsigned int v_ratio;
     69};
     70
     71static inline struct exynos_drm_plane_state *
     72to_exynos_plane_state(struct drm_plane_state *state)
     73{
     74	return container_of(state, struct exynos_drm_plane_state, base);
     75}
     76
     77/*
     78 * Exynos drm common overlay structure.
     79 *
     80 * @base: plane object
     81 * @index: hardware index of the overlay layer
     82 *
     83 * this structure is common to exynos SoC and its contents would be copied
     84 * to hardware specific overlay info.
     85 */
     86
     87struct exynos_drm_plane {
     88	struct drm_plane base;
     89	const struct exynos_drm_plane_config *config;
     90	unsigned int index;
     91};
     92
     93#define EXYNOS_DRM_PLANE_CAP_DOUBLE	(1 << 0)
     94#define EXYNOS_DRM_PLANE_CAP_SCALE	(1 << 1)
     95#define EXYNOS_DRM_PLANE_CAP_ZPOS	(1 << 2)
     96#define EXYNOS_DRM_PLANE_CAP_TILE	(1 << 3)
     97#define EXYNOS_DRM_PLANE_CAP_PIX_BLEND	(1 << 4)
     98#define EXYNOS_DRM_PLANE_CAP_WIN_BLEND	(1 << 5)
     99
    100/*
    101 * Exynos DRM plane configuration structure.
    102 *
    103 * @zpos: initial z-position of the plane.
    104 * @type: type of the plane (primary, cursor or overlay).
    105 * @pixel_formats: supported pixel formats.
    106 * @num_pixel_formats: number of elements in 'pixel_formats'.
    107 * @capabilities: supported features (see EXYNOS_DRM_PLANE_CAP_*)
    108 */
    109
    110struct exynos_drm_plane_config {
    111	unsigned int zpos;
    112	enum drm_plane_type type;
    113	const uint32_t *pixel_formats;
    114	unsigned int num_pixel_formats;
    115	unsigned int capabilities;
    116};
    117
    118/*
    119 * Exynos drm crtc ops
    120 *
    121 * @atomic_enable: enable the device
    122 * @atomic_disable: disable the device
    123 * @enable_vblank: specific driver callback for enabling vblank interrupt.
    124 * @disable_vblank: specific driver callback for disabling vblank interrupt.
    125 * @mode_valid: specific driver callback for mode validation
    126 * @atomic_check: validate state
    127 * @atomic_begin: prepare device to receive an update
    128 * @atomic_flush: mark the end of device update
    129 * @update_plane: apply hardware specific overlay data to registers.
    130 * @disable_plane: disable hardware specific overlay.
    131 * @te_handler: trigger to transfer video image at the tearing effect
    132 *	synchronization signal if there is a page flip request.
    133 */
    134struct exynos_drm_crtc;
    135struct exynos_drm_crtc_ops {
    136	void (*atomic_enable)(struct exynos_drm_crtc *crtc);
    137	void (*atomic_disable)(struct exynos_drm_crtc *crtc);
    138	int (*enable_vblank)(struct exynos_drm_crtc *crtc);
    139	void (*disable_vblank)(struct exynos_drm_crtc *crtc);
    140	enum drm_mode_status (*mode_valid)(struct exynos_drm_crtc *crtc,
    141		const struct drm_display_mode *mode);
    142	bool (*mode_fixup)(struct exynos_drm_crtc *crtc,
    143			   const struct drm_display_mode *mode,
    144			   struct drm_display_mode *adjusted_mode);
    145	int (*atomic_check)(struct exynos_drm_crtc *crtc,
    146			    struct drm_crtc_state *state);
    147	void (*atomic_begin)(struct exynos_drm_crtc *crtc);
    148	void (*update_plane)(struct exynos_drm_crtc *crtc,
    149			     struct exynos_drm_plane *plane);
    150	void (*disable_plane)(struct exynos_drm_crtc *crtc,
    151			      struct exynos_drm_plane *plane);
    152	void (*atomic_flush)(struct exynos_drm_crtc *crtc);
    153	void (*te_handler)(struct exynos_drm_crtc *crtc);
    154};
    155
    156struct exynos_drm_clk {
    157	void (*enable)(struct exynos_drm_clk *clk, bool enable);
    158};
    159
    160/*
    161 * Exynos specific crtc structure.
    162 *
    163 * @base: crtc object.
    164 * @type: one of EXYNOS_DISPLAY_TYPE_LCD and HDMI.
    165 * @ops: pointer to callbacks for exynos drm specific functionality
    166 * @ctx: A pointer to the crtc's implementation specific context
    167 * @pipe_clk: A pointer to the crtc's pipeline clock.
    168 */
    169struct exynos_drm_crtc {
    170	struct drm_crtc			base;
    171	enum exynos_drm_output_type	type;
    172	const struct exynos_drm_crtc_ops	*ops;
    173	void				*ctx;
    174	struct exynos_drm_clk		*pipe_clk;
    175	bool				i80_mode : 1;
    176};
    177
    178static inline void exynos_drm_pipe_clk_enable(struct exynos_drm_crtc *crtc,
    179					      bool enable)
    180{
    181	if (crtc->pipe_clk)
    182		crtc->pipe_clk->enable(crtc->pipe_clk, enable);
    183}
    184
    185struct drm_exynos_file_private {
    186	/* for g2d api */
    187	struct list_head	inuse_cmdlist;
    188	struct list_head	event_list;
    189	struct list_head	userptr_list;
    190};
    191
    192/*
    193 * Exynos drm private structure.
    194 *
    195 * @pending: the crtcs that have pending updates to finish
    196 * @lock: protect access to @pending
    197 * @wait: wait an atomic commit to finish
    198 */
    199struct exynos_drm_private {
    200	struct drm_fb_helper *fb_helper;
    201
    202	struct device *g2d_dev;
    203	struct device *dma_dev;
    204	void *mapping;
    205
    206	/* for atomic commit */
    207	u32			pending;
    208	spinlock_t		lock;
    209	wait_queue_head_t	wait;
    210};
    211
    212static inline struct device *to_dma_dev(struct drm_device *dev)
    213{
    214	struct exynos_drm_private *priv = dev->dev_private;
    215
    216	return priv->dma_dev;
    217}
    218
    219static inline bool is_drm_iommu_supported(struct drm_device *drm_dev)
    220{
    221	struct exynos_drm_private *priv = drm_dev->dev_private;
    222
    223	return priv->mapping ? true : false;
    224}
    225
    226int exynos_drm_register_dma(struct drm_device *drm, struct device *dev,
    227			    void **dma_priv);
    228void exynos_drm_unregister_dma(struct drm_device *drm, struct device *dev,
    229			       void **dma_priv);
    230void exynos_drm_cleanup_dma(struct drm_device *drm);
    231
    232#ifdef CONFIG_DRM_EXYNOS_DPI
    233struct drm_encoder *exynos_dpi_probe(struct device *dev);
    234int exynos_dpi_remove(struct drm_encoder *encoder);
    235int exynos_dpi_bind(struct drm_device *dev, struct drm_encoder *encoder);
    236#else
    237static inline struct drm_encoder *
    238exynos_dpi_probe(struct device *dev) { return NULL; }
    239static inline int exynos_dpi_remove(struct drm_encoder *encoder)
    240{
    241	return 0;
    242}
    243static inline int exynos_dpi_bind(struct drm_device *dev,
    244				  struct drm_encoder *encoder)
    245{
    246	return 0;
    247}
    248#endif
    249
    250#ifdef CONFIG_DRM_EXYNOS_FIMC
    251int exynos_drm_check_fimc_device(struct device *dev);
    252#else
    253static inline int exynos_drm_check_fimc_device(struct device *dev)
    254{
    255	return 0;
    256}
    257#endif
    258
    259int exynos_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state,
    260			 bool nonblock);
    261
    262
    263extern struct platform_driver fimd_driver;
    264extern struct platform_driver exynos5433_decon_driver;
    265extern struct platform_driver decon_driver;
    266extern struct platform_driver dp_driver;
    267extern struct platform_driver dsi_driver;
    268extern struct platform_driver mixer_driver;
    269extern struct platform_driver hdmi_driver;
    270extern struct platform_driver vidi_driver;
    271extern struct platform_driver g2d_driver;
    272extern struct platform_driver fimc_driver;
    273extern struct platform_driver rotator_driver;
    274extern struct platform_driver scaler_driver;
    275extern struct platform_driver gsc_driver;
    276extern struct platform_driver mic_driver;
    277#endif