cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intel_bw.h (1931B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Copyright © 2019 Intel Corporation
      4 */
      5
      6#ifndef __INTEL_BW_H__
      7#define __INTEL_BW_H__
      8
      9#include <drm/drm_atomic.h>
     10
     11#include "intel_display.h"
     12#include "intel_display_power.h"
     13#include "intel_global_state.h"
     14
     15struct drm_i915_private;
     16struct intel_atomic_state;
     17struct intel_crtc_state;
     18
     19struct intel_dbuf_bw {
     20	unsigned int max_bw[I915_MAX_DBUF_SLICES];
     21	u8 active_planes[I915_MAX_DBUF_SLICES];
     22};
     23
     24struct intel_bw_state {
     25	struct intel_global_state base;
     26	struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
     27
     28	/*
     29	 * Contains a bit mask, used to determine, whether correspondent
     30	 * pipe allows SAGV or not.
     31	 */
     32	u8 pipe_sagv_reject;
     33
     34	/* bitmask of active pipes */
     35	u8 active_pipes;
     36
     37	/*
     38	 * Current QGV points mask, which restricts
     39	 * some particular SAGV states, not to confuse
     40	 * with pipe_sagv_mask.
     41	 */
     42	u16 qgv_points_mask;
     43
     44	int min_cdclk[I915_MAX_PIPES];
     45	unsigned int data_rate[I915_MAX_PIPES];
     46	u8 num_active_planes[I915_MAX_PIPES];
     47};
     48
     49#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
     50
     51struct intel_bw_state *
     52intel_atomic_get_old_bw_state(struct intel_atomic_state *state);
     53
     54struct intel_bw_state *
     55intel_atomic_get_new_bw_state(struct intel_atomic_state *state);
     56
     57struct intel_bw_state *
     58intel_atomic_get_bw_state(struct intel_atomic_state *state);
     59
     60void intel_bw_init_hw(struct drm_i915_private *dev_priv);
     61int intel_bw_init(struct drm_i915_private *dev_priv);
     62int intel_bw_atomic_check(struct intel_atomic_state *state);
     63void intel_bw_crtc_update(struct intel_bw_state *bw_state,
     64			  const struct intel_crtc_state *crtc_state);
     65int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
     66				  u32 points_mask);
     67int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
     68			    bool *need_cdclk_calc);
     69int intel_bw_min_cdclk(struct drm_i915_private *i915,
     70		       const struct intel_bw_state *bw_state);
     71
     72#endif /* __INTEL_BW_H__ */