cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intel_cdclk.h (2962B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Copyright © 2019 Intel Corporation
      4 */
      5
      6#ifndef __INTEL_CDCLK_H__
      7#define __INTEL_CDCLK_H__
      8
      9#include <linux/types.h>
     10
     11#include "intel_display.h"
     12#include "intel_global_state.h"
     13
     14struct drm_i915_private;
     15struct intel_atomic_state;
     16struct intel_crtc_state;
     17
     18struct intel_cdclk_config {
     19	unsigned int cdclk, vco, ref, bypass;
     20	u8 voltage_level;
     21};
     22
     23struct intel_cdclk_state {
     24	struct intel_global_state base;
     25
     26	/*
     27	 * Logical configuration of cdclk (used for all scaling,
     28	 * watermark, etc. calculations and checks). This is
     29	 * computed as if all enabled crtcs were active.
     30	 */
     31	struct intel_cdclk_config logical;
     32
     33	/*
     34	 * Actual configuration of cdclk, can be different from the
     35	 * logical configuration only when all crtc's are DPMS off.
     36	 */
     37	struct intel_cdclk_config actual;
     38
     39	/* minimum acceptable cdclk to satisfy bandwidth requirements */
     40	int bw_min_cdclk;
     41	/* minimum acceptable cdclk for each pipe */
     42	int min_cdclk[I915_MAX_PIPES];
     43	/* minimum acceptable voltage level for each pipe */
     44	u8 min_voltage_level[I915_MAX_PIPES];
     45
     46	/* pipe to which cd2x update is synchronized */
     47	enum pipe pipe;
     48
     49	/* forced minimum cdclk for glk+ audio w/a */
     50	int force_min_cdclk;
     51
     52	/* bitmask of active pipes */
     53	u8 active_pipes;
     54};
     55
     56int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
     57void intel_cdclk_init_hw(struct drm_i915_private *i915);
     58void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
     59void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
     60void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
     61void intel_update_cdclk(struct drm_i915_private *dev_priv);
     62u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
     63bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
     64			       const struct intel_cdclk_config *b);
     65void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
     66void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
     67void intel_cdclk_dump_config(struct drm_i915_private *i915,
     68			     const struct intel_cdclk_config *cdclk_config,
     69			     const char *context);
     70int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
     71void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
     72			   struct intel_cdclk_config *cdclk_config);
     73int intel_cdclk_atomic_check(struct intel_atomic_state *state,
     74			     bool *need_cdclk_calc);
     75struct intel_cdclk_state *
     76intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
     77
     78#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)
     79#define intel_atomic_get_old_cdclk_state(state) \
     80	to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
     81#define intel_atomic_get_new_cdclk_state(state) \
     82	to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
     83
     84int intel_cdclk_init(struct drm_i915_private *dev_priv);
     85
     86#endif /* __INTEL_CDCLK_H__ */