cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intel_de.h (2208B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Copyright © 2019 Intel Corporation
      4 */
      5
      6#ifndef __INTEL_DE_H__
      7#define __INTEL_DE_H__
      8
      9#include "i915_drv.h"
     10#include "i915_trace.h"
     11#include "intel_uncore.h"
     12
     13static inline u32
     14intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
     15{
     16	return intel_uncore_read(&i915->uncore, reg);
     17}
     18
     19static inline void
     20intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
     21{
     22	intel_uncore_posting_read(&i915->uncore, reg);
     23}
     24
     25static inline void
     26intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
     27{
     28	intel_uncore_write(&i915->uncore, reg, val);
     29}
     30
     31static inline void
     32intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
     33{
     34	intel_uncore_rmw(&i915->uncore, reg, clear, set);
     35}
     36
     37static inline int
     38intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
     39			   u32 mask, u32 value, unsigned int timeout)
     40{
     41	return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout);
     42}
     43
     44static inline int
     45intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
     46		      u32 mask, unsigned int timeout)
     47{
     48	return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
     49}
     50
     51static inline int
     52intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
     53			u32 mask, unsigned int timeout)
     54{
     55	return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
     56}
     57
     58/*
     59 * Unlocked mmio-accessors, think carefully before using these.
     60 *
     61 * Certain architectures will die if the same cacheline is concurrently accessed
     62 * by different clients (e.g. on Ivybridge). Access to registers should
     63 * therefore generally be serialised, by either the dev_priv->uncore.lock or
     64 * a more localised lock guarding all access to that bank of registers.
     65 */
     66static inline u32
     67intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
     68{
     69	u32 val;
     70
     71	val = intel_uncore_read_fw(&i915->uncore, reg);
     72	trace_i915_reg_rw(false, reg, val, sizeof(val), true);
     73
     74	return val;
     75}
     76
     77static inline void
     78intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
     79{
     80	trace_i915_reg_rw(true, reg, val, sizeof(val), true);
     81	intel_uncore_write_fw(&i915->uncore, reg, val);
     82}
     83
     84#endif /* __INTEL_DE_H__ */