intel_display_power_well.h (5755B)
1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright © 2022 Intel Corporation 4 */ 5#ifndef __INTEL_DISPLAY_POWER_WELL_H__ 6#define __INTEL_DISPLAY_POWER_WELL_H__ 7 8#include <linux/types.h> 9 10#include "intel_display.h" 11#include "intel_display_power.h" 12 13struct drm_i915_private; 14struct i915_power_well; 15 16#define for_each_power_well(__dev_priv, __power_well) \ 17 for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ 18 (__power_well) - (__dev_priv)->power_domains.power_wells < \ 19 (__dev_priv)->power_domains.power_well_count; \ 20 (__power_well)++) 21 22#define for_each_power_well_reverse(__dev_priv, __power_well) \ 23 for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ 24 (__dev_priv)->power_domains.power_well_count - 1; \ 25 (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ 26 (__power_well)--) 27 28/* 29 * i915_power_well_id: 30 * 31 * IDs used to look up power wells. Power wells accessed directly bypassing 32 * the power domains framework must be assigned a unique ID. The rest of power 33 * wells must be assigned DISP_PW_ID_NONE. 34 */ 35enum i915_power_well_id { 36 DISP_PW_ID_NONE = 0, /* must be kept zero */ 37 38 VLV_DISP_PW_DISP2D, 39 BXT_DISP_PW_DPIO_CMN_A, 40 VLV_DISP_PW_DPIO_CMN_BC, 41 GLK_DISP_PW_DPIO_CMN_C, 42 CHV_DISP_PW_DPIO_CMN_D, 43 HSW_DISP_PW_GLOBAL, 44 SKL_DISP_PW_MISC_IO, 45 SKL_DISP_PW_1, 46 SKL_DISP_PW_2, 47 ICL_DISP_PW_3, 48 SKL_DISP_DC_OFF, 49 TGL_DISP_PW_TC_COLD_OFF, 50}; 51 52struct i915_power_well_instance { 53 const char *name; 54 const struct i915_power_domain_list { 55 const enum intel_display_power_domain *list; 56 u8 count; 57 } *domain_list; 58 59 /* unique identifier for this power well */ 60 enum i915_power_well_id id; 61 /* 62 * Arbitraty data associated with this power well. Platform and power 63 * well specific. 64 */ 65 union { 66 struct { 67 /* 68 * request/status flag index in the PUNIT power well 69 * control/status registers. 70 */ 71 u8 idx; 72 } vlv; 73 struct { 74 enum dpio_phy phy; 75 } bxt; 76 struct { 77 /* 78 * request/status flag index in the power well 79 * constrol/status registers. 80 */ 81 u8 idx; 82 } hsw; 83 }; 84}; 85 86struct i915_power_well_desc { 87 const struct i915_power_well_ops *ops; 88 const struct i915_power_well_instance_list { 89 const struct i915_power_well_instance *list; 90 u8 count; 91 } *instances; 92 93 /* Mask of pipes whose IRQ logic is backed by the pw */ 94 u16 irq_pipe_mask:4; 95 u16 always_on:1; 96 /* 97 * Instead of waiting for the status bit to ack enables, 98 * just wait a specific amount of time and then consider 99 * the well enabled. 100 */ 101 u16 fixed_enable_delay:1; 102 /* The pw is backing the VGA functionality */ 103 u16 has_vga:1; 104 u16 has_fuses:1; 105 /* 106 * The pw is for an ICL+ TypeC PHY port in 107 * Thunderbolt mode. 108 */ 109 u16 is_tc_tbt:1; 110}; 111 112struct i915_power_well { 113 const struct i915_power_well_desc *desc; 114 struct intel_power_domain_mask domains; 115 /* power well enable/disable usage count */ 116 int count; 117 /* cached hw enabled state */ 118 bool hw_enabled; 119 /* index into desc->instances->list */ 120 u8 instance_idx; 121}; 122 123struct i915_power_well *lookup_power_well(struct drm_i915_private *i915, 124 enum i915_power_well_id id); 125 126void intel_power_well_enable(struct drm_i915_private *i915, 127 struct i915_power_well *power_well); 128void intel_power_well_disable(struct drm_i915_private *i915, 129 struct i915_power_well *power_well); 130void intel_power_well_sync_hw(struct drm_i915_private *i915, 131 struct i915_power_well *power_well); 132void intel_power_well_get(struct drm_i915_private *i915, 133 struct i915_power_well *power_well); 134void intel_power_well_put(struct drm_i915_private *i915, 135 struct i915_power_well *power_well); 136bool intel_power_well_is_enabled(struct drm_i915_private *i915, 137 struct i915_power_well *power_well); 138bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well); 139bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 140 enum i915_power_well_id power_well_id); 141bool intel_power_well_is_always_on(struct i915_power_well *power_well); 142const char *intel_power_well_name(struct i915_power_well *power_well); 143struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well); 144int intel_power_well_refcount(struct i915_power_well *power_well); 145 146void chv_phy_powergate_lanes(struct intel_encoder *encoder, 147 bool override, unsigned int mask); 148bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 149 enum dpio_channel ch, bool override); 150 151void gen9_enable_dc5(struct drm_i915_private *dev_priv); 152void skl_enable_dc6(struct drm_i915_private *dev_priv); 153void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv); 154void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state); 155void gen9_disable_dc_states(struct drm_i915_private *dev_priv); 156void bxt_enable_dc9(struct drm_i915_private *dev_priv); 157void bxt_disable_dc9(struct drm_i915_private *dev_priv); 158 159extern const struct i915_power_well_ops i9xx_always_on_power_well_ops; 160extern const struct i915_power_well_ops chv_pipe_power_well_ops; 161extern const struct i915_power_well_ops chv_dpio_cmn_power_well_ops; 162extern const struct i915_power_well_ops i830_pipes_power_well_ops; 163extern const struct i915_power_well_ops hsw_power_well_ops; 164extern const struct i915_power_well_ops gen9_dc_off_power_well_ops; 165extern const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops; 166extern const struct i915_power_well_ops vlv_display_power_well_ops; 167extern const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops; 168extern const struct i915_power_well_ops vlv_dpio_power_well_ops; 169extern const struct i915_power_well_ops icl_aux_power_well_ops; 170extern const struct i915_power_well_ops icl_ddi_power_well_ops; 171extern const struct i915_power_well_ops tgl_tc_cold_off_ops; 172 173#endif