cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
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intel_overlay.c (39235B)


      1/*
      2 * Copyright © 2009
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice (including the next
     12 * paragraph) shall be included in all copies or substantial portions of the
     13 * Software.
     14 *
     15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     21 * SOFTWARE.
     22 *
     23 * Authors:
     24 *    Daniel Vetter <daniel@ffwll.ch>
     25 *
     26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
     27 */
     28
     29#include <drm/drm_fourcc.h>
     30
     31#include "gem/i915_gem_internal.h"
     32#include "gem/i915_gem_pm.h"
     33#include "gt/intel_gpu_commands.h"
     34#include "gt/intel_ring.h"
     35
     36#include "i915_drv.h"
     37#include "i915_reg.h"
     38#include "intel_de.h"
     39#include "intel_display_types.h"
     40#include "intel_frontbuffer.h"
     41#include "intel_overlay.h"
     42#include "intel_pci_config.h"
     43
     44/* Limits for overlay size. According to intel doc, the real limits are:
     45 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
     46 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
     47 * the mininum of both.  */
     48#define IMAGE_MAX_WIDTH		2048
     49#define IMAGE_MAX_HEIGHT	2046 /* 2 * 1023 */
     50/* on 830 and 845 these large limits result in the card hanging */
     51#define IMAGE_MAX_WIDTH_LEGACY	1024
     52#define IMAGE_MAX_HEIGHT_LEGACY	1088
     53
     54/* overlay register definitions */
     55/* OCMD register */
     56#define OCMD_TILED_SURFACE	(0x1<<19)
     57#define OCMD_MIRROR_MASK	(0x3<<17)
     58#define OCMD_MIRROR_MODE	(0x3<<17)
     59#define OCMD_MIRROR_HORIZONTAL	(0x1<<17)
     60#define OCMD_MIRROR_VERTICAL	(0x2<<17)
     61#define OCMD_MIRROR_BOTH	(0x3<<17)
     62#define OCMD_BYTEORDER_MASK	(0x3<<14) /* zero for YUYV or FOURCC YUY2 */
     63#define OCMD_UV_SWAP		(0x1<<14) /* YVYU */
     64#define OCMD_Y_SWAP		(0x2<<14) /* UYVY or FOURCC UYVY */
     65#define OCMD_Y_AND_UV_SWAP	(0x3<<14) /* VYUY */
     66#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
     67#define OCMD_RGB_888		(0x1<<10) /* not in i965 Intel docs */
     68#define OCMD_RGB_555		(0x2<<10) /* not in i965 Intel docs */
     69#define OCMD_RGB_565		(0x3<<10) /* not in i965 Intel docs */
     70#define OCMD_YUV_422_PACKED	(0x8<<10)
     71#define OCMD_YUV_411_PACKED	(0x9<<10) /* not in i965 Intel docs */
     72#define OCMD_YUV_420_PLANAR	(0xc<<10)
     73#define OCMD_YUV_422_PLANAR	(0xd<<10)
     74#define OCMD_YUV_410_PLANAR	(0xe<<10) /* also 411 */
     75#define OCMD_TVSYNCFLIP_PARITY	(0x1<<9)
     76#define OCMD_TVSYNCFLIP_ENABLE	(0x1<<7)
     77#define OCMD_BUF_TYPE_MASK	(0x1<<5)
     78#define OCMD_BUF_TYPE_FRAME	(0x0<<5)
     79#define OCMD_BUF_TYPE_FIELD	(0x1<<5)
     80#define OCMD_TEST_MODE		(0x1<<4)
     81#define OCMD_BUFFER_SELECT	(0x3<<2)
     82#define OCMD_BUFFER0		(0x0<<2)
     83#define OCMD_BUFFER1		(0x1<<2)
     84#define OCMD_FIELD_SELECT	(0x1<<2)
     85#define OCMD_FIELD0		(0x0<<1)
     86#define OCMD_FIELD1		(0x1<<1)
     87#define OCMD_ENABLE		(0x1<<0)
     88
     89/* OCONFIG register */
     90#define OCONF_PIPE_MASK		(0x1<<18)
     91#define OCONF_PIPE_A		(0x0<<18)
     92#define OCONF_PIPE_B		(0x1<<18)
     93#define OCONF_GAMMA2_ENABLE	(0x1<<16)
     94#define OCONF_CSC_MODE_BT601	(0x0<<5)
     95#define OCONF_CSC_MODE_BT709	(0x1<<5)
     96#define OCONF_CSC_BYPASS	(0x1<<4)
     97#define OCONF_CC_OUT_8BIT	(0x1<<3)
     98#define OCONF_TEST_MODE		(0x1<<2)
     99#define OCONF_THREE_LINE_BUFFER	(0x1<<0)
    100#define OCONF_TWO_LINE_BUFFER	(0x0<<0)
    101
    102/* DCLRKM (dst-key) register */
    103#define DST_KEY_ENABLE		(0x1<<31)
    104#define CLK_RGB24_MASK		0x0
    105#define CLK_RGB16_MASK		0x070307
    106#define CLK_RGB15_MASK		0x070707
    107
    108#define RGB30_TO_COLORKEY(c) \
    109	((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2))
    110#define RGB16_TO_COLORKEY(c) \
    111	((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3))
    112#define RGB15_TO_COLORKEY(c) \
    113	((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3))
    114#define RGB8I_TO_COLORKEY(c) \
    115	((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0))
    116
    117/* overlay flip addr flag */
    118#define OFC_UPDATE		0x1
    119
    120/* polyphase filter coefficients */
    121#define N_HORIZ_Y_TAPS          5
    122#define N_VERT_Y_TAPS           3
    123#define N_HORIZ_UV_TAPS         3
    124#define N_VERT_UV_TAPS          3
    125#define N_PHASES                17
    126#define MAX_TAPS                5
    127
    128/* memory bufferd overlay registers */
    129struct overlay_registers {
    130	u32 OBUF_0Y;
    131	u32 OBUF_1Y;
    132	u32 OBUF_0U;
    133	u32 OBUF_0V;
    134	u32 OBUF_1U;
    135	u32 OBUF_1V;
    136	u32 OSTRIDE;
    137	u32 YRGB_VPH;
    138	u32 UV_VPH;
    139	u32 HORZ_PH;
    140	u32 INIT_PHS;
    141	u32 DWINPOS;
    142	u32 DWINSZ;
    143	u32 SWIDTH;
    144	u32 SWIDTHSW;
    145	u32 SHEIGHT;
    146	u32 YRGBSCALE;
    147	u32 UVSCALE;
    148	u32 OCLRC0;
    149	u32 OCLRC1;
    150	u32 DCLRKV;
    151	u32 DCLRKM;
    152	u32 SCLRKVH;
    153	u32 SCLRKVL;
    154	u32 SCLRKEN;
    155	u32 OCONFIG;
    156	u32 OCMD;
    157	u32 RESERVED1; /* 0x6C */
    158	u32 OSTART_0Y;
    159	u32 OSTART_1Y;
    160	u32 OSTART_0U;
    161	u32 OSTART_0V;
    162	u32 OSTART_1U;
    163	u32 OSTART_1V;
    164	u32 OTILEOFF_0Y;
    165	u32 OTILEOFF_1Y;
    166	u32 OTILEOFF_0U;
    167	u32 OTILEOFF_0V;
    168	u32 OTILEOFF_1U;
    169	u32 OTILEOFF_1V;
    170	u32 FASTHSCALE; /* 0xA0 */
    171	u32 UVSCALEV; /* 0xA4 */
    172	u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
    173	u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
    174	u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
    175	u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
    176	u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
    177	u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
    178	u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
    179	u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
    180	u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
    181};
    182
    183struct intel_overlay {
    184	struct drm_i915_private *i915;
    185	struct intel_context *context;
    186	struct intel_crtc *crtc;
    187	struct i915_vma *vma;
    188	struct i915_vma *old_vma;
    189	struct intel_frontbuffer *frontbuffer;
    190	bool active;
    191	bool pfit_active;
    192	u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
    193	u32 color_key:24;
    194	u32 color_key_enabled:1;
    195	u32 brightness, contrast, saturation;
    196	u32 old_xscale, old_yscale;
    197	/* register access */
    198	struct drm_i915_gem_object *reg_bo;
    199	struct overlay_registers __iomem *regs;
    200	u32 flip_addr;
    201	/* flip handling */
    202	struct i915_active last_flip;
    203	void (*flip_complete)(struct intel_overlay *ovl);
    204};
    205
    206static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
    207				      bool enable)
    208{
    209	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
    210	u8 val;
    211
    212	/* WA_OVERLAY_CLKGATE:alm */
    213	if (enable)
    214		intel_de_write(dev_priv, DSPCLK_GATE_D, 0);
    215	else
    216		intel_de_write(dev_priv, DSPCLK_GATE_D,
    217			       OVRUNIT_CLOCK_GATE_DISABLE);
    218
    219	/* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
    220	pci_bus_read_config_byte(pdev->bus,
    221				 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);
    222	if (enable)
    223		val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE;
    224	else
    225		val |= I830_L2_CACHE_CLOCK_GATE_DISABLE;
    226	pci_bus_write_config_byte(pdev->bus,
    227				  PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
    228}
    229
    230static struct i915_request *
    231alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *))
    232{
    233	struct i915_request *rq;
    234	int err;
    235
    236	overlay->flip_complete = fn;
    237
    238	rq = i915_request_create(overlay->context);
    239	if (IS_ERR(rq))
    240		return rq;
    241
    242	err = i915_active_add_request(&overlay->last_flip, rq);
    243	if (err) {
    244		i915_request_add(rq);
    245		return ERR_PTR(err);
    246	}
    247
    248	return rq;
    249}
    250
    251/* overlay needs to be disable in OCMD reg */
    252static int intel_overlay_on(struct intel_overlay *overlay)
    253{
    254	struct drm_i915_private *dev_priv = overlay->i915;
    255	struct i915_request *rq;
    256	u32 *cs;
    257
    258	drm_WARN_ON(&dev_priv->drm, overlay->active);
    259
    260	rq = alloc_request(overlay, NULL);
    261	if (IS_ERR(rq))
    262		return PTR_ERR(rq);
    263
    264	cs = intel_ring_begin(rq, 4);
    265	if (IS_ERR(cs)) {
    266		i915_request_add(rq);
    267		return PTR_ERR(cs);
    268	}
    269
    270	overlay->active = true;
    271
    272	if (IS_I830(dev_priv))
    273		i830_overlay_clock_gating(dev_priv, false);
    274
    275	*cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON;
    276	*cs++ = overlay->flip_addr | OFC_UPDATE;
    277	*cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
    278	*cs++ = MI_NOOP;
    279	intel_ring_advance(rq, cs);
    280
    281	i915_request_add(rq);
    282
    283	return i915_active_wait(&overlay->last_flip);
    284}
    285
    286static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
    287				       struct i915_vma *vma)
    288{
    289	enum pipe pipe = overlay->crtc->pipe;
    290	struct intel_frontbuffer *frontbuffer = NULL;
    291
    292	drm_WARN_ON(&overlay->i915->drm, overlay->old_vma);
    293
    294	if (vma)
    295		frontbuffer = intel_frontbuffer_get(vma->obj);
    296
    297	intel_frontbuffer_track(overlay->frontbuffer, frontbuffer,
    298				INTEL_FRONTBUFFER_OVERLAY(pipe));
    299
    300	if (overlay->frontbuffer)
    301		intel_frontbuffer_put(overlay->frontbuffer);
    302	overlay->frontbuffer = frontbuffer;
    303
    304	intel_frontbuffer_flip_prepare(overlay->i915,
    305				       INTEL_FRONTBUFFER_OVERLAY(pipe));
    306
    307	overlay->old_vma = overlay->vma;
    308	if (vma)
    309		overlay->vma = i915_vma_get(vma);
    310	else
    311		overlay->vma = NULL;
    312}
    313
    314/* overlay needs to be enabled in OCMD reg */
    315static int intel_overlay_continue(struct intel_overlay *overlay,
    316				  struct i915_vma *vma,
    317				  bool load_polyphase_filter)
    318{
    319	struct drm_i915_private *dev_priv = overlay->i915;
    320	struct i915_request *rq;
    321	u32 flip_addr = overlay->flip_addr;
    322	u32 tmp, *cs;
    323
    324	drm_WARN_ON(&dev_priv->drm, !overlay->active);
    325
    326	if (load_polyphase_filter)
    327		flip_addr |= OFC_UPDATE;
    328
    329	/* check for underruns */
    330	tmp = intel_de_read(dev_priv, DOVSTA);
    331	if (tmp & (1 << 17))
    332		drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp);
    333
    334	rq = alloc_request(overlay, NULL);
    335	if (IS_ERR(rq))
    336		return PTR_ERR(rq);
    337
    338	cs = intel_ring_begin(rq, 2);
    339	if (IS_ERR(cs)) {
    340		i915_request_add(rq);
    341		return PTR_ERR(cs);
    342	}
    343
    344	*cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
    345	*cs++ = flip_addr;
    346	intel_ring_advance(rq, cs);
    347
    348	intel_overlay_flip_prepare(overlay, vma);
    349	i915_request_add(rq);
    350
    351	return 0;
    352}
    353
    354static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
    355{
    356	struct i915_vma *vma;
    357
    358	vma = fetch_and_zero(&overlay->old_vma);
    359	if (drm_WARN_ON(&overlay->i915->drm, !vma))
    360		return;
    361
    362	intel_frontbuffer_flip_complete(overlay->i915,
    363					INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
    364
    365	i915_vma_unpin(vma);
    366	i915_vma_put(vma);
    367}
    368
    369static void
    370intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
    371{
    372	intel_overlay_release_old_vma(overlay);
    373}
    374
    375static void intel_overlay_off_tail(struct intel_overlay *overlay)
    376{
    377	struct drm_i915_private *dev_priv = overlay->i915;
    378
    379	intel_overlay_release_old_vma(overlay);
    380
    381	overlay->crtc->overlay = NULL;
    382	overlay->crtc = NULL;
    383	overlay->active = false;
    384
    385	if (IS_I830(dev_priv))
    386		i830_overlay_clock_gating(dev_priv, true);
    387}
    388
    389static void intel_overlay_last_flip_retire(struct i915_active *active)
    390{
    391	struct intel_overlay *overlay =
    392		container_of(active, typeof(*overlay), last_flip);
    393
    394	if (overlay->flip_complete)
    395		overlay->flip_complete(overlay);
    396}
    397
    398/* overlay needs to be disabled in OCMD reg */
    399static int intel_overlay_off(struct intel_overlay *overlay)
    400{
    401	struct i915_request *rq;
    402	u32 *cs, flip_addr = overlay->flip_addr;
    403
    404	drm_WARN_ON(&overlay->i915->drm, !overlay->active);
    405
    406	/* According to intel docs the overlay hw may hang (when switching
    407	 * off) without loading the filter coeffs. It is however unclear whether
    408	 * this applies to the disabling of the overlay or to the switching off
    409	 * of the hw. Do it in both cases */
    410	flip_addr |= OFC_UPDATE;
    411
    412	rq = alloc_request(overlay, intel_overlay_off_tail);
    413	if (IS_ERR(rq))
    414		return PTR_ERR(rq);
    415
    416	cs = intel_ring_begin(rq, 6);
    417	if (IS_ERR(cs)) {
    418		i915_request_add(rq);
    419		return PTR_ERR(cs);
    420	}
    421
    422	/* wait for overlay to go idle */
    423	*cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
    424	*cs++ = flip_addr;
    425	*cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
    426
    427	/* turn overlay off */
    428	*cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF;
    429	*cs++ = flip_addr;
    430	*cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
    431
    432	intel_ring_advance(rq, cs);
    433
    434	intel_overlay_flip_prepare(overlay, NULL);
    435	i915_request_add(rq);
    436
    437	return i915_active_wait(&overlay->last_flip);
    438}
    439
    440/* recover from an interruption due to a signal
    441 * We have to be careful not to repeat work forever an make forward progess. */
    442static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
    443{
    444	return i915_active_wait(&overlay->last_flip);
    445}
    446
    447/* Wait for pending overlay flip and release old frame.
    448 * Needs to be called before the overlay register are changed
    449 * via intel_overlay_(un)map_regs
    450 */
    451static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
    452{
    453	struct drm_i915_private *dev_priv = overlay->i915;
    454	struct i915_request *rq;
    455	u32 *cs;
    456
    457	/*
    458	 * Only wait if there is actually an old frame to release to
    459	 * guarantee forward progress.
    460	 */
    461	if (!overlay->old_vma)
    462		return 0;
    463
    464	if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) {
    465		intel_overlay_release_old_vid_tail(overlay);
    466		return 0;
    467	}
    468
    469	rq = alloc_request(overlay, intel_overlay_release_old_vid_tail);
    470	if (IS_ERR(rq))
    471		return PTR_ERR(rq);
    472
    473	cs = intel_ring_begin(rq, 2);
    474	if (IS_ERR(cs)) {
    475		i915_request_add(rq);
    476		return PTR_ERR(cs);
    477	}
    478
    479	*cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
    480	*cs++ = MI_NOOP;
    481	intel_ring_advance(rq, cs);
    482
    483	i915_request_add(rq);
    484
    485	return i915_active_wait(&overlay->last_flip);
    486}
    487
    488void intel_overlay_reset(struct drm_i915_private *dev_priv)
    489{
    490	struct intel_overlay *overlay = dev_priv->overlay;
    491
    492	if (!overlay)
    493		return;
    494
    495	overlay->old_xscale = 0;
    496	overlay->old_yscale = 0;
    497	overlay->crtc = NULL;
    498	overlay->active = false;
    499}
    500
    501static int packed_depth_bytes(u32 format)
    502{
    503	switch (format & I915_OVERLAY_DEPTH_MASK) {
    504	case I915_OVERLAY_YUV422:
    505		return 4;
    506	case I915_OVERLAY_YUV411:
    507		/* return 6; not implemented */
    508	default:
    509		return -EINVAL;
    510	}
    511}
    512
    513static int packed_width_bytes(u32 format, short width)
    514{
    515	switch (format & I915_OVERLAY_DEPTH_MASK) {
    516	case I915_OVERLAY_YUV422:
    517		return width << 1;
    518	default:
    519		return -EINVAL;
    520	}
    521}
    522
    523static int uv_hsubsampling(u32 format)
    524{
    525	switch (format & I915_OVERLAY_DEPTH_MASK) {
    526	case I915_OVERLAY_YUV422:
    527	case I915_OVERLAY_YUV420:
    528		return 2;
    529	case I915_OVERLAY_YUV411:
    530	case I915_OVERLAY_YUV410:
    531		return 4;
    532	default:
    533		return -EINVAL;
    534	}
    535}
    536
    537static int uv_vsubsampling(u32 format)
    538{
    539	switch (format & I915_OVERLAY_DEPTH_MASK) {
    540	case I915_OVERLAY_YUV420:
    541	case I915_OVERLAY_YUV410:
    542		return 2;
    543	case I915_OVERLAY_YUV422:
    544	case I915_OVERLAY_YUV411:
    545		return 1;
    546	default:
    547		return -EINVAL;
    548	}
    549}
    550
    551static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
    552{
    553	u32 sw;
    554
    555	if (DISPLAY_VER(dev_priv) == 2)
    556		sw = ALIGN((offset & 31) + width, 32);
    557	else
    558		sw = ALIGN((offset & 63) + width, 64);
    559
    560	if (sw == 0)
    561		return 0;
    562
    563	return (sw - 32) >> 3;
    564}
    565
    566static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = {
    567	[ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, },
    568	[ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, },
    569	[ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, },
    570	[ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, },
    571	[ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, },
    572	[ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, },
    573	[ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, },
    574	[ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, },
    575	[ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, },
    576	[ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, },
    577	[10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, },
    578	[11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, },
    579	[12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, },
    580	[13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, },
    581	[14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, },
    582	[15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, },
    583	[16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, },
    584};
    585
    586static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = {
    587	[ 0] = { 0x3000, 0x1800, 0x1800, },
    588	[ 1] = { 0xb000, 0x18d0, 0x2e60, },
    589	[ 2] = { 0xb000, 0x1990, 0x2ce0, },
    590	[ 3] = { 0xb020, 0x1a68, 0x2b40, },
    591	[ 4] = { 0xb040, 0x1b20, 0x29e0, },
    592	[ 5] = { 0xb060, 0x1bd8, 0x2880, },
    593	[ 6] = { 0xb080, 0x1c88, 0x3e60, },
    594	[ 7] = { 0xb0a0, 0x1d28, 0x3c00, },
    595	[ 8] = { 0xb0c0, 0x1db8, 0x39e0, },
    596	[ 9] = { 0xb0e0, 0x1e40, 0x37e0, },
    597	[10] = { 0xb100, 0x1eb8, 0x3620, },
    598	[11] = { 0xb100, 0x1f18, 0x34a0, },
    599	[12] = { 0xb100, 0x1f68, 0x3360, },
    600	[13] = { 0xb0e0, 0x1fa8, 0x3240, },
    601	[14] = { 0xb0c0, 0x1fe0, 0x3140, },
    602	[15] = { 0xb060, 0x1ff0, 0x30a0, },
    603	[16] = { 0x3000, 0x0800, 0x3000, },
    604};
    605
    606static void update_polyphase_filter(struct overlay_registers __iomem *regs)
    607{
    608	memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
    609	memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
    610		    sizeof(uv_static_hcoeffs));
    611}
    612
    613static bool update_scaling_factors(struct intel_overlay *overlay,
    614				   struct overlay_registers __iomem *regs,
    615				   struct drm_intel_overlay_put_image *params)
    616{
    617	/* fixed point with a 12 bit shift */
    618	u32 xscale, yscale, xscale_UV, yscale_UV;
    619#define FP_SHIFT 12
    620#define FRACT_MASK 0xfff
    621	bool scale_changed = false;
    622	int uv_hscale = uv_hsubsampling(params->flags);
    623	int uv_vscale = uv_vsubsampling(params->flags);
    624
    625	if (params->dst_width > 1)
    626		xscale = ((params->src_scan_width - 1) << FP_SHIFT) /
    627			params->dst_width;
    628	else
    629		xscale = 1 << FP_SHIFT;
    630
    631	if (params->dst_height > 1)
    632		yscale = ((params->src_scan_height - 1) << FP_SHIFT) /
    633			params->dst_height;
    634	else
    635		yscale = 1 << FP_SHIFT;
    636
    637	/*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
    638	xscale_UV = xscale/uv_hscale;
    639	yscale_UV = yscale/uv_vscale;
    640	/* make the Y scale to UV scale ratio an exact multiply */
    641	xscale = xscale_UV * uv_hscale;
    642	yscale = yscale_UV * uv_vscale;
    643	/*} else {
    644	  xscale_UV = 0;
    645	  yscale_UV = 0;
    646	  }*/
    647
    648	if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
    649		scale_changed = true;
    650	overlay->old_xscale = xscale;
    651	overlay->old_yscale = yscale;
    652
    653	iowrite32(((yscale & FRACT_MASK) << 20) |
    654		  ((xscale >> FP_SHIFT)  << 16) |
    655		  ((xscale & FRACT_MASK) << 3),
    656		 &regs->YRGBSCALE);
    657
    658	iowrite32(((yscale_UV & FRACT_MASK) << 20) |
    659		  ((xscale_UV >> FP_SHIFT)  << 16) |
    660		  ((xscale_UV & FRACT_MASK) << 3),
    661		 &regs->UVSCALE);
    662
    663	iowrite32((((yscale    >> FP_SHIFT) << 16) |
    664		   ((yscale_UV >> FP_SHIFT) << 0)),
    665		 &regs->UVSCALEV);
    666
    667	if (scale_changed)
    668		update_polyphase_filter(regs);
    669
    670	return scale_changed;
    671}
    672
    673static void update_colorkey(struct intel_overlay *overlay,
    674			    struct overlay_registers __iomem *regs)
    675{
    676	const struct intel_plane_state *state =
    677		to_intel_plane_state(overlay->crtc->base.primary->state);
    678	u32 key = overlay->color_key;
    679	u32 format = 0;
    680	u32 flags = 0;
    681
    682	if (overlay->color_key_enabled)
    683		flags |= DST_KEY_ENABLE;
    684
    685	if (state->uapi.visible)
    686		format = state->hw.fb->format->format;
    687
    688	switch (format) {
    689	case DRM_FORMAT_C8:
    690		key = RGB8I_TO_COLORKEY(key);
    691		flags |= CLK_RGB24_MASK;
    692		break;
    693	case DRM_FORMAT_XRGB1555:
    694		key = RGB15_TO_COLORKEY(key);
    695		flags |= CLK_RGB15_MASK;
    696		break;
    697	case DRM_FORMAT_RGB565:
    698		key = RGB16_TO_COLORKEY(key);
    699		flags |= CLK_RGB16_MASK;
    700		break;
    701	case DRM_FORMAT_XRGB2101010:
    702	case DRM_FORMAT_XBGR2101010:
    703		key = RGB30_TO_COLORKEY(key);
    704		flags |= CLK_RGB24_MASK;
    705		break;
    706	default:
    707		flags |= CLK_RGB24_MASK;
    708		break;
    709	}
    710
    711	iowrite32(key, &regs->DCLRKV);
    712	iowrite32(flags, &regs->DCLRKM);
    713}
    714
    715static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params)
    716{
    717	u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
    718
    719	if (params->flags & I915_OVERLAY_YUV_PLANAR) {
    720		switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
    721		case I915_OVERLAY_YUV422:
    722			cmd |= OCMD_YUV_422_PLANAR;
    723			break;
    724		case I915_OVERLAY_YUV420:
    725			cmd |= OCMD_YUV_420_PLANAR;
    726			break;
    727		case I915_OVERLAY_YUV411:
    728		case I915_OVERLAY_YUV410:
    729			cmd |= OCMD_YUV_410_PLANAR;
    730			break;
    731		}
    732	} else { /* YUV packed */
    733		switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
    734		case I915_OVERLAY_YUV422:
    735			cmd |= OCMD_YUV_422_PACKED;
    736			break;
    737		case I915_OVERLAY_YUV411:
    738			cmd |= OCMD_YUV_411_PACKED;
    739			break;
    740		}
    741
    742		switch (params->flags & I915_OVERLAY_SWAP_MASK) {
    743		case I915_OVERLAY_NO_SWAP:
    744			break;
    745		case I915_OVERLAY_UV_SWAP:
    746			cmd |= OCMD_UV_SWAP;
    747			break;
    748		case I915_OVERLAY_Y_SWAP:
    749			cmd |= OCMD_Y_SWAP;
    750			break;
    751		case I915_OVERLAY_Y_AND_UV_SWAP:
    752			cmd |= OCMD_Y_AND_UV_SWAP;
    753			break;
    754		}
    755	}
    756
    757	return cmd;
    758}
    759
    760static struct i915_vma *intel_overlay_pin_fb(struct drm_i915_gem_object *new_bo)
    761{
    762	struct i915_gem_ww_ctx ww;
    763	struct i915_vma *vma;
    764	int ret;
    765
    766	i915_gem_ww_ctx_init(&ww, true);
    767retry:
    768	ret = i915_gem_object_lock(new_bo, &ww);
    769	if (!ret) {
    770		vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0,
    771							   NULL, PIN_MAPPABLE);
    772		ret = PTR_ERR_OR_ZERO(vma);
    773	}
    774	if (ret == -EDEADLK) {
    775		ret = i915_gem_ww_ctx_backoff(&ww);
    776		if (!ret)
    777			goto retry;
    778	}
    779	i915_gem_ww_ctx_fini(&ww);
    780	if (ret)
    781		return ERR_PTR(ret);
    782
    783	return vma;
    784}
    785
    786static int intel_overlay_do_put_image(struct intel_overlay *overlay,
    787				      struct drm_i915_gem_object *new_bo,
    788				      struct drm_intel_overlay_put_image *params)
    789{
    790	struct overlay_registers __iomem *regs = overlay->regs;
    791	struct drm_i915_private *dev_priv = overlay->i915;
    792	u32 swidth, swidthsw, sheight, ostride;
    793	enum pipe pipe = overlay->crtc->pipe;
    794	bool scale_changed = false;
    795	struct i915_vma *vma;
    796	int ret, tmp_width;
    797
    798	drm_WARN_ON(&dev_priv->drm,
    799		    !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
    800
    801	ret = intel_overlay_release_old_vid(overlay);
    802	if (ret != 0)
    803		return ret;
    804
    805	atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
    806
    807	vma = intel_overlay_pin_fb(new_bo);
    808	if (IS_ERR(vma)) {
    809		ret = PTR_ERR(vma);
    810		goto out_pin_section;
    811	}
    812
    813	i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB);
    814
    815	if (!overlay->active) {
    816		const struct intel_crtc_state *crtc_state =
    817			overlay->crtc->config;
    818		u32 oconfig = 0;
    819
    820		if (crtc_state->gamma_enable &&
    821		    crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
    822			oconfig |= OCONF_CC_OUT_8BIT;
    823		if (crtc_state->gamma_enable)
    824			oconfig |= OCONF_GAMMA2_ENABLE;
    825		if (DISPLAY_VER(dev_priv) == 4)
    826			oconfig |= OCONF_CSC_MODE_BT709;
    827		oconfig |= pipe == 0 ?
    828			OCONF_PIPE_A : OCONF_PIPE_B;
    829		iowrite32(oconfig, &regs->OCONFIG);
    830
    831		ret = intel_overlay_on(overlay);
    832		if (ret != 0)
    833			goto out_unpin;
    834	}
    835
    836	iowrite32(params->dst_y << 16 | params->dst_x, &regs->DWINPOS);
    837	iowrite32(params->dst_height << 16 | params->dst_width, &regs->DWINSZ);
    838
    839	if (params->flags & I915_OVERLAY_YUV_PACKED)
    840		tmp_width = packed_width_bytes(params->flags,
    841					       params->src_width);
    842	else
    843		tmp_width = params->src_width;
    844
    845	swidth = params->src_width;
    846	swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
    847	sheight = params->src_height;
    848	iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);
    849	ostride = params->stride_Y;
    850
    851	if (params->flags & I915_OVERLAY_YUV_PLANAR) {
    852		int uv_hscale = uv_hsubsampling(params->flags);
    853		int uv_vscale = uv_vsubsampling(params->flags);
    854		u32 tmp_U, tmp_V;
    855
    856		swidth |= (params->src_width / uv_hscale) << 16;
    857		sheight |= (params->src_height / uv_vscale) << 16;
    858
    859		tmp_U = calc_swidthsw(dev_priv, params->offset_U,
    860				      params->src_width / uv_hscale);
    861		tmp_V = calc_swidthsw(dev_priv, params->offset_V,
    862				      params->src_width / uv_hscale);
    863		swidthsw |= max(tmp_U, tmp_V) << 16;
    864
    865		iowrite32(i915_ggtt_offset(vma) + params->offset_U,
    866			  &regs->OBUF_0U);
    867		iowrite32(i915_ggtt_offset(vma) + params->offset_V,
    868			  &regs->OBUF_0V);
    869
    870		ostride |= params->stride_UV << 16;
    871	}
    872
    873	iowrite32(swidth, &regs->SWIDTH);
    874	iowrite32(swidthsw, &regs->SWIDTHSW);
    875	iowrite32(sheight, &regs->SHEIGHT);
    876	iowrite32(ostride, &regs->OSTRIDE);
    877
    878	scale_changed = update_scaling_factors(overlay, regs, params);
    879
    880	update_colorkey(overlay, regs);
    881
    882	iowrite32(overlay_cmd_reg(params), &regs->OCMD);
    883
    884	ret = intel_overlay_continue(overlay, vma, scale_changed);
    885	if (ret)
    886		goto out_unpin;
    887
    888	return 0;
    889
    890out_unpin:
    891	i915_vma_unpin(vma);
    892out_pin_section:
    893	atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
    894
    895	return ret;
    896}
    897
    898int intel_overlay_switch_off(struct intel_overlay *overlay)
    899{
    900	struct drm_i915_private *dev_priv = overlay->i915;
    901	int ret;
    902
    903	drm_WARN_ON(&dev_priv->drm,
    904		    !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
    905
    906	ret = intel_overlay_recover_from_interrupt(overlay);
    907	if (ret != 0)
    908		return ret;
    909
    910	if (!overlay->active)
    911		return 0;
    912
    913	ret = intel_overlay_release_old_vid(overlay);
    914	if (ret != 0)
    915		return ret;
    916
    917	iowrite32(0, &overlay->regs->OCMD);
    918
    919	return intel_overlay_off(overlay);
    920}
    921
    922static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
    923					  struct intel_crtc *crtc)
    924{
    925	if (!crtc->active)
    926		return -EINVAL;
    927
    928	/* can't use the overlay with double wide pipe */
    929	if (crtc->config->double_wide)
    930		return -EINVAL;
    931
    932	return 0;
    933}
    934
    935static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
    936{
    937	struct drm_i915_private *dev_priv = overlay->i915;
    938	u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL);
    939	u32 ratio;
    940
    941	/* XXX: This is not the same logic as in the xorg driver, but more in
    942	 * line with the intel documentation for the i965
    943	 */
    944	if (DISPLAY_VER(dev_priv) >= 4) {
    945		/* on i965 use the PGM reg to read out the autoscaler values */
    946		ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
    947	} else {
    948		if (pfit_control & VERT_AUTO_SCALE)
    949			ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
    950		else
    951			ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
    952		ratio >>= PFIT_VERT_SCALE_SHIFT;
    953	}
    954
    955	overlay->pfit_vscale_ratio = ratio;
    956}
    957
    958static int check_overlay_dst(struct intel_overlay *overlay,
    959			     struct drm_intel_overlay_put_image *rec)
    960{
    961	const struct intel_crtc_state *crtc_state =
    962		overlay->crtc->config;
    963	struct drm_rect req, clipped;
    964
    965	drm_rect_init(&req, rec->dst_x, rec->dst_y,
    966		      rec->dst_width, rec->dst_height);
    967
    968	clipped = req;
    969	drm_rect_intersect(&clipped, &crtc_state->pipe_src);
    970
    971	if (!drm_rect_visible(&clipped) ||
    972	    !drm_rect_equals(&clipped, &req))
    973		return -EINVAL;
    974
    975	return 0;
    976}
    977
    978static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec)
    979{
    980	u32 tmp;
    981
    982	/* downscaling limit is 8.0 */
    983	tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16;
    984	if (tmp > 7)
    985		return -EINVAL;
    986
    987	tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16;
    988	if (tmp > 7)
    989		return -EINVAL;
    990
    991	return 0;
    992}
    993
    994static int check_overlay_src(struct drm_i915_private *dev_priv,
    995			     struct drm_intel_overlay_put_image *rec,
    996			     struct drm_i915_gem_object *new_bo)
    997{
    998	int uv_hscale = uv_hsubsampling(rec->flags);
    999	int uv_vscale = uv_vsubsampling(rec->flags);
   1000	u32 stride_mask;
   1001	int depth;
   1002	u32 tmp;
   1003
   1004	/* check src dimensions */
   1005	if (IS_I845G(dev_priv) || IS_I830(dev_priv)) {
   1006		if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
   1007		    rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
   1008			return -EINVAL;
   1009	} else {
   1010		if (rec->src_height > IMAGE_MAX_HEIGHT ||
   1011		    rec->src_width  > IMAGE_MAX_WIDTH)
   1012			return -EINVAL;
   1013	}
   1014
   1015	/* better safe than sorry, use 4 as the maximal subsampling ratio */
   1016	if (rec->src_height < N_VERT_Y_TAPS*4 ||
   1017	    rec->src_width  < N_HORIZ_Y_TAPS*4)
   1018		return -EINVAL;
   1019
   1020	/* check alignment constraints */
   1021	switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
   1022	case I915_OVERLAY_RGB:
   1023		/* not implemented */
   1024		return -EINVAL;
   1025
   1026	case I915_OVERLAY_YUV_PACKED:
   1027		if (uv_vscale != 1)
   1028			return -EINVAL;
   1029
   1030		depth = packed_depth_bytes(rec->flags);
   1031		if (depth < 0)
   1032			return depth;
   1033
   1034		/* ignore UV planes */
   1035		rec->stride_UV = 0;
   1036		rec->offset_U = 0;
   1037		rec->offset_V = 0;
   1038		/* check pixel alignment */
   1039		if (rec->offset_Y % depth)
   1040			return -EINVAL;
   1041		break;
   1042
   1043	case I915_OVERLAY_YUV_PLANAR:
   1044		if (uv_vscale < 0 || uv_hscale < 0)
   1045			return -EINVAL;
   1046		/* no offset restrictions for planar formats */
   1047		break;
   1048
   1049	default:
   1050		return -EINVAL;
   1051	}
   1052
   1053	if (rec->src_width % uv_hscale)
   1054		return -EINVAL;
   1055
   1056	/* stride checking */
   1057	if (IS_I830(dev_priv) || IS_I845G(dev_priv))
   1058		stride_mask = 255;
   1059	else
   1060		stride_mask = 63;
   1061
   1062	if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
   1063		return -EINVAL;
   1064	if (DISPLAY_VER(dev_priv) == 4 && rec->stride_Y < 512)
   1065		return -EINVAL;
   1066
   1067	tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
   1068		4096 : 8192;
   1069	if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
   1070		return -EINVAL;
   1071
   1072	/* check buffer dimensions */
   1073	switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
   1074	case I915_OVERLAY_RGB:
   1075	case I915_OVERLAY_YUV_PACKED:
   1076		/* always 4 Y values per depth pixels */
   1077		if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
   1078			return -EINVAL;
   1079
   1080		tmp = rec->stride_Y*rec->src_height;
   1081		if (rec->offset_Y + tmp > new_bo->base.size)
   1082			return -EINVAL;
   1083		break;
   1084
   1085	case I915_OVERLAY_YUV_PLANAR:
   1086		if (rec->src_width > rec->stride_Y)
   1087			return -EINVAL;
   1088		if (rec->src_width/uv_hscale > rec->stride_UV)
   1089			return -EINVAL;
   1090
   1091		tmp = rec->stride_Y * rec->src_height;
   1092		if (rec->offset_Y + tmp > new_bo->base.size)
   1093			return -EINVAL;
   1094
   1095		tmp = rec->stride_UV * (rec->src_height / uv_vscale);
   1096		if (rec->offset_U + tmp > new_bo->base.size ||
   1097		    rec->offset_V + tmp > new_bo->base.size)
   1098			return -EINVAL;
   1099		break;
   1100	}
   1101
   1102	return 0;
   1103}
   1104
   1105int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
   1106				  struct drm_file *file_priv)
   1107{
   1108	struct drm_intel_overlay_put_image *params = data;
   1109	struct drm_i915_private *dev_priv = to_i915(dev);
   1110	struct intel_overlay *overlay;
   1111	struct drm_crtc *drmmode_crtc;
   1112	struct intel_crtc *crtc;
   1113	struct drm_i915_gem_object *new_bo;
   1114	int ret;
   1115
   1116	overlay = dev_priv->overlay;
   1117	if (!overlay) {
   1118		drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
   1119		return -ENODEV;
   1120	}
   1121
   1122	if (!(params->flags & I915_OVERLAY_ENABLE)) {
   1123		drm_modeset_lock_all(dev);
   1124		ret = intel_overlay_switch_off(overlay);
   1125		drm_modeset_unlock_all(dev);
   1126
   1127		return ret;
   1128	}
   1129
   1130	drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id);
   1131	if (!drmmode_crtc)
   1132		return -ENOENT;
   1133	crtc = to_intel_crtc(drmmode_crtc);
   1134
   1135	new_bo = i915_gem_object_lookup(file_priv, params->bo_handle);
   1136	if (!new_bo)
   1137		return -ENOENT;
   1138
   1139	drm_modeset_lock_all(dev);
   1140
   1141	if (i915_gem_object_is_tiled(new_bo)) {
   1142		drm_dbg_kms(&dev_priv->drm,
   1143			    "buffer used for overlay image can not be tiled\n");
   1144		ret = -EINVAL;
   1145		goto out_unlock;
   1146	}
   1147
   1148	ret = intel_overlay_recover_from_interrupt(overlay);
   1149	if (ret != 0)
   1150		goto out_unlock;
   1151
   1152	if (overlay->crtc != crtc) {
   1153		ret = intel_overlay_switch_off(overlay);
   1154		if (ret != 0)
   1155			goto out_unlock;
   1156
   1157		ret = check_overlay_possible_on_crtc(overlay, crtc);
   1158		if (ret != 0)
   1159			goto out_unlock;
   1160
   1161		overlay->crtc = crtc;
   1162		crtc->overlay = overlay;
   1163
   1164		/* line too wide, i.e. one-line-mode */
   1165		if (drm_rect_width(&crtc->config->pipe_src) > 1024 &&
   1166		    crtc->config->gmch_pfit.control & PFIT_ENABLE) {
   1167			overlay->pfit_active = true;
   1168			update_pfit_vscale_ratio(overlay);
   1169		} else
   1170			overlay->pfit_active = false;
   1171	}
   1172
   1173	ret = check_overlay_dst(overlay, params);
   1174	if (ret != 0)
   1175		goto out_unlock;
   1176
   1177	if (overlay->pfit_active) {
   1178		params->dst_y = (((u32)params->dst_y << 12) /
   1179				 overlay->pfit_vscale_ratio);
   1180		/* shifting right rounds downwards, so add 1 */
   1181		params->dst_height = (((u32)params->dst_height << 12) /
   1182				 overlay->pfit_vscale_ratio) + 1;
   1183	}
   1184
   1185	if (params->src_scan_height > params->src_height ||
   1186	    params->src_scan_width > params->src_width) {
   1187		ret = -EINVAL;
   1188		goto out_unlock;
   1189	}
   1190
   1191	ret = check_overlay_src(dev_priv, params, new_bo);
   1192	if (ret != 0)
   1193		goto out_unlock;
   1194
   1195	/* Check scaling after src size to prevent a divide-by-zero. */
   1196	ret = check_overlay_scaling(params);
   1197	if (ret != 0)
   1198		goto out_unlock;
   1199
   1200	ret = intel_overlay_do_put_image(overlay, new_bo, params);
   1201	if (ret != 0)
   1202		goto out_unlock;
   1203
   1204	drm_modeset_unlock_all(dev);
   1205	i915_gem_object_put(new_bo);
   1206
   1207	return 0;
   1208
   1209out_unlock:
   1210	drm_modeset_unlock_all(dev);
   1211	i915_gem_object_put(new_bo);
   1212
   1213	return ret;
   1214}
   1215
   1216static void update_reg_attrs(struct intel_overlay *overlay,
   1217			     struct overlay_registers __iomem *regs)
   1218{
   1219	iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
   1220		  &regs->OCLRC0);
   1221	iowrite32(overlay->saturation, &regs->OCLRC1);
   1222}
   1223
   1224static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
   1225{
   1226	int i;
   1227
   1228	if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
   1229		return false;
   1230
   1231	for (i = 0; i < 3; i++) {
   1232		if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
   1233			return false;
   1234	}
   1235
   1236	return true;
   1237}
   1238
   1239static bool check_gamma5_errata(u32 gamma5)
   1240{
   1241	int i;
   1242
   1243	for (i = 0; i < 3; i++) {
   1244		if (((gamma5 >> i*8) & 0xff) == 0x80)
   1245			return false;
   1246	}
   1247
   1248	return true;
   1249}
   1250
   1251static int check_gamma(struct drm_intel_overlay_attrs *attrs)
   1252{
   1253	if (!check_gamma_bounds(0, attrs->gamma0) ||
   1254	    !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
   1255	    !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
   1256	    !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
   1257	    !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
   1258	    !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
   1259	    !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
   1260		return -EINVAL;
   1261
   1262	if (!check_gamma5_errata(attrs->gamma5))
   1263		return -EINVAL;
   1264
   1265	return 0;
   1266}
   1267
   1268int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
   1269			      struct drm_file *file_priv)
   1270{
   1271	struct drm_intel_overlay_attrs *attrs = data;
   1272	struct drm_i915_private *dev_priv = to_i915(dev);
   1273	struct intel_overlay *overlay;
   1274	int ret;
   1275
   1276	overlay = dev_priv->overlay;
   1277	if (!overlay) {
   1278		drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
   1279		return -ENODEV;
   1280	}
   1281
   1282	drm_modeset_lock_all(dev);
   1283
   1284	ret = -EINVAL;
   1285	if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
   1286		attrs->color_key  = overlay->color_key;
   1287		attrs->brightness = overlay->brightness;
   1288		attrs->contrast   = overlay->contrast;
   1289		attrs->saturation = overlay->saturation;
   1290
   1291		if (DISPLAY_VER(dev_priv) != 2) {
   1292			attrs->gamma0 = intel_de_read(dev_priv, OGAMC0);
   1293			attrs->gamma1 = intel_de_read(dev_priv, OGAMC1);
   1294			attrs->gamma2 = intel_de_read(dev_priv, OGAMC2);
   1295			attrs->gamma3 = intel_de_read(dev_priv, OGAMC3);
   1296			attrs->gamma4 = intel_de_read(dev_priv, OGAMC4);
   1297			attrs->gamma5 = intel_de_read(dev_priv, OGAMC5);
   1298		}
   1299	} else {
   1300		if (attrs->brightness < -128 || attrs->brightness > 127)
   1301			goto out_unlock;
   1302		if (attrs->contrast > 255)
   1303			goto out_unlock;
   1304		if (attrs->saturation > 1023)
   1305			goto out_unlock;
   1306
   1307		overlay->color_key  = attrs->color_key;
   1308		overlay->brightness = attrs->brightness;
   1309		overlay->contrast   = attrs->contrast;
   1310		overlay->saturation = attrs->saturation;
   1311
   1312		update_reg_attrs(overlay, overlay->regs);
   1313
   1314		if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
   1315			if (DISPLAY_VER(dev_priv) == 2)
   1316				goto out_unlock;
   1317
   1318			if (overlay->active) {
   1319				ret = -EBUSY;
   1320				goto out_unlock;
   1321			}
   1322
   1323			ret = check_gamma(attrs);
   1324			if (ret)
   1325				goto out_unlock;
   1326
   1327			intel_de_write(dev_priv, OGAMC0, attrs->gamma0);
   1328			intel_de_write(dev_priv, OGAMC1, attrs->gamma1);
   1329			intel_de_write(dev_priv, OGAMC2, attrs->gamma2);
   1330			intel_de_write(dev_priv, OGAMC3, attrs->gamma3);
   1331			intel_de_write(dev_priv, OGAMC4, attrs->gamma4);
   1332			intel_de_write(dev_priv, OGAMC5, attrs->gamma5);
   1333		}
   1334	}
   1335	overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
   1336
   1337	ret = 0;
   1338out_unlock:
   1339	drm_modeset_unlock_all(dev);
   1340
   1341	return ret;
   1342}
   1343
   1344static int get_registers(struct intel_overlay *overlay, bool use_phys)
   1345{
   1346	struct drm_i915_private *i915 = overlay->i915;
   1347	struct drm_i915_gem_object *obj;
   1348	struct i915_vma *vma;
   1349	int err;
   1350
   1351	obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
   1352	if (IS_ERR(obj))
   1353		obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
   1354	if (IS_ERR(obj))
   1355		return PTR_ERR(obj);
   1356
   1357	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
   1358	if (IS_ERR(vma)) {
   1359		err = PTR_ERR(vma);
   1360		goto err_put_bo;
   1361	}
   1362
   1363	if (use_phys)
   1364		overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl);
   1365	else
   1366		overlay->flip_addr = i915_ggtt_offset(vma);
   1367	overlay->regs = i915_vma_pin_iomap(vma);
   1368	i915_vma_unpin(vma);
   1369
   1370	if (IS_ERR(overlay->regs)) {
   1371		err = PTR_ERR(overlay->regs);
   1372		goto err_put_bo;
   1373	}
   1374
   1375	overlay->reg_bo = obj;
   1376	return 0;
   1377
   1378err_put_bo:
   1379	i915_gem_object_put(obj);
   1380	return err;
   1381}
   1382
   1383void intel_overlay_setup(struct drm_i915_private *dev_priv)
   1384{
   1385	struct intel_overlay *overlay;
   1386	struct intel_engine_cs *engine;
   1387	int ret;
   1388
   1389	if (!HAS_OVERLAY(dev_priv))
   1390		return;
   1391
   1392	engine = to_gt(dev_priv)->engine[RCS0];
   1393	if (!engine || !engine->kernel_context)
   1394		return;
   1395
   1396	overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
   1397	if (!overlay)
   1398		return;
   1399
   1400	overlay->i915 = dev_priv;
   1401	overlay->context = engine->kernel_context;
   1402	GEM_BUG_ON(!overlay->context);
   1403
   1404	overlay->color_key = 0x0101fe;
   1405	overlay->color_key_enabled = true;
   1406	overlay->brightness = -19;
   1407	overlay->contrast = 75;
   1408	overlay->saturation = 146;
   1409
   1410	i915_active_init(&overlay->last_flip,
   1411			 NULL, intel_overlay_last_flip_retire, 0);
   1412
   1413	ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv));
   1414	if (ret)
   1415		goto out_free;
   1416
   1417	memset_io(overlay->regs, 0, sizeof(struct overlay_registers));
   1418	update_polyphase_filter(overlay->regs);
   1419	update_reg_attrs(overlay, overlay->regs);
   1420
   1421	dev_priv->overlay = overlay;
   1422	drm_info(&dev_priv->drm, "Initialized overlay support.\n");
   1423	return;
   1424
   1425out_free:
   1426	kfree(overlay);
   1427}
   1428
   1429void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
   1430{
   1431	struct intel_overlay *overlay;
   1432
   1433	overlay = fetch_and_zero(&dev_priv->overlay);
   1434	if (!overlay)
   1435		return;
   1436
   1437	/*
   1438	 * The bo's should be free'd by the generic code already.
   1439	 * Furthermore modesetting teardown happens beforehand so the
   1440	 * hardware should be off already.
   1441	 */
   1442	drm_WARN_ON(&dev_priv->drm, overlay->active);
   1443
   1444	i915_gem_object_put(overlay->reg_bo);
   1445	i915_active_fini(&overlay->last_flip);
   1446
   1447	kfree(overlay);
   1448}
   1449
   1450#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
   1451
   1452struct intel_overlay_error_state {
   1453	struct overlay_registers regs;
   1454	unsigned long base;
   1455	u32 dovsta;
   1456	u32 isr;
   1457};
   1458
   1459struct intel_overlay_error_state *
   1460intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
   1461{
   1462	struct intel_overlay *overlay = dev_priv->overlay;
   1463	struct intel_overlay_error_state *error;
   1464
   1465	if (!overlay || !overlay->active)
   1466		return NULL;
   1467
   1468	error = kmalloc(sizeof(*error), GFP_ATOMIC);
   1469	if (error == NULL)
   1470		return NULL;
   1471
   1472	error->dovsta = intel_de_read(dev_priv, DOVSTA);
   1473	error->isr = intel_de_read(dev_priv, GEN2_ISR);
   1474	error->base = overlay->flip_addr;
   1475
   1476	memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));
   1477
   1478	return error;
   1479}
   1480
   1481void
   1482intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
   1483				struct intel_overlay_error_state *error)
   1484{
   1485	i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
   1486			  error->dovsta, error->isr);
   1487	i915_error_printf(m, "  Register file at 0x%08lx:\n",
   1488			  error->base);
   1489
   1490#define P(x) i915_error_printf(m, "    " #x ":	0x%08x\n", error->regs.x)
   1491	P(OBUF_0Y);
   1492	P(OBUF_1Y);
   1493	P(OBUF_0U);
   1494	P(OBUF_0V);
   1495	P(OBUF_1U);
   1496	P(OBUF_1V);
   1497	P(OSTRIDE);
   1498	P(YRGB_VPH);
   1499	P(UV_VPH);
   1500	P(HORZ_PH);
   1501	P(INIT_PHS);
   1502	P(DWINPOS);
   1503	P(DWINSZ);
   1504	P(SWIDTH);
   1505	P(SWIDTHSW);
   1506	P(SHEIGHT);
   1507	P(YRGBSCALE);
   1508	P(UVSCALE);
   1509	P(OCLRC0);
   1510	P(OCLRC1);
   1511	P(DCLRKV);
   1512	P(DCLRKM);
   1513	P(SCLRKVH);
   1514	P(SCLRKVL);
   1515	P(SCLRKEN);
   1516	P(OCONFIG);
   1517	P(OCMD);
   1518	P(OSTART_0Y);
   1519	P(OSTART_1Y);
   1520	P(OSTART_0U);
   1521	P(OSTART_0V);
   1522	P(OSTART_1U);
   1523	P(OSTART_1V);
   1524	P(OTILEOFF_0Y);
   1525	P(OTILEOFF_1Y);
   1526	P(OTILEOFF_0U);
   1527	P(OTILEOFF_0V);
   1528	P(OTILEOFF_1U);
   1529	P(OTILEOFF_1V);
   1530	P(FASTHSCALE);
   1531	P(UVSCALEV);
   1532#undef P
   1533}
   1534
   1535#endif