cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intel_snps_phy.h (1160B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Copyright © 2019 Intel Corporation
      4 */
      5
      6#ifndef __INTEL_SNPS_PHY_H__
      7#define __INTEL_SNPS_PHY_H__
      8
      9#include <linux/types.h>
     10
     11struct drm_i915_private;
     12struct intel_encoder;
     13struct intel_crtc_state;
     14struct intel_mpllb_state;
     15enum phy;
     16
     17void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv);
     18void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv,
     19					   enum phy phy, bool enable);
     20
     21int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
     22			   struct intel_encoder *encoder);
     23void intel_mpllb_enable(struct intel_encoder *encoder,
     24			const struct intel_crtc_state *crtc_state);
     25void intel_mpllb_disable(struct intel_encoder *encoder);
     26void intel_mpllb_readout_hw_state(struct intel_encoder *encoder,
     27				  struct intel_mpllb_state *pll_state);
     28int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,
     29				const struct intel_mpllb_state *pll_state);
     30
     31int intel_snps_phy_check_hdmi_link_rate(int clock);
     32void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
     33				      const struct intel_crtc_state *crtc_state);
     34
     35#endif /* __INTEL_SNPS_PHY_H__ */