intel_vbt_defs.h (24788B)
1/* 2 * Copyright © 2006-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28/* 29 * This information is private to VBT parsing in intel_bios.c. 30 * 31 * Please do NOT include anywhere else. 32 */ 33#ifndef _INTEL_BIOS_PRIVATE 34#error "intel_vbt_defs.h is private to intel_bios.c" 35#endif 36 37#ifndef _INTEL_VBT_DEFS_H_ 38#define _INTEL_VBT_DEFS_H_ 39 40#include "intel_bios.h" 41 42/** 43 * struct vbt_header - VBT Header structure 44 * @signature: VBT signature, always starts with "$VBT" 45 * @version: Version of this structure 46 * @header_size: Size of this structure 47 * @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks) 48 * @vbt_checksum: Checksum 49 * @reserved0: Reserved 50 * @bdb_offset: Offset of &struct bdb_header from beginning of VBT 51 * @aim_offset: Offsets of add-in data blocks from beginning of VBT 52 */ 53struct vbt_header { 54 u8 signature[20]; 55 u16 version; 56 u16 header_size; 57 u16 vbt_size; 58 u8 vbt_checksum; 59 u8 reserved0; 60 u32 bdb_offset; 61 u32 aim_offset[4]; 62} __packed; 63 64/** 65 * struct bdb_header - BDB Header structure 66 * @signature: BDB signature "BIOS_DATA_BLOCK" 67 * @version: Version of the data block definitions 68 * @header_size: Size of this structure 69 * @bdb_size: Size of BDB (BDB Header and data blocks) 70 */ 71struct bdb_header { 72 u8 signature[16]; 73 u16 version; 74 u16 header_size; 75 u16 bdb_size; 76} __packed; 77 78/* 79 * There are several types of BIOS data blocks (BDBs), each block has 80 * an ID and size in the first 3 bytes (ID in first, size in next 2). 81 * Known types are listed below. 82 */ 83enum bdb_block_id { 84 BDB_GENERAL_FEATURES = 1, 85 BDB_GENERAL_DEFINITIONS = 2, 86 BDB_OLD_TOGGLE_LIST = 3, 87 BDB_MODE_SUPPORT_LIST = 4, 88 BDB_GENERIC_MODE_TABLE = 5, 89 BDB_EXT_MMIO_REGS = 6, 90 BDB_SWF_IO = 7, 91 BDB_SWF_MMIO = 8, 92 BDB_PSR = 9, 93 BDB_MODE_REMOVAL_TABLE = 10, 94 BDB_CHILD_DEVICE_TABLE = 11, 95 BDB_DRIVER_FEATURES = 12, 96 BDB_DRIVER_PERSISTENCE = 13, 97 BDB_EXT_TABLE_PTRS = 14, 98 BDB_DOT_CLOCK_OVERRIDE = 15, 99 BDB_DISPLAY_SELECT = 16, 100 BDB_DRIVER_ROTATION = 18, 101 BDB_DISPLAY_REMOVE = 19, 102 BDB_OEM_CUSTOM = 20, 103 BDB_EFP_LIST = 21, /* workarounds for VGA hsync/vsync */ 104 BDB_SDVO_LVDS_OPTIONS = 22, 105 BDB_SDVO_PANEL_DTDS = 23, 106 BDB_SDVO_LVDS_PNP_IDS = 24, 107 BDB_SDVO_LVDS_POWER_SEQ = 25, 108 BDB_TV_OPTIONS = 26, 109 BDB_EDP = 27, 110 BDB_LVDS_OPTIONS = 40, 111 BDB_LVDS_LFP_DATA_PTRS = 41, 112 BDB_LVDS_LFP_DATA = 42, 113 BDB_LVDS_BACKLIGHT = 43, 114 BDB_LFP_POWER = 44, 115 BDB_MIPI_CONFIG = 52, 116 BDB_MIPI_SEQUENCE = 53, 117 BDB_COMPRESSION_PARAMETERS = 56, 118 BDB_GENERIC_DTD = 58, 119 BDB_SKIP = 254, /* VBIOS private block, ignore */ 120}; 121 122/* 123 * Block 1 - General Bit Definitions 124 */ 125 126struct bdb_general_features { 127 /* bits 1 */ 128 u8 panel_fitting:2; 129 u8 flexaim:1; 130 u8 msg_enable:1; 131 u8 clear_screen:3; 132 u8 color_flip:1; 133 134 /* bits 2 */ 135 u8 download_ext_vbt:1; 136 u8 enable_ssc:1; 137 u8 ssc_freq:1; 138 u8 enable_lfp_on_override:1; 139 u8 disable_ssc_ddt:1; 140 u8 underscan_vga_timings:1; 141 u8 display_clock_mode:1; 142 u8 vbios_hotplug_support:1; 143 144 /* bits 3 */ 145 u8 disable_smooth_vision:1; 146 u8 single_dvi:1; 147 u8 rotate_180:1; /* 181 */ 148 u8 fdi_rx_polarity_inverted:1; 149 u8 vbios_extended_mode:1; /* 160 */ 150 u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160 */ 151 u8 panel_best_fit_timing:1; /* 160 */ 152 u8 ignore_strap_state:1; /* 160 */ 153 154 /* bits 4 */ 155 u8 legacy_monitor_detect; 156 157 /* bits 5 */ 158 u8 int_crt_support:1; 159 u8 int_tv_support:1; 160 u8 int_efp_support:1; 161 u8 dp_ssc_enable:1; /* PCH attached eDP supports SSC */ 162 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ 163 u8 dp_ssc_dongle_supported:1; 164 u8 rsvd11:2; /* finish byte */ 165 166 /* bits 6 */ 167 u8 tc_hpd_retry_timeout:7; /* 242 */ 168 u8 rsvd12:1; 169 170 /* bits 7 */ 171 u8 afc_startup_config:2;/* 249 */ 172 u8 rsvd13:6; 173} __packed; 174 175/* 176 * Block 2 - General Bytes Definition 177 */ 178 179/* pre-915 */ 180#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ 181#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ 182#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ 183#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ 184 185/* Pre 915 */ 186#define DEVICE_TYPE_NONE 0x00 187#define DEVICE_TYPE_CRT 0x01 188#define DEVICE_TYPE_TV 0x09 189#define DEVICE_TYPE_EFP 0x12 190#define DEVICE_TYPE_LFP 0x22 191/* On 915+ */ 192#define DEVICE_TYPE_CRT_DPMS 0x6001 193#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 194#define DEVICE_TYPE_TV_COMPOSITE 0x0209 195#define DEVICE_TYPE_TV_MACROVISION 0x0289 196#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c 197#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 198#define DEVICE_TYPE_TV_SCART 0x0209 199#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 200#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 201#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 202#define DEVICE_TYPE_EFP_DVI_I 0x6053 203#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 204#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 205#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 206#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 207#define DEVICE_TYPE_LFP_PANELLINK 0x5012 208#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 209#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 210#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 211#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 212 213/* Add the device class for LFP, TV, HDMI */ 214#define DEVICE_TYPE_INT_LFP 0x1022 215#define DEVICE_TYPE_INT_TV 0x1009 216#define DEVICE_TYPE_HDMI 0x60D2 217#define DEVICE_TYPE_DP 0x68C6 218#define DEVICE_TYPE_DP_DUAL_MODE 0x60D6 219#define DEVICE_TYPE_eDP 0x78C6 220 221#define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) 222#define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) 223#define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) 224#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) 225#define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) 226#define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) 227#define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) 228#define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) 229#define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) 230#define DEVICE_TYPE_LVDS_SIGNALING (1 << 5) 231#define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) 232#define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) 233#define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) 234#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) 235#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) 236 237#define DEVICE_CFG_NONE 0x00 238#define DEVICE_CFG_12BIT_DVOB 0x01 239#define DEVICE_CFG_12BIT_DVOC 0x02 240#define DEVICE_CFG_24BIT_DVOBC 0x09 241#define DEVICE_CFG_24BIT_DVOCB 0x0a 242#define DEVICE_CFG_DUAL_DVOB 0x11 243#define DEVICE_CFG_DUAL_DVOC 0x12 244#define DEVICE_CFG_DUAL_DVOBC 0x13 245#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 246#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a 247 248#define DEVICE_WIRE_NONE 0x00 249#define DEVICE_WIRE_DVOB 0x01 250#define DEVICE_WIRE_DVOC 0x02 251#define DEVICE_WIRE_DVOBC 0x03 252#define DEVICE_WIRE_DVOBB 0x05 253#define DEVICE_WIRE_DVOCC 0x06 254#define DEVICE_WIRE_DVOB_MASTER 0x0d 255#define DEVICE_WIRE_DVOC_MASTER 0x0e 256 257/* dvo_port pre BDB 155 */ 258#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ 259#define DEVICE_PORT_DVOB 0x01 260#define DEVICE_PORT_DVOC 0x02 261 262/* dvo_port BDB 155+ */ 263#define DVO_PORT_HDMIA 0 264#define DVO_PORT_HDMIB 1 265#define DVO_PORT_HDMIC 2 266#define DVO_PORT_HDMID 3 267#define DVO_PORT_LVDS 4 268#define DVO_PORT_TV 5 269#define DVO_PORT_CRT 6 270#define DVO_PORT_DPB 7 271#define DVO_PORT_DPC 8 272#define DVO_PORT_DPD 9 273#define DVO_PORT_DPA 10 274#define DVO_PORT_DPE 11 /* 193 */ 275#define DVO_PORT_HDMIE 12 /* 193 */ 276#define DVO_PORT_DPF 13 /* N/A */ 277#define DVO_PORT_HDMIF 14 /* N/A */ 278#define DVO_PORT_DPG 15 /* 217 */ 279#define DVO_PORT_HDMIG 16 /* 217 */ 280#define DVO_PORT_DPH 17 /* 217 */ 281#define DVO_PORT_HDMIH 18 /* 217 */ 282#define DVO_PORT_DPI 19 /* 217 */ 283#define DVO_PORT_HDMII 20 /* 217 */ 284#define DVO_PORT_MIPIA 21 /* 171 */ 285#define DVO_PORT_MIPIB 22 /* 171 */ 286#define DVO_PORT_MIPIC 23 /* 171 */ 287#define DVO_PORT_MIPID 24 /* 171 */ 288 289#define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204 */ 290#define HDMI_MAX_DATA_RATE_297 1 /* 204 */ 291#define HDMI_MAX_DATA_RATE_165 2 /* 204 */ 292#define HDMI_MAX_DATA_RATE_594 3 /* 249 */ 293#define HDMI_MAX_DATA_RATE_340 4 /* 249 */ 294#define HDMI_MAX_DATA_RATE_300 5 /* 249 */ 295 296#define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33 297 298/* DDC Bus DDI Type 155+ */ 299enum vbt_gmbus_ddi { 300 DDC_BUS_DDI_B = 0x1, 301 DDC_BUS_DDI_C, 302 DDC_BUS_DDI_D, 303 DDC_BUS_DDI_F, 304 ICL_DDC_BUS_DDI_A = 0x1, 305 ICL_DDC_BUS_DDI_B, 306 TGL_DDC_BUS_DDI_C, 307 RKL_DDC_BUS_DDI_D = 0x3, 308 RKL_DDC_BUS_DDI_E, 309 ICL_DDC_BUS_PORT_1 = 0x4, 310 ICL_DDC_BUS_PORT_2, 311 ICL_DDC_BUS_PORT_3, 312 ICL_DDC_BUS_PORT_4, 313 TGL_DDC_BUS_PORT_5, 314 TGL_DDC_BUS_PORT_6, 315 ADLS_DDC_BUS_PORT_TC1 = 0x2, 316 ADLS_DDC_BUS_PORT_TC2, 317 ADLS_DDC_BUS_PORT_TC3, 318 ADLS_DDC_BUS_PORT_TC4, 319 ADLP_DDC_BUS_PORT_TC1 = 0x3, 320 ADLP_DDC_BUS_PORT_TC2, 321 ADLP_DDC_BUS_PORT_TC3, 322 ADLP_DDC_BUS_PORT_TC4 323 324}; 325 326#define DP_AUX_A 0x40 327#define DP_AUX_B 0x10 328#define DP_AUX_C 0x20 329#define DP_AUX_D 0x30 330#define DP_AUX_E 0x50 331#define DP_AUX_F 0x60 332#define DP_AUX_G 0x70 333#define DP_AUX_H 0x80 334#define DP_AUX_I 0x90 335 336/* DP max link rate 216+ */ 337#define BDB_216_VBT_DP_MAX_LINK_RATE_HBR3 0 338#define BDB_216_VBT_DP_MAX_LINK_RATE_HBR2 1 339#define BDB_216_VBT_DP_MAX_LINK_RATE_HBR 2 340#define BDB_216_VBT_DP_MAX_LINK_RATE_LBR 3 341 342/* DP max link rate 230+ */ 343#define BDB_230_VBT_DP_MAX_LINK_RATE_DEF 0 344#define BDB_230_VBT_DP_MAX_LINK_RATE_LBR 1 345#define BDB_230_VBT_DP_MAX_LINK_RATE_HBR 2 346#define BDB_230_VBT_DP_MAX_LINK_RATE_HBR2 3 347#define BDB_230_VBT_DP_MAX_LINK_RATE_HBR3 4 348#define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR10 5 349#define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR13P5 6 350#define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR20 7 351 352/* 353 * The child device config, aka the display device data structure, provides a 354 * description of a port and its configuration on the platform. 355 * 356 * The child device config size has been increased, and fields have been added 357 * and their meaning has changed over time. Care must be taken when accessing 358 * basically any of the fields to ensure the correct interpretation for the BDB 359 * version in question. 360 * 361 * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve 362 * space for the full structure below, and initialize the tail not actually 363 * present in VBT to zeros. Accessing those fields is fine, as long as the 364 * default zero is taken into account, again according to the BDB version. 365 * 366 * BDB versions 155 and below are considered legacy, and version 155 seems to be 367 * a baseline for some of the VBT documentation. When adding new fields, please 368 * include the BDB version when the field was added, if it's above that. 369 */ 370struct child_device_config { 371 u16 handle; 372 u16 device_type; /* See DEVICE_TYPE_* above */ 373 374 union { 375 u8 device_id[10]; /* ascii string */ 376 struct { 377 u8 i2c_speed; 378 u8 dp_onboard_redriver; /* 158 */ 379 u8 dp_ondock_redriver; /* 158 */ 380 u8 hdmi_level_shifter_value:5; /* 169 */ 381 u8 hdmi_max_data_rate:3; /* 204 */ 382 u16 dtd_buf_ptr; /* 161 */ 383 u8 edidless_efp:1; /* 161 */ 384 u8 compression_enable:1; /* 198 */ 385 u8 compression_method_cps:1; /* 198 */ 386 u8 ganged_edp:1; /* 202 */ 387 u8 reserved0:4; 388 u8 compression_structure_index:4; /* 198 */ 389 u8 reserved1:4; 390 u8 slave_port; /* 202 */ 391 u8 reserved2; 392 } __packed; 393 } __packed; 394 395 u16 addin_offset; 396 u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */ 397 u8 i2c_pin; 398 u8 slave_addr; 399 u8 ddc_pin; 400 u16 edid_ptr; 401 u8 dvo_cfg; /* See DEVICE_CFG_* above */ 402 403 union { 404 struct { 405 u8 dvo2_port; 406 u8 i2c2_pin; 407 u8 slave2_addr; 408 u8 ddc2_pin; 409 } __packed; 410 struct { 411 u8 efp_routed:1; /* 158 */ 412 u8 lane_reversal:1; /* 184 */ 413 u8 lspcon:1; /* 192 */ 414 u8 iboost:1; /* 196 */ 415 u8 hpd_invert:1; /* 196 */ 416 u8 use_vbt_vswing:1; /* 218 */ 417 u8 flag_reserved:2; 418 u8 hdmi_support:1; /* 158 */ 419 u8 dp_support:1; /* 158 */ 420 u8 tmds_support:1; /* 158 */ 421 u8 support_reserved:5; 422 u8 aux_channel; 423 u8 dongle_detect; 424 } __packed; 425 } __packed; 426 427 u8 pipe_cap:2; 428 u8 sdvo_stall:1; /* 158 */ 429 u8 hpd_status:2; 430 u8 integrated_encoder:1; 431 u8 capabilities_reserved:2; 432 u8 dvo_wiring; /* See DEVICE_WIRE_* above */ 433 434 union { 435 u8 dvo2_wiring; 436 u8 mipi_bridge_type; /* 171 */ 437 } __packed; 438 439 u16 extended_type; 440 u8 dvo_function; 441 u8 dp_usb_type_c:1; /* 195 */ 442 u8 tbt:1; /* 209 */ 443 u8 flags2_reserved:2; /* 195 */ 444 u8 dp_port_trace_length:4; /* 209 */ 445 u8 dp_gpio_index; /* 195 */ 446 u16 dp_gpio_pin_num; /* 195 */ 447 u8 dp_iboost_level:4; /* 196 */ 448 u8 hdmi_iboost_level:4; /* 196 */ 449 u8 dp_max_link_rate:3; /* 216/230 GLK+ */ 450 u8 dp_max_link_rate_reserved:5; /* 216/230 */ 451} __packed; 452 453struct bdb_general_definitions { 454 /* DDC GPIO */ 455 u8 crt_ddc_gmbus_pin; 456 457 /* DPMS bits */ 458 u8 dpms_acpi:1; 459 u8 skip_boot_crt_detect:1; 460 u8 dpms_aim:1; 461 u8 rsvd1:5; /* finish byte */ 462 463 /* boot device bits */ 464 u8 boot_display[2]; 465 u8 child_dev_size; 466 467 /* 468 * Device info: 469 * If TV is present, it'll be at devices[0]. 470 * LVDS will be next, either devices[0] or [1], if present. 471 * On some platforms the number of device is 6. But could be as few as 472 * 4 if both TV and LVDS are missing. 473 * And the device num is related with the size of general definition 474 * block. It is obtained by using the following formula: 475 * number = (block_size - sizeof(bdb_general_definitions))/ 476 * defs->child_dev_size; 477 */ 478 u8 devices[]; 479} __packed; 480 481/* 482 * Block 9 - SRD Feature Block 483 */ 484 485struct psr_table { 486 /* Feature bits */ 487 u8 full_link:1; 488 u8 require_aux_to_wakeup:1; 489 u8 feature_bits_rsvd:6; 490 491 /* Wait times */ 492 u8 idle_frames:4; 493 u8 lines_to_wait:3; 494 u8 wait_times_rsvd:1; 495 496 /* TP wake up time in multiple of 100 */ 497 u16 tp1_wakeup_time; 498 u16 tp2_tp3_wakeup_time; 499} __packed; 500 501struct bdb_psr { 502 struct psr_table psr_table[16]; 503 504 /* PSR2 TP2/TP3 wakeup time for 16 panels */ 505 u32 psr2_tp2_tp3_wakeup_time; 506} __packed; 507 508/* 509 * Block 12 - Driver Features Data Block 510 */ 511 512#define BDB_DRIVER_FEATURE_NO_LVDS 0 513#define BDB_DRIVER_FEATURE_INT_LVDS 1 514#define BDB_DRIVER_FEATURE_SDVO_LVDS 2 515#define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3 516 517struct bdb_driver_features { 518 u8 boot_dev_algorithm:1; 519 u8 block_display_switch:1; 520 u8 allow_display_switch:1; 521 u8 hotplug_dvo:1; 522 u8 dual_view_zoom:1; 523 u8 int15h_hook:1; 524 u8 sprite_in_clone:1; 525 u8 primary_lfp_id:1; 526 527 u16 boot_mode_x; 528 u16 boot_mode_y; 529 u8 boot_mode_bpp; 530 u8 boot_mode_refresh; 531 532 u16 enable_lfp_primary:1; 533 u16 selective_mode_pruning:1; 534 u16 dual_frequency:1; 535 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ 536 u16 nt_clone_support:1; 537 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ 538 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ 539 u16 cui_aspect_scaling:1; 540 u16 preserve_aspect_ratio:1; 541 u16 sdvo_device_power_down:1; 542 u16 crt_hotplug:1; 543 u16 lvds_config:2; 544 u16 tv_hotplug:1; 545 u16 hdmi_config:2; 546 547 u8 static_display:1; 548 u8 reserved2:7; 549 u16 legacy_crt_max_x; 550 u16 legacy_crt_max_y; 551 u8 legacy_crt_max_refresh; 552 553 u8 hdmi_termination; 554 u8 custom_vbt_version; 555 /* Driver features data block */ 556 u16 rmpm_enabled:1; 557 u16 s2ddt_enabled:1; 558 u16 dpst_enabled:1; 559 u16 bltclt_enabled:1; 560 u16 adb_enabled:1; 561 u16 drrs_enabled:1; 562 u16 grs_enabled:1; 563 u16 gpmt_enabled:1; 564 u16 tbt_enabled:1; 565 u16 psr_enabled:1; 566 u16 ips_enabled:1; 567 u16 reserved3:4; 568 u16 pc_feature_valid:1; 569} __packed; 570 571/* 572 * Block 22 - SDVO LVDS General Options 573 */ 574 575struct bdb_sdvo_lvds_options { 576 u8 panel_backlight; 577 u8 h40_set_panel_type; 578 u8 panel_type; 579 u8 ssc_clk_freq; 580 u16 als_low_trip; 581 u16 als_high_trip; 582 u8 sclalarcoeff_tab_row_num; 583 u8 sclalarcoeff_tab_row_size; 584 u8 coefficient[8]; 585 u8 panel_misc_bits_1; 586 u8 panel_misc_bits_2; 587 u8 panel_misc_bits_3; 588 u8 panel_misc_bits_4; 589} __packed; 590 591/* 592 * Block 23 - SDVO LVDS Panel DTDs 593 */ 594 595struct lvds_dvo_timing { 596 u16 clock; /**< In 10khz */ 597 u8 hactive_lo; 598 u8 hblank_lo; 599 u8 hblank_hi:4; 600 u8 hactive_hi:4; 601 u8 vactive_lo; 602 u8 vblank_lo; 603 u8 vblank_hi:4; 604 u8 vactive_hi:4; 605 u8 hsync_off_lo; 606 u8 hsync_pulse_width_lo; 607 u8 vsync_pulse_width_lo:4; 608 u8 vsync_off_lo:4; 609 u8 vsync_pulse_width_hi:2; 610 u8 vsync_off_hi:2; 611 u8 hsync_pulse_width_hi:2; 612 u8 hsync_off_hi:2; 613 u8 himage_lo; 614 u8 vimage_lo; 615 u8 vimage_hi:4; 616 u8 himage_hi:4; 617 u8 h_border; 618 u8 v_border; 619 u8 rsvd1:3; 620 u8 digital:2; 621 u8 vsync_positive:1; 622 u8 hsync_positive:1; 623 u8 non_interlaced:1; 624} __packed; 625 626struct bdb_sdvo_panel_dtds { 627 struct lvds_dvo_timing dtds[4]; 628} __packed; 629 630/* 631 * Block 27 - eDP VBT Block 632 */ 633 634#define EDP_18BPP 0 635#define EDP_24BPP 1 636#define EDP_30BPP 2 637#define EDP_RATE_1_62 0 638#define EDP_RATE_2_7 1 639#define EDP_LANE_1 0 640#define EDP_LANE_2 1 641#define EDP_LANE_4 3 642#define EDP_PREEMPHASIS_NONE 0 643#define EDP_PREEMPHASIS_3_5dB 1 644#define EDP_PREEMPHASIS_6dB 2 645#define EDP_PREEMPHASIS_9_5dB 3 646#define EDP_VSWING_0_4V 0 647#define EDP_VSWING_0_6V 1 648#define EDP_VSWING_0_8V 2 649#define EDP_VSWING_1_2V 3 650 651 652struct edp_fast_link_params { 653 u8 rate:4; 654 u8 lanes:4; 655 u8 preemphasis:4; 656 u8 vswing:4; 657} __packed; 658 659struct edp_pwm_delays { 660 u16 pwm_on_to_backlight_enable; 661 u16 backlight_disable_to_pwm_off; 662} __packed; 663 664struct edp_full_link_params { 665 u8 preemphasis:4; 666 u8 vswing:4; 667} __packed; 668 669struct bdb_edp { 670 struct edp_power_seq power_seqs[16]; 671 u32 color_depth; 672 struct edp_fast_link_params fast_link_params[16]; 673 u32 sdrrs_msa_timing_delay; 674 675 /* ith bit indicates enabled/disabled for (i+1)th panel */ 676 u16 edp_s3d_feature; /* 162 */ 677 u16 edp_t3_optimization; /* 165 */ 678 u64 edp_vswing_preemph; /* 173 */ 679 u16 fast_link_training; /* 182 */ 680 u16 dpcd_600h_write_required; /* 185 */ 681 struct edp_pwm_delays pwm_delays[16]; /* 186 */ 682 u16 full_link_params_provided; /* 199 */ 683 struct edp_full_link_params full_link_params[16]; /* 199 */ 684} __packed; 685 686/* 687 * Block 40 - LFP Data Block 688 */ 689 690/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */ 691#define MODE_MASK 0x3 692 693struct bdb_lvds_options { 694 u8 panel_type; 695 u8 panel_type2; /* 212 */ 696 /* LVDS capabilities, stored in a dword */ 697 u8 pfit_mode:2; 698 u8 pfit_text_mode_enhanced:1; 699 u8 pfit_gfx_mode_enhanced:1; 700 u8 pfit_ratio_auto:1; 701 u8 pixel_dither:1; 702 u8 lvds_edid:1; 703 u8 rsvd2:1; 704 u8 rsvd4; 705 /* LVDS Panel channel bits stored here */ 706 u32 lvds_panel_channel_bits; 707 /* LVDS SSC (Spread Spectrum Clock) bits stored here. */ 708 u16 ssc_bits; 709 u16 ssc_freq; 710 u16 ssc_ddt; 711 /* Panel color depth defined here */ 712 u16 panel_color_depth; 713 /* LVDS panel type bits stored here */ 714 u32 dps_panel_type_bits; 715 /* LVDS backlight control type bits stored here */ 716 u32 blt_control_type_bits; 717 718 u16 lcdvcc_s0_enable; /* 200 */ 719 u32 rotation; /* 228 */ 720} __packed; 721 722/* 723 * Block 41 - LFP Data Table Pointers 724 */ 725struct lvds_lfp_data_ptr_table { 726 u16 offset; /* offsets are from start of bdb */ 727 u8 table_size; 728} __packed; 729 730/* LFP pointer table contains entries to the struct below */ 731struct lvds_lfp_data_ptr { 732 struct lvds_lfp_data_ptr_table fp_timing; 733 struct lvds_lfp_data_ptr_table dvo_timing; 734 struct lvds_lfp_data_ptr_table panel_pnp_id; 735} __packed; 736 737struct bdb_lvds_lfp_data_ptrs { 738 u8 lvds_entries; 739 struct lvds_lfp_data_ptr ptr[16]; 740 struct lvds_lfp_data_ptr_table panel_name; /* 156-163? */ 741} __packed; 742 743/* 744 * Block 42 - LFP Data Tables 745 */ 746 747/* LFP data has 3 blocks per entry */ 748struct lvds_fp_timing { 749 u16 x_res; 750 u16 y_res; 751 u32 lvds_reg; 752 u32 lvds_reg_val; 753 u32 pp_on_reg; 754 u32 pp_on_reg_val; 755 u32 pp_off_reg; 756 u32 pp_off_reg_val; 757 u32 pp_cycle_reg; 758 u32 pp_cycle_reg_val; 759 u32 pfit_reg; 760 u32 pfit_reg_val; 761 u16 terminator; 762} __packed; 763 764struct lvds_pnp_id { 765 u16 mfg_name; 766 u16 product_code; 767 u32 serial; 768 u8 mfg_week; 769 u8 mfg_year; 770} __packed; 771 772/* 773 * For reference only. fp_timing has variable size so 774 * the data must be accessed using the data table pointers. 775 * Do not use this directly! 776 */ 777struct lvds_lfp_data_entry { 778 struct lvds_fp_timing fp_timing; 779 struct lvds_dvo_timing dvo_timing; 780 struct lvds_pnp_id pnp_id; 781} __packed; 782 783struct bdb_lvds_lfp_data { 784 struct lvds_lfp_data_entry data[16]; 785} __packed; 786 787struct lvds_lfp_panel_name { 788 u8 name[13]; 789} __packed; 790 791struct lvds_lfp_black_border { 792 u8 top; /* 227 */ 793 u8 bottom; /* 227 */ 794 u8 left; /* 238 */ 795 u8 right; /* 238 */ 796} __packed; 797 798struct bdb_lvds_lfp_data_tail { 799 struct lvds_lfp_panel_name panel_name[16]; /* 156-163? */ 800 u16 scaling_enable; /* 187 */ 801 u8 seamless_drrs_min_refresh_rate[16]; /* 188 */ 802 u8 pixel_overlap_count[16]; /* 208 */ 803 struct lvds_lfp_black_border black_border[16]; /* 227 */ 804 u16 dual_lfp_port_sync_enable; /* 231 */ 805 u16 gpu_dithering_for_banding_artifacts; /* 245 */ 806} __packed; 807 808/* 809 * Block 43 - LFP Backlight Control Data Block 810 */ 811 812#define BDB_BACKLIGHT_TYPE_NONE 0 813#define BDB_BACKLIGHT_TYPE_PWM 2 814 815struct lfp_backlight_data_entry { 816 u8 type:2; 817 u8 active_low_pwm:1; 818 u8 obsolete1:5; 819 u16 pwm_freq_hz; 820 u8 min_brightness; /* Obsolete from 234+ */ 821 u8 obsolete2; 822 u8 obsolete3; 823} __packed; 824 825struct lfp_backlight_control_method { 826 u8 type:4; 827 u8 controller:4; 828} __packed; 829 830struct lfp_brightness_level { 831 u16 level; 832 u16 reserved; 833} __packed; 834 835#define EXP_BDB_LFP_BL_DATA_SIZE_REV_191 \ 836 offsetof(struct bdb_lfp_backlight_data, brightness_level) 837#define EXP_BDB_LFP_BL_DATA_SIZE_REV_234 \ 838 offsetof(struct bdb_lfp_backlight_data, brightness_precision_bits) 839 840struct bdb_lfp_backlight_data { 841 u8 entry_size; 842 struct lfp_backlight_data_entry data[16]; 843 u8 level[16]; /* Obsolete from 234+ */ 844 struct lfp_backlight_control_method backlight_control[16]; 845 struct lfp_brightness_level brightness_level[16]; /* 234+ */ 846 struct lfp_brightness_level brightness_min_level[16]; /* 234+ */ 847 u8 brightness_precision_bits[16]; /* 236+ */ 848} __packed; 849 850/* 851 * Block 44 - LFP Power Conservation Features Block 852 */ 853 854struct als_data_entry { 855 u16 backlight_adjust; 856 u16 lux; 857} __packed; 858 859struct agressiveness_profile_entry { 860 u8 dpst_agressiveness : 4; 861 u8 lace_agressiveness : 4; 862} __packed; 863 864struct bdb_lfp_power { 865 u8 lfp_feature_bits; 866 struct als_data_entry als[5]; 867 u8 lace_aggressiveness_profile; 868 u16 dpst; 869 u16 psr; 870 u16 drrs; 871 u16 lace_support; 872 u16 adt; 873 u16 dmrrs; 874 u16 adb; 875 u16 lace_enabled_status; 876 struct agressiveness_profile_entry aggressivenes[16]; 877 u16 hobl; /* 232+ */ 878 u16 vrr_feature_enabled; /* 233+ */ 879} __packed; 880 881/* 882 * Block 52 - MIPI Configuration Block 883 */ 884 885#define MAX_MIPI_CONFIGURATIONS 6 886 887struct bdb_mipi_config { 888 struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; 889 struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; 890} __packed; 891 892/* 893 * Block 53 - MIPI Sequence Block 894 */ 895 896struct bdb_mipi_sequence { 897 u8 version; 898 u8 data[]; /* up to 6 variable length blocks */ 899} __packed; 900 901/* 902 * Block 56 - Compression Parameters 903 */ 904 905#define VBT_RC_BUFFER_BLOCK_SIZE_1KB 0 906#define VBT_RC_BUFFER_BLOCK_SIZE_4KB 1 907#define VBT_RC_BUFFER_BLOCK_SIZE_16KB 2 908#define VBT_RC_BUFFER_BLOCK_SIZE_64KB 3 909 910#define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value) ((vbt_value) + 8) /* bits */ 911#define VBT_DSC_MAX_BPP(vbt_value) (6 + (vbt_value) * 2) 912 913struct dsc_compression_parameters_entry { 914 u8 version_major:4; 915 u8 version_minor:4; 916 917 u8 rc_buffer_block_size:2; 918 u8 reserved1:6; 919 920 /* 921 * Buffer size in bytes: 922 * 923 * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes 924 */ 925 u8 rc_buffer_size; 926 u32 slices_per_line; 927 928 u8 line_buffer_depth:4; 929 u8 reserved2:4; 930 931 /* Flag Bits 1 */ 932 u8 block_prediction_enable:1; 933 u8 reserved3:7; 934 935 u8 max_bpp; /* mapping */ 936 937 /* Color depth capabilities */ 938 u8 reserved4:1; 939 u8 support_8bpc:1; 940 u8 support_10bpc:1; 941 u8 support_12bpc:1; 942 u8 reserved5:4; 943 944 u16 slice_height; 945} __packed; 946 947struct bdb_compression_parameters { 948 u16 entry_size; 949 struct dsc_compression_parameters_entry data[16]; 950} __packed; 951 952/* 953 * Block 58 - Generic DTD Block 954 */ 955 956struct generic_dtd_entry { 957 u32 pixel_clock; 958 u16 hactive; 959 u16 hblank; 960 u16 hfront_porch; 961 u16 hsync; 962 u16 vactive; 963 u16 vblank; 964 u16 vfront_porch; 965 u16 vsync; 966 u16 width_mm; 967 u16 height_mm; 968 969 /* Flags */ 970 u8 rsvd_flags:6; 971 u8 vsync_positive_polarity:1; 972 u8 hsync_positive_polarity:1; 973 974 u8 rsvd[3]; 975} __packed; 976 977struct bdb_generic_dtd { 978 u16 gdtd_size; 979 struct generic_dtd_entry dtd[]; /* up to 24 DTD's */ 980} __packed; 981 982#endif /* _INTEL_VBT_DEFS_H_ */