cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

gen2_engine_cs.h (1230B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Copyright © 2020 Intel Corporation
      4 */
      5
      6#ifndef __GEN2_ENGINE_CS_H__
      7#define __GEN2_ENGINE_CS_H__
      8
      9#include <linux/types.h>
     10
     11struct i915_request;
     12struct intel_engine_cs;
     13
     14int gen2_emit_flush(struct i915_request *rq, u32 mode);
     15int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode);
     16int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode);
     17
     18u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs);
     19u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs);
     20
     21int i830_emit_bb_start(struct i915_request *rq,
     22		       u64 offset, u32 len,
     23		       unsigned int dispatch_flags);
     24int gen3_emit_bb_start(struct i915_request *rq,
     25		       u64 offset, u32 len,
     26		       unsigned int dispatch_flags);
     27int gen4_emit_bb_start(struct i915_request *rq,
     28		       u64 offset, u32 length,
     29		       unsigned int dispatch_flags);
     30
     31void gen2_irq_enable(struct intel_engine_cs *engine);
     32void gen2_irq_disable(struct intel_engine_cs *engine);
     33void gen3_irq_enable(struct intel_engine_cs *engine);
     34void gen3_irq_disable(struct intel_engine_cs *engine);
     35void gen5_irq_enable(struct intel_engine_cs *engine);
     36void gen5_irq_disable(struct intel_engine_cs *engine);
     37
     38#endif /* __GEN2_ENGINE_CS_H__ */