intel_engine_regs.h (11680B)
1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6#ifndef __INTEL_ENGINE_REGS__ 7#define __INTEL_ENGINE_REGS__ 8 9#include "i915_reg_defs.h" 10 11#define RING_TAIL(base) _MMIO((base) + 0x30) 12#define TAIL_ADDR 0x001FFFF8 13#define RING_HEAD(base) _MMIO((base) + 0x34) 14#define HEAD_WRAP_COUNT 0xFFE00000 15#define HEAD_WRAP_ONE 0x00200000 16#define HEAD_ADDR 0x001FFFFC 17#define RING_START(base) _MMIO((base) + 0x38) 18#define RING_CTL(base) _MMIO((base) + 0x3c) 19#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ 20#define RING_NR_PAGES 0x001FF000 21#define RING_REPORT_MASK 0x00000006 22#define RING_REPORT_64K 0x00000002 23#define RING_REPORT_128K 0x00000004 24#define RING_NO_REPORT 0x00000000 25#define RING_VALID_MASK 0x00000001 26#define RING_VALID 0x00000001 27#define RING_INVALID 0x00000000 28#define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */ 29#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */ 30#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */ 31#define RING_SYNC_0(base) _MMIO((base) + 0x40) 32#define RING_SYNC_1(base) _MMIO((base) + 0x44) 33#define RING_SYNC_2(base) _MMIO((base) + 0x48) 34#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 35#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 36#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) 37#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 38#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 39#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) 40#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 41#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 42#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) 43#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) 44#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) 45#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) 46#define RING_PSMI_CTL(base) _MMIO((base) + 0x50) 47#define GEN8_RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12) 48#define GEN8_FF_DOP_CLOCK_GATE_DISABLE REG_BIT(10) 49#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7) 50#define GEN6_BSD_GO_INDICATOR REG_BIT(4) 51#define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3) 52#define GEN6_BSD_SLEEP_FLUSH_DISABLE REG_BIT(2) 53#define GEN6_PSMI_SLEEP_MSG_DISABLE REG_BIT(0) 54#define RING_MAX_IDLE(base) _MMIO((base) + 0x54) 55#define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54) 56#define IDLE_TIME_MASK 0xFFFFF 57#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c) 58#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */ 59#define RING_IPEIR(base) _MMIO((base) + 0x64) 60#define RING_IPEHR(base) _MMIO((base) + 0x68) 61#define RING_INSTDONE(base) _MMIO((base) + 0x6c) 62#define RING_INSTPS(base) _MMIO((base) + 0x70) 63#define RING_DMA_FADD(base) _MMIO((base) + 0x78) 64#define RING_ACTHD(base) _MMIO((base) + 0x74) 65#define RING_HWS_PGA(base) _MMIO((base) + 0x80) 66#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84) 67#define IPEIR(base) _MMIO((base) + 0x88) 68#define IPEHR(base) _MMIO((base) + 0x8c) 69#define RING_ID(base) _MMIO((base) + 0x8c) 70#define RING_NOPID(base) _MMIO((base) + 0x94) 71#define RING_HWSTAM(base) _MMIO((base) + 0x98) 72#define RING_MI_MODE(base) _MMIO((base) + 0x9c) 73#define ASYNC_FLIP_PERF_DISABLE REG_BIT(14) 74#define MI_FLUSH_ENABLE REG_BIT(12) 75#define TGL_NESTED_BB_EN REG_BIT(12) 76#define MODE_IDLE REG_BIT(9) 77#define STOP_RING REG_BIT(8) 78#define VS_TIMER_DISPATCH REG_BIT(6) 79#define RING_IMR(base) _MMIO((base) + 0xa8) 80#define RING_EIR(base) _MMIO((base) + 0xb0) 81#define RING_EMR(base) _MMIO((base) + 0xb4) 82#define RING_ESR(base) _MMIO((base) + 0xb8) 83#define RING_INSTPM(base) _MMIO((base) + 0xc0) 84#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4) 85#define ACTHD(base) _MMIO((base) + 0xc8) 86#define GEN8_R_PWR_CLK_STATE(base) _MMIO((base) + 0xc8) 87#define GEN8_RPCS_ENABLE (1 << 31) 88#define GEN8_RPCS_S_CNT_ENABLE (1 << 18) 89#define GEN8_RPCS_S_CNT_SHIFT 15 90#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) 91#define GEN11_RPCS_S_CNT_SHIFT 12 92#define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT) 93#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) 94#define GEN8_RPCS_SS_CNT_SHIFT 8 95#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) 96#define GEN8_RPCS_EU_MAX_SHIFT 4 97#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) 98#define GEN8_RPCS_EU_MIN_SHIFT 0 99#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) 100 101#define RING_RESET_CTL(base) _MMIO((base) + 0xd0) 102#define RESET_CTL_CAT_ERROR REG_BIT(2) 103#define RESET_CTL_READY_TO_RESET REG_BIT(1) 104#define RESET_CTL_REQUEST_RESET REG_BIT(0) 105#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0) 106#define RING_BBSTATE(base) _MMIO((base) + 0x110) 107#define RING_BB_PPGTT (1 << 5) 108#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */ 109#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */ 110#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */ 111#define RING_BBADDR(base) _MMIO((base) + 0x140) 112#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */ 113#define CCID(base) _MMIO((base) + 0x180) 114#define CCID_EN BIT(0) 115#define CCID_EXTENDED_STATE_RESTORE BIT(2) 116#define CCID_EXTENDED_STATE_SAVE BIT(3) 117#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */ 118#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */ 119#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ 120#define ECOSKPD(base) _MMIO((base) + 0x1d0) 121#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4) 122#define ECO_GATING_CX_ONLY REG_BIT(3) 123#define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3) 124#define ECO_FLIP_DONE REG_BIT(0) 125#define GEN6_BLITTER_LOCK_SHIFT 16 126 127#define BLIT_CCTL(base) _MMIO((base) + 0x204) 128#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8) 129#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0) 130#define BLIT_CCTL_MASK (BLIT_CCTL_DST_MOCS_MASK | \ 131 BLIT_CCTL_SRC_MOCS_MASK) 132#define BLIT_CCTL_MOCS(dst, src) \ 133 (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \ 134 REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1)) 135 136/* 137 * CMD_CCTL read/write fields take a MOCS value and _not_ a table index. 138 * The lsb of each can be considered a separate enabling bit for encryption. 139 * 6:0 == default MOCS value for reads => 6:1 == table index for reads. 140 * 13:7 == default MOCS value for writes => 13:8 == table index for writes. 141 * 15:14 == Reserved => 31:30 are set to 0. 142 */ 143#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7) 144#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0) 145#define CMD_CCTL_MOCS_MASK (CMD_CCTL_WRITE_OVERRIDE_MASK | \ 146 CMD_CCTL_READ_OVERRIDE_MASK) 147#define CMD_CCTL_MOCS_OVERRIDE(write, read) \ 148 (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \ 149 REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1)) 150 151#define RING_PREDICATE_RESULT(base) _MMIO((base) + 0x3b8) /* gen12+ */ 152#define MI_PREDICATE_RESULT_2(base) _MMIO((base) + 0x3bc) 153#define LOWER_SLICE_ENABLED (1 << 0) 154#define LOWER_SLICE_DISABLED (0 << 0) 155#define MI_PREDICATE_SRC0(base) _MMIO((base) + 0x400) 156#define MI_PREDICATE_SRC0_UDW(base) _MMIO((base) + 0x400 + 4) 157#define MI_PREDICATE_SRC1(base) _MMIO((base) + 0x408) 158#define MI_PREDICATE_SRC1_UDW(base) _MMIO((base) + 0x408 + 4) 159#define MI_PREDICATE_DATA(base) _MMIO((base) + 0x410) 160#define MI_PREDICATE_RESULT(base) _MMIO((base) + 0x418) 161#define MI_PREDICATE_RESULT_1(base) _MMIO((base) + 0x41c) 162 163#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220) 164#define PP_DIR_DCLV_2G 0xffffffff 165#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228) 166#define RING_ELSP(base) _MMIO((base) + 0x230) 167#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234) 168#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4) 169#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244) 170#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0) 171#define CTX_CTRL_RS_CTX_ENABLE REG_BIT(1) 172#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT REG_BIT(2) 173#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3) 174#define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE REG_BIT(8) 175#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c) 176#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4) 177#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8) 178#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c) 179#define GFX_RUN_LIST_ENABLE (1 << 15) 180#define GFX_INTERRUPT_STEERING (1 << 14) 181#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13) 182#define GFX_SURFACE_FAULT_ENABLE (1 << 12) 183#define GFX_REPLAY_MODE (1 << 11) 184#define GFX_PSMI_GRANULARITY (1 << 10) 185#define GEN12_GFX_PREFETCH_DISABLE REG_BIT(10) 186#define GFX_PPGTT_ENABLE (1 << 9) 187#define GEN8_GFX_PPGTT_48B (1 << 7) 188#define GFX_FORWARD_VBLANK_MASK (3 << 5) 189#define GFX_FORWARD_VBLANK_NEVER (0 << 5) 190#define GFX_FORWARD_VBLANK_ALWAYS (1 << 5) 191#define GFX_FORWARD_VBLANK_COND (2 << 5) 192#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3) 193#define RING_TIMESTAMP(base) _MMIO((base) + 0x358) 194#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4) 195#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0) 196#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ 197#define RING_PREDICATE_RESULT(base) _MMIO((base) + 0x3b8) 198#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4) 199#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2) 200#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */ 201#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28) 202#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28) 203#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28) 204#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28) 205#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */ 206#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0) 207#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0) 208#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0) 209#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0) 210#define RING_FORCE_TO_NONPRIV_MASK_VALID \ 211 (RING_FORCE_TO_NONPRIV_RANGE_MASK | RING_FORCE_TO_NONPRIV_ACCESS_MASK) 212#define RING_MAX_NONPRIV_SLOTS 12 213 214#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510) 215#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518) 216#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550) 217#define EL_CTRL_LOAD REG_BIT(0) 218 219/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */ 220#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8) 221#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4) 222 223#define GEN11_VCS_SFC_FORCED_LOCK(base) _MMIO((base) + 0x88c) 224#define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0) 225#define GEN11_VCS_SFC_LOCK_STATUS(base) _MMIO((base) + 0x890) 226#define GEN11_VCS_SFC_USAGE_BIT (1 << 0) 227#define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1) 228 229#define GEN11_VECS_SFC_FORCED_LOCK(base) _MMIO((base) + 0x201c) 230#define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0) 231#define GEN11_VECS_SFC_LOCK_ACK(base) _MMIO((base) + 0x2018) 232#define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0) 233#define GEN11_VECS_SFC_USAGE(base) _MMIO((base) + 0x2014) 234#define GEN11_VECS_SFC_USAGE_BIT (1 << 0) 235 236#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) 237 238#define GEN12_HCP_SFC_LOCK_STATUS(base) _MMIO((base) + 0x2914) 239#define GEN12_HCP_SFC_LOCK_ACK_BIT REG_BIT(1) 240#define GEN12_HCP_SFC_USAGE_BIT REG_BIT(0) 241 242#define VDBOX_CGCTL3F10(base) _MMIO((base) + 0x3f10) 243#define IECPUNIT_CLKGATE_DIS REG_BIT(22) 244 245#define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18) 246#define ALNUNIT_CLKGATE_DIS REG_BIT(13) 247 248 249#endif /* __INTEL_ENGINE_REGS__ */