cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intel_gsc.h (920B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
      4 */
      5#ifndef __INTEL_GSC_DEV_H__
      6#define __INTEL_GSC_DEV_H__
      7
      8#include <linux/types.h>
      9
     10struct drm_i915_private;
     11struct intel_gt;
     12struct mei_aux_device;
     13
     14#define INTEL_GSC_NUM_INTERFACES 2
     15/*
     16 * The HECI1 bit corresponds to bit15 and HECI2 to bit14.
     17 * The reason for this is to allow growth for more interfaces in the future.
     18 */
     19#define GSC_IRQ_INTF(_x)  BIT(15 - (_x))
     20
     21/**
     22 * struct intel_gsc - graphics security controller
     23 * @intf : gsc interface
     24 */
     25struct intel_gsc {
     26	struct intel_gsc_intf {
     27		struct mei_aux_device *adev;
     28		int irq;
     29		unsigned int id;
     30	} intf[INTEL_GSC_NUM_INTERFACES];
     31};
     32
     33void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *dev_priv);
     34void intel_gsc_fini(struct intel_gsc *gsc);
     35void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir);
     36
     37#endif /* __INTEL_GSC_DEV_H__ */