cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

intel_gt_irq.h (1821B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Copyright © 2019 Intel Corporation
      4 */
      5
      6#ifndef INTEL_GT_IRQ_H
      7#define INTEL_GT_IRQ_H
      8
      9#include <linux/types.h>
     10
     11#include "intel_engine_types.h"
     12
     13struct intel_gt;
     14
     15#define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
     16		      GEN8_GT_BCS_IRQ | \
     17		      GEN8_GT_VCS0_IRQ | \
     18		      GEN8_GT_VCS1_IRQ | \
     19		      GEN8_GT_VECS_IRQ | \
     20		      GEN8_GT_PM_IRQ | \
     21		      GEN8_GT_GUC_IRQ)
     22
     23void gen11_gt_irq_reset(struct intel_gt *gt);
     24void gen11_gt_irq_postinstall(struct intel_gt *gt);
     25void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl);
     26
     27bool gen11_gt_reset_one_iir(struct intel_gt *gt,
     28			    const unsigned int bank,
     29			    const unsigned int bit);
     30
     31void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir);
     32
     33void gen5_gt_irq_postinstall(struct intel_gt *gt);
     34void gen5_gt_irq_reset(struct intel_gt *gt);
     35void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask);
     36void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask);
     37
     38void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir);
     39
     40void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl);
     41void gen8_gt_irq_reset(struct intel_gt *gt);
     42void gen8_gt_irq_postinstall(struct intel_gt *gt);
     43
     44static inline void intel_engine_cs_irq(struct intel_engine_cs *engine, u16 iir)
     45{
     46	if (iir)
     47		engine->irq_handler(engine, iir);
     48}
     49
     50static inline void
     51intel_engine_set_irq_handler(struct intel_engine_cs *engine,
     52			     void (*fn)(struct intel_engine_cs *engine,
     53					u16 iir))
     54{
     55	/*
     56	 * As the interrupt is live as allocate and setup the engines,
     57	 * err on the side of caution and apply barriers to updating
     58	 * the irq handler callback. This assures that when we do use
     59	 * the engine, we will receive interrupts only to ourselves,
     60	 * and not lose any.
     61	 */
     62	smp_store_mb(engine->irq_handler, fn);
     63}
     64
     65#endif /* INTEL_GT_IRQ_H */