cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

guc_actions_slpc_abi.h (9674B)


      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Copyright © 2021 Intel Corporation
      4 */
      5
      6#ifndef _GUC_ACTIONS_SLPC_ABI_H_
      7#define _GUC_ACTIONS_SLPC_ABI_H_
      8
      9#include <linux/types.h>
     10
     11/**
     12 * DOC: SLPC SHARED DATA STRUCTURE
     13 *
     14 *  +----+------+--------------------------------------------------------------+
     15 *  | CL | Bytes| Description                                                  |
     16 *  +====+======+==============================================================+
     17 *  | 1  | 0-3  | SHARED DATA SIZE                                             |
     18 *  |    +------+--------------------------------------------------------------+
     19 *  |    | 4-7  | GLOBAL STATE                                                 |
     20 *  |    +------+--------------------------------------------------------------+
     21 *  |    | 8-11 | DISPLAY DATA ADDRESS                                         |
     22 *  |    +------+--------------------------------------------------------------+
     23 *  |    | 12:63| PADDING                                                      |
     24 *  +----+------+--------------------------------------------------------------+
     25 *  |    | 0:63 | PADDING(PLATFORM INFO)                                       |
     26 *  +----+------+--------------------------------------------------------------+
     27 *  | 3  | 0-3  | TASK STATE DATA                                              |
     28 *  +    +------+--------------------------------------------------------------+
     29 *  |    | 4:63 | PADDING                                                      |
     30 *  +----+------+--------------------------------------------------------------+
     31 *  |4-21|0:1087| OVERRIDE PARAMS AND BIT FIELDS                               |
     32 *  +----+------+--------------------------------------------------------------+
     33 *  |    |      | PADDING + EXTRA RESERVED PAGE                                |
     34 *  +----+------+--------------------------------------------------------------+
     35 */
     36
     37/*
     38 * SLPC exposes certain parameters for global configuration by the host.
     39 * These are referred to as override parameters, because in most cases
     40 * the host will not need to modify the default values used by SLPC.
     41 * SLPC remembers the default values which allows the host to easily restore
     42 * them by simply unsetting the override. The host can set or unset override
     43 * parameters during SLPC (re-)initialization using the SLPC Reset event.
     44 * The host can also set or unset override parameters on the fly using the
     45 * Parameter Set and Parameter Unset events
     46 */
     47
     48#define SLPC_MAX_OVERRIDE_PARAMETERS		256
     49#define SLPC_OVERRIDE_BITFIELD_SIZE \
     50		(SLPC_MAX_OVERRIDE_PARAMETERS / 32)
     51
     52#define SLPC_PAGE_SIZE_BYTES			4096
     53#define SLPC_CACHELINE_SIZE_BYTES		64
     54#define SLPC_SHARED_DATA_SIZE_BYTE_HEADER	SLPC_CACHELINE_SIZE_BYTES
     55#define SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO	SLPC_CACHELINE_SIZE_BYTES
     56#define SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE	SLPC_CACHELINE_SIZE_BYTES
     57#define SLPC_SHARED_DATA_MODE_DEFN_TABLE_SIZE	SLPC_PAGE_SIZE_BYTES
     58#define SLPC_SHARED_DATA_SIZE_BYTE_MAX		(2 * SLPC_PAGE_SIZE_BYTES)
     59
     60/*
     61 * Cacheline size aligned (Total size needed for
     62 * SLPM_KMD_MAX_OVERRIDE_PARAMETERS=256 is 1088 bytes)
     63 */
     64#define SLPC_OVERRIDE_PARAMS_TOTAL_BYTES	(((((SLPC_MAX_OVERRIDE_PARAMETERS * 4) \
     65						+ ((SLPC_MAX_OVERRIDE_PARAMETERS / 32) * 4)) \
     66		+ (SLPC_CACHELINE_SIZE_BYTES - 1)) / SLPC_CACHELINE_SIZE_BYTES) * \
     67					SLPC_CACHELINE_SIZE_BYTES)
     68
     69#define SLPC_SHARED_DATA_SIZE_BYTE_OTHER	(SLPC_SHARED_DATA_SIZE_BYTE_MAX - \
     70					(SLPC_SHARED_DATA_SIZE_BYTE_HEADER \
     71					+ SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO \
     72					+ SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE \
     73					+ SLPC_OVERRIDE_PARAMS_TOTAL_BYTES \
     74					+ SLPC_SHARED_DATA_MODE_DEFN_TABLE_SIZE))
     75
     76enum slpc_task_enable {
     77	SLPC_PARAM_TASK_DEFAULT = 0,
     78	SLPC_PARAM_TASK_ENABLED,
     79	SLPC_PARAM_TASK_DISABLED,
     80	SLPC_PARAM_TASK_UNKNOWN
     81};
     82
     83enum slpc_global_state {
     84	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
     85	SLPC_GLOBAL_STATE_INITIALIZING = 1,
     86	SLPC_GLOBAL_STATE_RESETTING = 2,
     87	SLPC_GLOBAL_STATE_RUNNING = 3,
     88	SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
     89	SLPC_GLOBAL_STATE_ERROR = 5
     90};
     91
     92enum slpc_param_id {
     93	SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
     94	SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
     95	SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
     96	SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
     97	SLPC_PARAM_TASK_ENABLE_DCC = 4,
     98	SLPC_PARAM_TASK_DISABLE_DCC = 5,
     99	SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
    100	SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
    101	SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
    102	SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
    103	SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
    104	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
    105	SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
    106	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
    107	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
    108	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
    109	SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
    110	SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
    111	SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
    112	SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
    113	SLPC_PARAM_GLOBAL_RT_MODE_TURBO_FREQ_DELTA_MHZ = 20,
    114	SLPC_PARAM_PWRGATE_RC_MODE = 21,
    115	SLPC_PARAM_EDR_MODE_COMPUTE_TIMEOUT_MS = 22,
    116	SLPC_PARAM_EDR_QOS_FREQ_MHZ = 23,
    117	SLPC_PARAM_MEDIA_FF_RATIO_MODE = 24,
    118	SLPC_PARAM_ENABLE_IA_FREQ_LIMITING = 25,
    119	SLPC_PARAM_STRATEGIES = 26,
    120	SLPC_PARAM_POWER_PROFILE = 27,
    121	SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY = 28,
    122	SLPC_MAX_PARAM = 32,
    123};
    124
    125enum slpc_event_id {
    126	SLPC_EVENT_RESET = 0,
    127	SLPC_EVENT_SHUTDOWN = 1,
    128	SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
    129	SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
    130	SLPC_EVENT_FLIP_COMPLETE = 4,
    131	SLPC_EVENT_QUERY_TASK_STATE = 5,
    132	SLPC_EVENT_PARAMETER_SET = 6,
    133	SLPC_EVENT_PARAMETER_UNSET = 7,
    134};
    135
    136struct slpc_task_state_data {
    137	union {
    138		u32 task_status_padding;
    139		struct {
    140			u32 status;
    141#define SLPC_GTPERF_TASK_ENABLED	REG_BIT(0)
    142#define SLPC_DCC_TASK_ENABLED		REG_BIT(11)
    143#define SLPC_IN_DCC			REG_BIT(12)
    144#define SLPC_BALANCER_ENABLED		REG_BIT(15)
    145#define SLPC_IBC_TASK_ENABLED		REG_BIT(16)
    146#define SLPC_BALANCER_IA_LMT_ENABLED	REG_BIT(17)
    147#define SLPC_BALANCER_IA_LMT_ACTIVE	REG_BIT(18)
    148		};
    149	};
    150	union {
    151		u32 freq_padding;
    152		struct {
    153#define SLPC_MAX_UNSLICE_FREQ_MASK	REG_GENMASK(7, 0)
    154#define SLPC_MIN_UNSLICE_FREQ_MASK	REG_GENMASK(15, 8)
    155#define SLPC_MAX_SLICE_FREQ_MASK	REG_GENMASK(23, 16)
    156#define SLPC_MIN_SLICE_FREQ_MASK	REG_GENMASK(31, 24)
    157			u32 freq;
    158		};
    159	};
    160} __packed;
    161
    162struct slpc_shared_data_header {
    163	/* Total size in bytes of this shared buffer. */
    164	u32 size;
    165	u32 global_state;
    166	u32 display_data_addr;
    167} __packed;
    168
    169struct slpc_override_params {
    170	u32 bits[SLPC_OVERRIDE_BITFIELD_SIZE];
    171	u32 values[SLPC_MAX_OVERRIDE_PARAMETERS];
    172} __packed;
    173
    174struct slpc_shared_data {
    175	struct slpc_shared_data_header header;
    176	u8 shared_data_header_pad[SLPC_SHARED_DATA_SIZE_BYTE_HEADER -
    177				sizeof(struct slpc_shared_data_header)];
    178
    179	u8 platform_info_pad[SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO];
    180
    181	struct slpc_task_state_data task_state_data;
    182	u8 task_state_data_pad[SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE -
    183				sizeof(struct slpc_task_state_data)];
    184
    185	struct slpc_override_params override_params;
    186	u8 override_params_pad[SLPC_OVERRIDE_PARAMS_TOTAL_BYTES -
    187				sizeof(struct slpc_override_params)];
    188
    189	u8 shared_data_pad[SLPC_SHARED_DATA_SIZE_BYTE_OTHER];
    190
    191	/* PAGE 2 (4096 bytes), mode based parameter will be removed soon */
    192	u8 reserved_mode_definition[4096];
    193} __packed;
    194
    195/**
    196 * DOC: SLPC H2G MESSAGE FORMAT
    197 *
    198 *  +---+-------+--------------------------------------------------------------+
    199 *  |   | Bits  | Description                                                  |
    200 *  +===+=======+==============================================================+
    201 *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_HOST_                                |
    202 *  |   +-------+--------------------------------------------------------------+
    203 *  |   | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_                                 |
    204 *  |   +-------+--------------------------------------------------------------+
    205 *  |   | 27:16 | DATA0 = MBZ                                                  |
    206 *  |   +-------+--------------------------------------------------------------+
    207 *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_PC_SLPM_REQUEST` = 0x3003     |
    208 *  +---+-------+--------------------------------------------------------------+
    209 *  | 1 |  31:8 | **EVENT_ID**                                                 |
    210 *  +   +-------+--------------------------------------------------------------+
    211 *  |   |   7:0 | **EVENT_ARGC** - number of data arguments                    |
    212 *  +---+-------+--------------------------------------------------------------+
    213 *  | 2 |  31:0 | **EVENT_DATA1**                                              |
    214 *  +---+-------+--------------------------------------------------------------+
    215 *  |...|  31:0 | ...                                                          |
    216 *  +---+-------+--------------------------------------------------------------+
    217 *  |2+n|  31:0 | **EVENT_DATAn**                                              |
    218 *  +---+-------+--------------------------------------------------------------+
    219 */
    220
    221#define GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST		0x3003
    222
    223#define HOST2GUC_PC_SLPC_REQUEST_MSG_MIN_LEN \
    224				(GUC_HXG_REQUEST_MSG_MIN_LEN + 1u)
    225#define HOST2GUC_PC_SLPC_EVENT_MAX_INPUT_ARGS		9
    226#define HOST2GUC_PC_SLPC_REQUEST_MSG_MAX_LEN \
    227		(HOST2GUC_PC_SLPC_REQUEST_REQUEST_MSG_MIN_LEN + \
    228			HOST2GUC_PC_SLPC_EVENT_MAX_INPUT_ARGS)
    229#define HOST2GUC_PC_SLPC_REQUEST_MSG_0_MBZ		GUC_HXG_REQUEST_MSG_0_DATA0
    230#define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID		(0xff << 8)
    231#define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC	(0xff << 0)
    232#define HOST2GUC_PC_SLPC_REQUEST_MSG_N_EVENT_DATA_N	GUC_HXG_REQUEST_MSG_n_DATAn
    233
    234#endif