display.c (27354B)
1/* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Zhiyuan Lv <zhiyuan.lv@intel.com> 26 * 27 * Contributors: 28 * Terrence Xu <terrence.xu@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * Zhi Wang <zhi.a.wang@intel.com> 32 * 33 */ 34 35#include "i915_drv.h" 36#include "i915_reg.h" 37#include "gvt.h" 38 39static int get_edp_pipe(struct intel_vgpu *vgpu) 40{ 41 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); 42 int pipe = -1; 43 44 switch (data & TRANS_DDI_EDP_INPUT_MASK) { 45 case TRANS_DDI_EDP_INPUT_A_ON: 46 case TRANS_DDI_EDP_INPUT_A_ONOFF: 47 pipe = PIPE_A; 48 break; 49 case TRANS_DDI_EDP_INPUT_B_ONOFF: 50 pipe = PIPE_B; 51 break; 52 case TRANS_DDI_EDP_INPUT_C_ONOFF: 53 pipe = PIPE_C; 54 break; 55 } 56 return pipe; 57} 58 59static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) 60{ 61 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 62 63 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) 64 return 0; 65 66 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) 67 return 0; 68 return 1; 69} 70 71int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 72{ 73 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 74 75 if (drm_WARN_ON(&dev_priv->drm, 76 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) 77 return -EINVAL; 78 79 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) 80 return 1; 81 82 if (edp_pipe_is_enabled(vgpu) && 83 get_edp_pipe(vgpu) == pipe) 84 return 1; 85 return 0; 86} 87 88static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = { 89 { 90/* EDID with 1024x768 as its resolution */ 91 /*Header*/ 92 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 93 /* Vendor & Product Identification */ 94 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 95 /* Version & Revision */ 96 0x01, 0x04, 97 /* Basic Display Parameters & Features */ 98 0xa5, 0x34, 0x20, 0x78, 0x23, 99 /* Color Characteristics */ 100 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 101 /* Established Timings: maximum resolution is 1024x768 */ 102 0x21, 0x08, 0x00, 103 /* Standard Timings. All invalid */ 104 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00, 105 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 106 /* 18 Byte Data Blocks 1: invalid */ 107 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0, 108 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 109 /* 18 Byte Data Blocks 2: invalid */ 110 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 111 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 112 /* 18 Byte Data Blocks 3: invalid */ 113 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 114 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 115 /* 18 Byte Data Blocks 4: invalid */ 116 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 117 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 118 /* Extension Block Count */ 119 0x00, 120 /* Checksum */ 121 0xef, 122 }, 123 { 124/* EDID with 1920x1200 as its resolution */ 125 /*Header*/ 126 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 127 /* Vendor & Product Identification */ 128 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 129 /* Version & Revision */ 130 0x01, 0x04, 131 /* Basic Display Parameters & Features */ 132 0xa5, 0x34, 0x20, 0x78, 0x23, 133 /* Color Characteristics */ 134 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 135 /* Established Timings: maximum resolution is 1024x768 */ 136 0x21, 0x08, 0x00, 137 /* 138 * Standard Timings. 139 * below new resolutions can be supported: 140 * 1920x1080, 1280x720, 1280x960, 1280x1024, 141 * 1440x900, 1600x1200, 1680x1050 142 */ 143 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 144 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01, 145 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */ 146 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0, 147 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 148 /* 18 Byte Data Blocks 2: invalid */ 149 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 150 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 151 /* 18 Byte Data Blocks 3: invalid */ 152 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 153 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 154 /* 18 Byte Data Blocks 4: invalid */ 155 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 156 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 157 /* Extension Block Count */ 158 0x00, 159 /* Checksum */ 160 0x45, 161 }, 162}; 163 164#define DPCD_HEADER_SIZE 0xb 165 166/* let the virtual display supports DP1.2 */ 167static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { 168 0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 169}; 170 171static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 172{ 173 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 174 int pipe; 175 176 if (IS_BROXTON(dev_priv)) { 177 enum transcoder trans; 178 enum port port; 179 180 /* Clear PIPE, DDI, PHY, HPD before setting new */ 181 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 182 ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | 183 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | 184 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)); 185 186 for_each_pipe(dev_priv, pipe) { 187 vgpu_vreg_t(vgpu, PIPECONF(pipe)) &= 188 ~(PIPECONF_ENABLE | PIPECONF_STATE_ENABLE); 189 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; 190 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 191 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK; 192 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; 193 } 194 195 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) { 196 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &= 197 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 198 TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE); 199 } 200 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 201 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 202 TRANS_DDI_PORT_MASK); 203 204 for (port = PORT_A; port <= PORT_C; port++) { 205 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &= 206 ~BXT_PHY_LANE_ENABLED; 207 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |= 208 (BXT_PHY_CMNLANE_POWERDOWN_ACK | 209 BXT_PHY_LANE_POWERDOWN_ACK); 210 211 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &= 212 ~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 213 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 214 PORT_PLL_ENABLE); 215 216 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &= 217 ~(DDI_INIT_DISPLAY_DETECTED | 218 DDI_BUF_CTL_ENABLE); 219 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE; 220 } 221 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 222 ~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK); 223 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 224 ~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK); 225 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 226 ~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK); 227 /* No hpd_invert set in vgpu vbt, need to clear invert mask */ 228 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK; 229 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK; 230 231 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1)); 232 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 233 ~PHY_POWER_GOOD; 234 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 235 ~PHY_POWER_GOOD; 236 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); 237 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30); 238 239 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED; 240 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED; 241 242 /* 243 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 244 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 245 * TRANSCODER_A can be enabled. PORT_x depends on the input of 246 * setup_virtual_dp_monitor. 247 */ 248 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; 249 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_STATE_ENABLE; 250 251 /* 252 * Golden M/N are calculated based on: 253 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 254 * DP link clk 1620 MHz and non-constant_n. 255 * TODO: calculate DP link symbol clk and stream clk m/n. 256 */ 257 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64); 258 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; 259 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; 260 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; 261 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; 262 263 /* Enable per-DDI/PORT vreg */ 264 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 265 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1); 266 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 267 PHY_POWER_GOOD; 268 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |= 269 BIT(30); 270 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= 271 BXT_PHY_LANE_ENABLED; 272 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= 273 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 274 BXT_PHY_LANE_POWERDOWN_ACK); 275 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |= 276 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 277 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 278 PORT_PLL_ENABLE); 279 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= 280 (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED); 281 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= 282 ~DDI_BUF_IS_IDLE; 283 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |= 284 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 285 TRANS_DDI_FUNC_ENABLE); 286 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 287 PORTA_HOTPLUG_ENABLE; 288 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 289 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 290 } 291 292 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 293 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 294 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); 295 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 296 PHY_POWER_GOOD; 297 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= 298 BIT(30); 299 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= 300 BXT_PHY_LANE_ENABLED; 301 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= 302 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 303 BXT_PHY_LANE_POWERDOWN_ACK); 304 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |= 305 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 306 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 307 PORT_PLL_ENABLE); 308 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= 309 DDI_BUF_CTL_ENABLE; 310 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= 311 ~DDI_BUF_IS_IDLE; 312 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 313 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 314 (PORT_B << TRANS_DDI_PORT_SHIFT) | 315 TRANS_DDI_FUNC_ENABLE); 316 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 317 PORTB_HOTPLUG_ENABLE; 318 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 319 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 320 } 321 322 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 323 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 324 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); 325 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 326 PHY_POWER_GOOD; 327 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= 328 BIT(30); 329 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= 330 BXT_PHY_LANE_ENABLED; 331 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= 332 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 333 BXT_PHY_LANE_POWERDOWN_ACK); 334 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |= 335 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 336 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 337 PORT_PLL_ENABLE); 338 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= 339 DDI_BUF_CTL_ENABLE; 340 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= 341 ~DDI_BUF_IS_IDLE; 342 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 343 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 344 (PORT_B << TRANS_DDI_PORT_SHIFT) | 345 TRANS_DDI_FUNC_ENABLE); 346 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 347 PORTC_HOTPLUG_ENABLE; 348 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 349 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 350 } 351 352 return; 353 } 354 355 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | 356 SDE_PORTC_HOTPLUG_CPT | 357 SDE_PORTD_HOTPLUG_CPT); 358 359 if (IS_SKYLAKE(dev_priv) || 360 IS_KABYLAKE(dev_priv) || 361 IS_COFFEELAKE(dev_priv) || 362 IS_COMETLAKE(dev_priv)) { 363 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | 364 SDE_PORTE_HOTPLUG_SPT); 365 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= 366 SKL_FUSE_DOWNLOAD_STATUS | 367 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | 368 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | 369 SKL_FUSE_PG_DIST_STATUS(SKL_PG2); 370 /* 371 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 372 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 373 * TRANSCODER_A can be enabled. PORT_x depends on the input of 374 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x 375 * so we fixed to DPLL0 here. 376 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode 377 */ 378 vgpu_vreg_t(vgpu, DPLL_CTRL1) = 379 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0); 380 vgpu_vreg_t(vgpu, DPLL_CTRL1) |= 381 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0); 382 vgpu_vreg_t(vgpu, LCPLL1_CTL) = 383 LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK; 384 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0); 385 /* 386 * Golden M/N are calculated based on: 387 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 388 * DP link clk 1620 MHz and non-constant_n. 389 * TODO: calculate DP link symbol clk and stream clk m/n. 390 */ 391 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64); 392 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; 393 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; 394 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; 395 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; 396 } 397 398 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 399 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 400 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B); 401 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 402 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B); 403 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 404 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); 405 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 406 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 407 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 408 TRANS_DDI_PORT_MASK); 409 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 410 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 411 (PORT_B << TRANS_DDI_PORT_SHIFT) | 412 TRANS_DDI_FUNC_ENABLE); 413 if (IS_BROADWELL(dev_priv)) { 414 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= 415 ~PORT_CLK_SEL_MASK; 416 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= 417 PORT_CLK_SEL_LCPLL_810; 418 } 419 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; 420 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; 421 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; 422 } 423 424 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 425 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 426 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C); 427 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 428 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C); 429 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 430 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C); 431 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; 432 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 433 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 434 TRANS_DDI_PORT_MASK); 435 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 436 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 437 (PORT_C << TRANS_DDI_PORT_SHIFT) | 438 TRANS_DDI_FUNC_ENABLE); 439 if (IS_BROADWELL(dev_priv)) { 440 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= 441 ~PORT_CLK_SEL_MASK; 442 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= 443 PORT_CLK_SEL_LCPLL_810; 444 } 445 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; 446 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; 447 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 448 } 449 450 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { 451 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 452 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D); 453 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 454 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D); 455 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 456 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D); 457 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 458 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 459 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 460 TRANS_DDI_PORT_MASK); 461 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 462 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 463 (PORT_D << TRANS_DDI_PORT_SHIFT) | 464 TRANS_DDI_FUNC_ENABLE); 465 if (IS_BROADWELL(dev_priv)) { 466 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= 467 ~PORT_CLK_SEL_MASK; 468 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= 469 PORT_CLK_SEL_LCPLL_810; 470 } 471 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; 472 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; 473 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; 474 } 475 476 if ((IS_SKYLAKE(dev_priv) || 477 IS_KABYLAKE(dev_priv) || 478 IS_COFFEELAKE(dev_priv) || 479 IS_COMETLAKE(dev_priv)) && 480 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { 481 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; 482 } 483 484 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 485 if (IS_BROADWELL(dev_priv)) 486 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 487 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 488 else 489 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; 490 491 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; 492 } 493 494 /* Clear host CRT status, so guest couldn't detect this host CRT. */ 495 if (IS_BROADWELL(dev_priv)) 496 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; 497 498 /* Disable Primary/Sprite/Cursor plane */ 499 for_each_pipe(dev_priv, pipe) { 500 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; 501 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 502 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK; 503 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; 504 } 505 506 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; 507} 508 509static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 510{ 511 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 512 513 kfree(port->edid); 514 port->edid = NULL; 515 516 kfree(port->dpcd); 517 port->dpcd = NULL; 518} 519 520static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data) 521{ 522 struct intel_vgpu_vblank_timer *vblank_timer; 523 struct intel_vgpu *vgpu; 524 525 vblank_timer = container_of(data, struct intel_vgpu_vblank_timer, timer); 526 vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer); 527 528 /* Set vblank emulation request per-vGPU bit */ 529 intel_gvt_request_service(vgpu->gvt, 530 INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id); 531 hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period); 532 return HRTIMER_RESTART; 533} 534 535static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 536 int type, unsigned int resolution) 537{ 538 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 539 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 540 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; 541 542 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM)) 543 return -EINVAL; 544 545 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL); 546 if (!port->edid) 547 return -ENOMEM; 548 549 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); 550 if (!port->dpcd) { 551 kfree(port->edid); 552 return -ENOMEM; 553 } 554 555 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution], 556 EDID_SIZE); 557 port->edid->data_valid = true; 558 559 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); 560 port->dpcd->data_valid = true; 561 port->dpcd->data[DPCD_SINK_COUNT] = 0x1; 562 port->type = type; 563 port->id = resolution; 564 port->vrefresh_k = GVT_DEFAULT_REFRESH_RATE * MSEC_PER_SEC; 565 vgpu->display.port_num = port_num; 566 567 /* Init hrtimer based on default refresh rate */ 568 hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); 569 vblank_timer->timer.function = vblank_timer_fn; 570 vblank_timer->vrefresh_k = port->vrefresh_k; 571 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); 572 573 emulate_monitor_status_change(vgpu); 574 575 return 0; 576} 577 578/** 579 * vgpu_update_vblank_emulation - Update per-vGPU vblank_timer 580 * @vgpu: vGPU operated 581 * @turnon: Turn ON/OFF vblank_timer 582 * 583 * This function is used to turn on/off or update the per-vGPU vblank_timer 584 * when PIPECONF is enabled or disabled. vblank_timer period is also updated 585 * if guest changed the refresh rate. 586 * 587 */ 588void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon) 589{ 590 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; 591 struct intel_vgpu_port *port = 592 intel_vgpu_port(vgpu, vgpu->display.port_num); 593 594 if (turnon) { 595 /* 596 * Skip the re-enable if already active and vrefresh unchanged. 597 * Otherwise, stop timer if already active and restart with new 598 * period. 599 */ 600 if (vblank_timer->vrefresh_k != port->vrefresh_k || 601 !hrtimer_active(&vblank_timer->timer)) { 602 /* Stop timer before start with new period if active */ 603 if (hrtimer_active(&vblank_timer->timer)) 604 hrtimer_cancel(&vblank_timer->timer); 605 606 /* Make sure new refresh rate updated to timer period */ 607 vblank_timer->vrefresh_k = port->vrefresh_k; 608 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); 609 hrtimer_start(&vblank_timer->timer, 610 ktime_add_ns(ktime_get(), vblank_timer->period), 611 HRTIMER_MODE_ABS); 612 } 613 } else { 614 /* Caller request to stop vblank */ 615 hrtimer_cancel(&vblank_timer->timer); 616 } 617} 618 619static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 620{ 621 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 622 struct intel_vgpu_irq *irq = &vgpu->irq; 623 int vblank_event[] = { 624 [PIPE_A] = PIPE_A_VBLANK, 625 [PIPE_B] = PIPE_B_VBLANK, 626 [PIPE_C] = PIPE_C_VBLANK, 627 }; 628 int event; 629 630 if (pipe < PIPE_A || pipe > PIPE_C) 631 return; 632 633 for_each_set_bit(event, irq->flip_done_event[pipe], 634 INTEL_GVT_EVENT_MAX) { 635 clear_bit(event, irq->flip_done_event[pipe]); 636 if (!pipe_is_enabled(vgpu, pipe)) 637 continue; 638 639 intel_vgpu_trigger_virtual_event(vgpu, event); 640 } 641 642 if (pipe_is_enabled(vgpu, pipe)) { 643 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++; 644 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); 645 } 646} 647 648void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu) 649{ 650 int pipe; 651 652 mutex_lock(&vgpu->vgpu_lock); 653 for_each_pipe(vgpu->gvt->gt->i915, pipe) 654 emulate_vblank_on_pipe(vgpu, pipe); 655 mutex_unlock(&vgpu->vgpu_lock); 656} 657 658/** 659 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU 660 * @vgpu: a vGPU 661 * @connected: link state 662 * 663 * This function is used to trigger hotplug interrupt for vGPU 664 * 665 */ 666void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) 667{ 668 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 669 670 /* TODO: add more platforms support */ 671 if (IS_SKYLAKE(i915) || 672 IS_KABYLAKE(i915) || 673 IS_COFFEELAKE(i915) || 674 IS_COMETLAKE(i915)) { 675 if (connected) { 676 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 677 SFUSE_STRAP_DDID_DETECTED; 678 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 679 } else { 680 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 681 ~SFUSE_STRAP_DDID_DETECTED; 682 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT; 683 } 684 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT; 685 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 686 PORTD_HOTPLUG_STATUS_MASK; 687 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG); 688 } else if (IS_BROXTON(i915)) { 689 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 690 if (connected) { 691 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 692 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 693 } else { 694 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 695 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 696 } 697 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 698 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 699 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 700 ~PORTA_HOTPLUG_STATUS_MASK; 701 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 702 PORTA_HOTPLUG_LONG_DETECT; 703 intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG); 704 } 705 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 706 if (connected) { 707 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 708 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 709 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 710 SFUSE_STRAP_DDIB_DETECTED; 711 } else { 712 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 713 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 714 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 715 ~SFUSE_STRAP_DDIB_DETECTED; 716 } 717 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 718 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 719 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 720 ~PORTB_HOTPLUG_STATUS_MASK; 721 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 722 PORTB_HOTPLUG_LONG_DETECT; 723 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG); 724 } 725 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 726 if (connected) { 727 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 728 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 729 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 730 SFUSE_STRAP_DDIC_DETECTED; 731 } else { 732 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 733 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 734 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 735 ~SFUSE_STRAP_DDIC_DETECTED; 736 } 737 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 738 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 739 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 740 ~PORTC_HOTPLUG_STATUS_MASK; 741 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 742 PORTC_HOTPLUG_LONG_DETECT; 743 intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG); 744 } 745 } 746} 747 748/** 749 * intel_vgpu_clean_display - clean vGPU virtual display emulation 750 * @vgpu: a vGPU 751 * 752 * This function is used to clean vGPU virtual display emulation stuffs 753 * 754 */ 755void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 756{ 757 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 758 759 if (IS_SKYLAKE(dev_priv) || 760 IS_KABYLAKE(dev_priv) || 761 IS_COFFEELAKE(dev_priv) || 762 IS_COMETLAKE(dev_priv)) 763 clean_virtual_dp_monitor(vgpu, PORT_D); 764 else 765 clean_virtual_dp_monitor(vgpu, PORT_B); 766 767 vgpu_update_vblank_emulation(vgpu, false); 768} 769 770/** 771 * intel_vgpu_init_display- initialize vGPU virtual display emulation 772 * @vgpu: a vGPU 773 * @resolution: resolution index for intel_vgpu_edid 774 * 775 * This function is used to initialize vGPU virtual display emulation stuffs 776 * 777 * Returns: 778 * Zero on success, negative error code if failed. 779 * 780 */ 781int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) 782{ 783 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 784 785 intel_vgpu_init_i2c_edid(vgpu); 786 787 if (IS_SKYLAKE(dev_priv) || 788 IS_KABYLAKE(dev_priv) || 789 IS_COFFEELAKE(dev_priv) || 790 IS_COMETLAKE(dev_priv)) 791 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, 792 resolution); 793 else 794 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B, 795 resolution); 796} 797 798/** 799 * intel_vgpu_reset_display- reset vGPU virtual display emulation 800 * @vgpu: a vGPU 801 * 802 * This function is used to reset vGPU virtual display emulation stuffs 803 * 804 */ 805void intel_vgpu_reset_display(struct intel_vgpu *vgpu) 806{ 807 emulate_monitor_status_change(vgpu); 808}