cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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edid.h (4231B)

      1/*
      2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice (including the next
     12 * paragraph) shall be included in all copies or substantial portions of the
     13 * Software.
     14 *
     15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     21 * SOFTWARE.
     22 *
     23 * Authors:
     24 *    Ke Yu
     25 *    Zhiyuan Lv <zhiyuan.lv@intel.com>
     26 *
     27 * Contributors:
     28 *    Terrence Xu <terrence.xu@intel.com>
     29 *    Changbin Du <changbin.du@intel.com>
     30 *    Bing Niu <bing.niu@intel.com>
     31 *    Zhi Wang <zhi.a.wang@intel.com>
     32 *
     33 */
     34
     35#ifndef _GVT_EDID_H_
     36#define _GVT_EDID_H_
     37
     38#include <linux/types.h>
     39
     40struct intel_vgpu;
     41
     42#define EDID_SIZE		128
     43#define EDID_ADDR		0x50 /* Linux hvm EDID addr */
     44
     45#define GVT_AUX_NATIVE_WRITE			0x8
     46#define GVT_AUX_NATIVE_READ			0x9
     47#define GVT_AUX_I2C_WRITE			0x0
     48#define GVT_AUX_I2C_READ			0x1
     49#define GVT_AUX_I2C_STATUS			0x2
     50#define GVT_AUX_I2C_MOT				0x4
     51#define GVT_AUX_I2C_REPLY_ACK			0x0
     52
     53struct intel_vgpu_edid_data {
     54	bool data_valid;
     55	unsigned char edid_block[EDID_SIZE];
     56};
     57
     58enum gmbus_cycle_type {
     59	GMBUS_NOCYCLE	= 0x0,
     60	NIDX_NS_W	= 0x1,
     61	IDX_NS_W	= 0x3,
     62	GMBUS_STOP	= 0x4,
     63	NIDX_STOP	= 0x5,
     64	IDX_STOP	= 0x7
     65};
     66
     67/*
     68 * States of GMBUS
     69 *
     70 * GMBUS0-3 could be related to the EDID virtualization. Another two GMBUS
     71 * registers, GMBUS4 (interrupt mask) and GMBUS5 (2 byte indes register), are
     72 * not considered here. Below describes the usage of GMBUS registers that are
     73 * cared by the EDID virtualization
     74 *
     75 * GMBUS0:
     76 *      R/W
     77 *      port selection. value of bit0 - bit2 corresponds to the GPIO registers.
     78 *
     79 * GMBUS1:
     80 *      R/W Protect
     81 *      Command and Status.
     82 *      bit0 is the direction bit: 1 is read; 0 is write.
     83 *      bit1 - bit7 is slave 7-bit address.
     84 *      bit16 - bit24 total byte count (ignore?)
     85 *
     86 * GMBUS2:
     87 *      Most of bits are read only except bit 15 (IN_USE)
     88 *      Status register
     89 *      bit0 - bit8 current byte count
     90 *      bit 11: hardware ready;
     91 *
     92 * GMBUS3:
     93 *      Read/Write
     94 *      Data for transfer
     95 */
     96
     97/* From hw specs, Other phases like START, ADDRESS, INDEX
     98 * are invisible to GMBUS MMIO interface. So no definitions
     99 * in below enum types
    100 */
    101enum gvt_gmbus_phase {
    102	GMBUS_IDLE_PHASE = 0,
    103	GMBUS_DATA_PHASE,
    104	GMBUS_WAIT_PHASE,
    105	//GMBUS_STOP_PHASE,
    106	GMBUS_MAX_PHASE
    107};
    108
    109struct intel_vgpu_i2c_gmbus {
    110	unsigned int total_byte_count; /* from GMBUS1 */
    111	enum gmbus_cycle_type cycle_type;
    112	enum gvt_gmbus_phase phase;
    113};
    114
    115struct intel_vgpu_i2c_aux_ch {
    116	bool i2c_over_aux_ch;
    117	bool aux_ch_mot;
    118};
    119
    120enum i2c_state {
    121	I2C_NOT_SPECIFIED = 0,
    122	I2C_GMBUS = 1,
    123	I2C_AUX_CH = 2
    124};
    125
    126/* I2C sequences cannot interleave.
    127 * GMBUS and AUX_CH sequences cannot interleave.
    128 */
    129struct intel_vgpu_i2c_edid {
    130	enum i2c_state state;
    131
    132	unsigned int port;
    133	bool slave_selected;
    134	bool edid_available;
    135	unsigned int current_edid_read;
    136
    137	struct intel_vgpu_i2c_gmbus gmbus;
    138	struct intel_vgpu_i2c_aux_ch aux_ch;
    139};
    140
    141void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu);
    142
    143int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
    144		unsigned int offset, void *p_data, unsigned int bytes);
    145
    146int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
    147		unsigned int offset, void *p_data, unsigned int bytes);
    148
    149void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
    150		int port_idx,
    151		unsigned int offset,
    152		void *p_data);
    153
    154#endif /*_GVT_EDID_H_*/