cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mmio_context.h (2345B)

      1/*
      2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice (including the next
     12 * paragraph) shall be included in all copies or substantial portions of the
     13 * Software.
     14 *
     15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     21 * SOFTWARE.
     22 *
     23 * Authors:
     24 *    Eddie Dong <eddie.dong@intel.com>
     25 *    Kevin Tian <kevin.tian@intel.com>
     26 *
     27 * Contributors:
     28 *    Zhi Wang <zhi.a.wang@intel.com>
     29 *    Changbin Du <changbin.du@intel.com>
     30 *    Zhenyu Wang <zhenyuw@linux.intel.com>
     31 *    Tina Zhang <tina.zhang@intel.com>
     32 *    Bing Niu <bing.niu@intel.com>
     33 *
     34 */
     35
     36#ifndef __GVT_RENDER_H__
     37#define __GVT_RENDER_H__
     38
     39#include <linux/types.h>
     40
     41#include "gt/intel_engine_regs.h"
     42#include "gt/intel_engine_types.h"
     43#include "gt/intel_lrc_reg.h"
     44
     45struct i915_request;
     46struct intel_context;
     47struct intel_engine_cs;
     48struct intel_gvt;
     49struct intel_vgpu;
     50
     51struct engine_mmio {
     52	enum intel_engine_id id;
     53	i915_reg_t reg;
     54	u32 mask;
     55	bool in_context;
     56	u32 value;
     57};
     58
     59void intel_gvt_switch_mmio(struct intel_vgpu *pre,
     60			   struct intel_vgpu *next,
     61			   const struct intel_engine_cs *engine);
     62
     63void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt);
     64
     65bool is_inhibit_context(struct intel_context *ce);
     66
     67int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
     68				       struct i915_request *req);
     69
     70#define IS_RESTORE_INHIBIT(a) \
     71	IS_MASKED_BITS_ENABLED(a, CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT)
     72
     73#endif