cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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i915_irq.h (4853B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Copyright © 2019 Intel Corporation
      4 */
      5
      6#ifndef __I915_IRQ_H__
      7#define __I915_IRQ_H__
      8
      9#include <linux/ktime.h>
     10#include <linux/types.h>
     11
     12#include "i915_reg.h"
     13
     14enum pipe;
     15struct drm_crtc;
     16struct drm_device;
     17struct drm_display_mode;
     18struct drm_i915_private;
     19struct intel_crtc;
     20struct intel_uncore;
     21
     22void intel_irq_init(struct drm_i915_private *dev_priv);
     23void intel_irq_fini(struct drm_i915_private *dev_priv);
     24int intel_irq_install(struct drm_i915_private *dev_priv);
     25void intel_irq_uninstall(struct drm_i915_private *dev_priv);
     26
     27u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
     28			      enum pipe pipe);
     29void
     30i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
     31		     u32 status_mask);
     32
     33void
     34i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
     35		      u32 status_mask);
     36
     37void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
     38void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
     39
     40void intel_hpd_irq_setup(struct drm_i915_private *i915);
     41void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
     42				   u32 mask,
     43				   u32 bits);
     44
     45void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits);
     46void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits);
     47
     48void bdw_enable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32 bits);
     49void bdw_disable_pipe_irq(struct drm_i915_private *i915, enum pipe pipe, u32 bits);
     50
     51void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits);
     52void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits);
     53
     54void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
     55void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
     56void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
     57void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
     58void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
     59void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
     60void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
     61u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask);
     62
     63void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
     64void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
     65bool intel_irqs_enabled(struct drm_i915_private *dev_priv);
     66void intel_synchronize_irq(struct drm_i915_private *i915);
     67void intel_synchronize_hardirq(struct drm_i915_private *i915);
     68
     69int intel_get_crtc_scanline(struct intel_crtc *crtc);
     70void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
     71				     u8 pipe_mask);
     72void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
     73				     u8 pipe_mask);
     74u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv);
     75
     76bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
     77				     ktime_t *vblank_time, bool in_vblank_irq);
     78
     79u32 i915_get_vblank_counter(struct drm_crtc *crtc);
     80u32 g4x_get_vblank_counter(struct drm_crtc *crtc);
     81
     82int i8xx_enable_vblank(struct drm_crtc *crtc);
     83int i915gm_enable_vblank(struct drm_crtc *crtc);
     84int i965_enable_vblank(struct drm_crtc *crtc);
     85int ilk_enable_vblank(struct drm_crtc *crtc);
     86int bdw_enable_vblank(struct drm_crtc *crtc);
     87void i8xx_disable_vblank(struct drm_crtc *crtc);
     88void i915gm_disable_vblank(struct drm_crtc *crtc);
     89void i965_disable_vblank(struct drm_crtc *crtc);
     90void ilk_disable_vblank(struct drm_crtc *crtc);
     91void bdw_disable_vblank(struct drm_crtc *crtc);
     92
     93void gen2_irq_reset(struct intel_uncore *uncore);
     94void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
     95		    i915_reg_t iir, i915_reg_t ier);
     96
     97void gen2_irq_init(struct intel_uncore *uncore,
     98		   u32 imr_val, u32 ier_val);
     99void gen3_irq_init(struct intel_uncore *uncore,
    100		   i915_reg_t imr, u32 imr_val,
    101		   i915_reg_t ier, u32 ier_val,
    102		   i915_reg_t iir);
    103
    104#define GEN8_IRQ_RESET_NDX(uncore, type, which) \
    105({ \
    106	unsigned int which_ = which; \
    107	gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
    108		       GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
    109})
    110
    111#define GEN3_IRQ_RESET(uncore, type) \
    112	gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
    113
    114#define GEN2_IRQ_RESET(uncore) \
    115	gen2_irq_reset(uncore)
    116
    117#define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
    118({ \
    119	unsigned int which_ = which; \
    120	gen3_irq_init((uncore), \
    121		      GEN8_##type##_IMR(which_), imr_val, \
    122		      GEN8_##type##_IER(which_), ier_val, \
    123		      GEN8_##type##_IIR(which_)); \
    124})
    125
    126#define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \
    127	gen3_irq_init((uncore), \
    128		      type##IMR, imr_val, \
    129		      type##IER, ier_val, \
    130		      type##IIR)
    131
    132#define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \
    133	gen2_irq_init((uncore), imr_val, ier_val)
    134
    135#endif /* __I915_IRQ_H__ */