cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intel_pm.h (3925B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Copyright © 2019 Intel Corporation
      4 */
      5
      6#ifndef __INTEL_PM_H__
      7#define __INTEL_PM_H__
      8
      9#include <linux/types.h>
     10
     11#include "display/intel_display.h"
     12#include "display/intel_global_state.h"
     13
     14#include "i915_drv.h"
     15
     16struct drm_device;
     17struct drm_i915_private;
     18struct i915_request;
     19struct intel_atomic_state;
     20struct intel_bw_state;
     21struct intel_crtc;
     22struct intel_crtc_state;
     23struct intel_plane;
     24struct skl_ddb_entry;
     25struct skl_pipe_wm;
     26struct skl_wm_level;
     27
     28void intel_init_clock_gating(struct drm_i915_private *dev_priv);
     29void intel_suspend_hw(struct drm_i915_private *dev_priv);
     30int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
     31void intel_init_pm(struct drm_i915_private *dev_priv);
     32void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
     33void intel_pm_setup(struct drm_i915_private *dev_priv);
     34void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
     35void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
     36void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
     37void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
     38u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
     39void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
     40			       struct skl_ddb_entry *ddb_y,
     41			       struct skl_ddb_entry *ddb_uv);
     42void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
     43u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
     44			    const struct skl_ddb_entry *entry);
     45void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
     46			      struct skl_pipe_wm *out);
     47void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
     48void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
     49void skl_wm_sanitize(struct drm_i915_private *dev_priv);
     50bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
     51			   const struct intel_bw_state *bw_state);
     52void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
     53void intel_sagv_post_plane_update(struct intel_atomic_state *state);
     54const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
     55					      enum plane_id plane_id,
     56					      int level);
     57const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
     58					      enum plane_id plane_id);
     59bool skl_wm_level_equals(const struct skl_wm_level *l1,
     60			 const struct skl_wm_level *l2);
     61bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
     62				 const struct skl_ddb_entry *entries,
     63				 int num_entries, int ignore_idx);
     64void skl_write_plane_wm(struct intel_plane *plane,
     65			const struct intel_crtc_state *crtc_state);
     66void skl_write_cursor_wm(struct intel_plane *plane,
     67			 const struct intel_crtc_state *crtc_state);
     68bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
     69void intel_init_ipc(struct drm_i915_private *dev_priv);
     70void intel_enable_ipc(struct drm_i915_private *dev_priv);
     71
     72bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
     73
     74struct intel_dbuf_state {
     75	struct intel_global_state base;
     76
     77	struct skl_ddb_entry ddb[I915_MAX_PIPES];
     78	unsigned int weight[I915_MAX_PIPES];
     79	u8 slices[I915_MAX_PIPES];
     80	u8 enabled_slices;
     81	u8 active_pipes;
     82	bool joined_mbus;
     83};
     84
     85struct intel_dbuf_state *
     86intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
     87
     88#define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
     89#define intel_atomic_get_old_dbuf_state(state) \
     90	to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
     91#define intel_atomic_get_new_dbuf_state(state) \
     92	to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
     93
     94int intel_dbuf_init(struct drm_i915_private *dev_priv);
     95void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
     96void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
     97void intel_mbus_dbox_update(struct intel_atomic_state *state);
     98
     99#endif /* __INTEL_PM_H__ */