vlv_sideband_reg.h (6799B)
1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6#ifndef _VLV_SIDEBAND_REG_H_ 7#define _VLV_SIDEBAND_REG_H_ 8 9/* See configdb bunit SB addr map */ 10#define BUNIT_REG_BISOC 0x11 11 12/* PUNIT_REG_*SSPM0 */ 13#define _SSPM0_SSC(val) ((val) << 0) 14#define SSPM0_SSC_MASK _SSPM0_SSC(0x3) 15#define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0) 16#define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1) 17#define SSPM0_SSC_RESET _SSPM0_SSC(0x2) 18#define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3) 19#define _SSPM0_SSS(val) ((val) << 24) 20#define SSPM0_SSS_MASK _SSPM0_SSS(0x3) 21#define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0) 22#define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1) 23#define SSPM0_SSS_RESET _SSPM0_SSS(0x2) 24#define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3) 25 26/* PUNIT_REG_*SSPM1 */ 27#define SSPM1_FREQSTAT_SHIFT 24 28#define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT) 29#define SSPM1_FREQGUAR_SHIFT 8 30#define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT) 31#define SSPM1_FREQ_SHIFT 0 32#define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT) 33 34#define PUNIT_REG_VEDSSPM0 0x32 35#define PUNIT_REG_VEDSSPM1 0x33 36 37#define PUNIT_REG_DSPSSPM 0x36 38#define DSPFREQSTAT_SHIFT_CHV 24 39#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) 40#define DSPFREQGUAR_SHIFT_CHV 8 41#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) 42#define DSPFREQSTAT_SHIFT 30 43#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) 44#define DSPFREQGUAR_SHIFT 14 45#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) 46#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ 47#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ 48#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ 49#define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) 50#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) 51#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) 52#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) 53#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) 54#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) 55#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) 56#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) 57#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) 58#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) 59#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) 60#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) 61 62#define PUNIT_REG_ISPSSPM0 0x39 63#define PUNIT_REG_ISPSSPM1 0x3a 64 65#define PUNIT_REG_PWRGT_CTRL 0x60 66#define PUNIT_REG_PWRGT_STATUS 0x61 67#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2)) 68#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2)) 69#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2)) 70#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2)) 71#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2)) 72 73#define PUNIT_PWGT_IDX_RENDER 0 74#define PUNIT_PWGT_IDX_MEDIA 1 75#define PUNIT_PWGT_IDX_DISP2D 3 76#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5 77#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6 78#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7 79#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8 80#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9 81#define PUNIT_PWGT_IDX_DPIO_RX0 10 82#define PUNIT_PWGT_IDX_DPIO_RX1 11 83#define PUNIT_PWGT_IDX_DPIO_CMN_D 12 84 85#define PUNIT_REG_GPU_LFM 0xd3 86#define PUNIT_REG_GPU_FREQ_REQ 0xd4 87#define PUNIT_REG_GPU_FREQ_STS 0xd8 88#define GPLLENABLE (1 << 4) 89#define GENFREQSTATUS (1 << 0) 90#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc 91#define PUNIT_REG_CZ_TIMESTAMP 0xce 92 93#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 94#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 95 96#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 97#define FB_GFX_FREQ_FUSE_MASK 0xff 98#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 99#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 100#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 101 102#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 103#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 104 105#define PUNIT_REG_DDR_SETUP2 0x139 106#define FORCE_DDR_FREQ_REQ_ACK (1 << 8) 107#define FORCE_DDR_LOW_FREQ (1 << 1) 108#define FORCE_DDR_HIGH_FREQ (1 << 0) 109 110#define PUNIT_GPU_STATUS_REG 0xdb 111#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 112#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff 113#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 114#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff 115 116#define PUNIT_GPU_DUTYCYCLE_REG 0xdf 117#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 118#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff 119 120#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c 121#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 122#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 123#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 124#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 125#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 126#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 127#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 128#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 129#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 130 131#define VLV_TURBO_SOC_OVERRIDE 0x04 132#define VLV_OVERRIDE_EN 1 133#define VLV_SOC_TDP_EN (1 << 1) 134#define VLV_BIAS_CPU_125_SOC_875 (6 << 2) 135#define CHV_BIAS_CPU_50_SOC_50 (3 << 2) 136 137/* vlv2 north clock has */ 138#define CCK_FUSE_REG 0x8 139#define CCK_FUSE_HPLL_FREQ_MASK 0x3 140#define CCK_REG_DSI_PLL_FUSE 0x44 141#define CCK_REG_DSI_PLL_CONTROL 0x48 142#define DSI_PLL_VCO_EN (1 << 31) 143#define DSI_PLL_LDO_GATE (1 << 30) 144#define DSI_PLL_P1_POST_DIV_SHIFT 17 145#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) 146#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) 147#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) 148#define DSI_PLL_MUX_MASK (3 << 9) 149#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) 150#define DSI_PLL_MUX_DSI0_CCK (1 << 10) 151#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) 152#define DSI_PLL_MUX_DSI1_CCK (1 << 9) 153#define DSI_PLL_CLK_GATE_MASK (0xf << 5) 154#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) 155#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) 156#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) 157#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) 158#define DSI_PLL_LOCK (1 << 0) 159#define CCK_REG_DSI_PLL_DIVIDER 0x4c 160#define DSI_PLL_LFSR (1 << 31) 161#define DSI_PLL_FRACTION_EN (1 << 30) 162#define DSI_PLL_FRAC_COUNTER_SHIFT 27 163#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) 164#define DSI_PLL_USYNC_CNT_SHIFT 18 165#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) 166#define DSI_PLL_N1_DIV_SHIFT 16 167#define DSI_PLL_N1_DIV_MASK (3 << 16) 168#define DSI_PLL_M1_DIV_SHIFT 0 169#define DSI_PLL_M1_DIV_MASK (0x1ff << 0) 170#define CCK_CZ_CLOCK_CONTROL 0x62 171#define CCK_GPLL_CLOCK_CONTROL 0x67 172#define CCK_DISPLAY_CLOCK_CONTROL 0x6b 173#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c 174#define CCK_TRUNK_FORCE_ON (1 << 17) 175#define CCK_TRUNK_FORCE_OFF (1 << 16) 176#define CCK_FREQUENCY_STATUS (0x1f << 8) 177#define CCK_FREQUENCY_STATUS_SHIFT 8 178#define CCK_FREQUENCY_VALUES (0x1f << 0) 179 180#endif /* _VLV_SIDEBAND_REG_H_ */