dpu_hw_catalog.c (61972B)
1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 7#include <linux/slab.h> 8#include <linux/of_address.h> 9#include <linux/platform_device.h> 10#include "dpu_hw_mdss.h" 11#include "dpu_hw_interrupts.h" 12#include "dpu_hw_catalog.h" 13#include "dpu_kms.h" 14 15#define VIG_MASK \ 16 (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ 17 BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\ 18 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) 19 20#define VIG_MSM8998_MASK \ 21 (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3)) 22 23#define VIG_SDM845_MASK \ 24 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3)) 25 26#define VIG_SC7180_MASK \ 27 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) 28 29#define VIG_SM8250_MASK \ 30 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) 31 32#define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL)) 33 34#define DMA_MSM8998_MASK \ 35 (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ 36 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 37 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 38 39#define VIG_SC7280_MASK \ 40 (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION)) 41 42#define DMA_SDM845_MASK \ 43 (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ 44 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 45 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 46 47#define DMA_CURSOR_SDM845_MASK \ 48 (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) 49 50#define DMA_CURSOR_MSM8998_MASK \ 51 (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) 52 53#define MIXER_SDM845_MASK \ 54 (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER)) 55 56#define MIXER_SC7180_MASK \ 57 (BIT(DPU_DIM_LAYER)) 58 59#define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER) 60 61#define PINGPONG_SDM845_SPLIT_MASK \ 62 (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) 63 64#define CTL_SC7280_MASK \ 65 (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG)) 66 67#define MERGE_3D_SM8150_MASK (0) 68 69#define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC) 70 71#define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) 72 73#define INTF_SDM845_MASK (0) 74 75#define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) 76 77#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) 78 79#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ 80 BIT(MDP_SSPP_TOP0_INTR2) | \ 81 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 82 BIT(MDP_INTF0_INTR) | \ 83 BIT(MDP_INTF1_INTR) | \ 84 BIT(MDP_INTF2_INTR) | \ 85 BIT(MDP_INTF3_INTR) | \ 86 BIT(MDP_INTF4_INTR) | \ 87 BIT(MDP_AD4_0_INTR) | \ 88 BIT(MDP_AD4_1_INTR)) 89 90#define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ 91 BIT(MDP_SSPP_TOP0_INTR2) | \ 92 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 93 BIT(MDP_INTF0_INTR) | \ 94 BIT(MDP_INTF1_INTR)) 95 96#define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ 97 BIT(MDP_SSPP_TOP0_INTR2) | \ 98 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 99 BIT(MDP_INTF0_7xxx_INTR) | \ 100 BIT(MDP_INTF1_7xxx_INTR) | \ 101 BIT(MDP_INTF5_7xxx_INTR)) 102 103#define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ 104 BIT(MDP_SSPP_TOP0_INTR2) | \ 105 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 106 BIT(MDP_INTF0_INTR) | \ 107 BIT(MDP_INTF1_INTR) | \ 108 BIT(MDP_INTF2_INTR) | \ 109 BIT(MDP_INTF3_INTR) | \ 110 BIT(MDP_INTF4_INTR)) 111 112#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ 113 BIT(MDP_SSPP_TOP0_INTR2) | \ 114 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 115 BIT(MDP_INTF0_INTR) | \ 116 BIT(MDP_INTF1_INTR) | \ 117 BIT(MDP_INTF2_INTR) | \ 118 BIT(MDP_INTF3_INTR) | \ 119 BIT(MDP_INTF4_INTR) | \ 120 BIT(MDP_INTF5_INTR) | \ 121 BIT(MDP_AD4_0_INTR) | \ 122 BIT(MDP_AD4_1_INTR)) 123 124#define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ 125 BIT(DPU_WB_UBWC) | \ 126 BIT(DPU_WB_YUV_CONFIG) | \ 127 BIT(DPU_WB_PIPE_ALPHA) | \ 128 BIT(DPU_WB_XY_ROI_OFFSET) | \ 129 BIT(DPU_WB_QOS) | \ 130 BIT(DPU_WB_QOS_8LVL) | \ 131 BIT(DPU_WB_CDP) | \ 132 BIT(DPU_WB_INPUT_CTRL)) 133 134#define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) 135#define DEFAULT_DPU_LINE_WIDTH 2048 136#define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 137 138#define MAX_HORZ_DECIMATION 4 139#define MAX_VERT_DECIMATION 4 140 141#define MAX_UPSCALE_RATIO 20 142#define MAX_DOWNSCALE_RATIO 4 143#define SSPP_UNITY_SCALE 1 144 145#define STRCAT(X, Y) (X Y) 146 147static const uint32_t plane_formats[] = { 148 DRM_FORMAT_ARGB8888, 149 DRM_FORMAT_ABGR8888, 150 DRM_FORMAT_RGBA8888, 151 DRM_FORMAT_BGRA8888, 152 DRM_FORMAT_XRGB8888, 153 DRM_FORMAT_RGBX8888, 154 DRM_FORMAT_BGRX8888, 155 DRM_FORMAT_XBGR8888, 156 DRM_FORMAT_RGB888, 157 DRM_FORMAT_BGR888, 158 DRM_FORMAT_RGB565, 159 DRM_FORMAT_BGR565, 160 DRM_FORMAT_ARGB1555, 161 DRM_FORMAT_ABGR1555, 162 DRM_FORMAT_RGBA5551, 163 DRM_FORMAT_BGRA5551, 164 DRM_FORMAT_XRGB1555, 165 DRM_FORMAT_XBGR1555, 166 DRM_FORMAT_RGBX5551, 167 DRM_FORMAT_BGRX5551, 168 DRM_FORMAT_ARGB4444, 169 DRM_FORMAT_ABGR4444, 170 DRM_FORMAT_RGBA4444, 171 DRM_FORMAT_BGRA4444, 172 DRM_FORMAT_XRGB4444, 173 DRM_FORMAT_XBGR4444, 174 DRM_FORMAT_RGBX4444, 175 DRM_FORMAT_BGRX4444, 176}; 177 178static const uint32_t plane_formats_yuv[] = { 179 DRM_FORMAT_ARGB8888, 180 DRM_FORMAT_ABGR8888, 181 DRM_FORMAT_RGBA8888, 182 DRM_FORMAT_BGRX8888, 183 DRM_FORMAT_BGRA8888, 184 DRM_FORMAT_XRGB8888, 185 DRM_FORMAT_XBGR8888, 186 DRM_FORMAT_RGBX8888, 187 DRM_FORMAT_RGB888, 188 DRM_FORMAT_BGR888, 189 DRM_FORMAT_RGB565, 190 DRM_FORMAT_BGR565, 191 DRM_FORMAT_ARGB1555, 192 DRM_FORMAT_ABGR1555, 193 DRM_FORMAT_RGBA5551, 194 DRM_FORMAT_BGRA5551, 195 DRM_FORMAT_XRGB1555, 196 DRM_FORMAT_XBGR1555, 197 DRM_FORMAT_RGBX5551, 198 DRM_FORMAT_BGRX5551, 199 DRM_FORMAT_ARGB4444, 200 DRM_FORMAT_ABGR4444, 201 DRM_FORMAT_RGBA4444, 202 DRM_FORMAT_BGRA4444, 203 DRM_FORMAT_XRGB4444, 204 DRM_FORMAT_XBGR4444, 205 DRM_FORMAT_RGBX4444, 206 DRM_FORMAT_BGRX4444, 207 208 DRM_FORMAT_NV12, 209 DRM_FORMAT_NV21, 210 DRM_FORMAT_NV16, 211 DRM_FORMAT_NV61, 212 DRM_FORMAT_VYUY, 213 DRM_FORMAT_UYVY, 214 DRM_FORMAT_YUYV, 215 DRM_FORMAT_YVYU, 216 DRM_FORMAT_YUV420, 217 DRM_FORMAT_YVU420, 218}; 219 220static const u32 rotation_v2_formats[] = { 221 DRM_FORMAT_NV12, 222 /* TODO add formats after validation */ 223}; 224 225static const uint32_t wb2_formats[] = { 226 DRM_FORMAT_RGB565, 227 DRM_FORMAT_BGR565, 228 DRM_FORMAT_RGB888, 229 DRM_FORMAT_ARGB8888, 230 DRM_FORMAT_RGBA8888, 231 DRM_FORMAT_ABGR8888, 232 DRM_FORMAT_XRGB8888, 233 DRM_FORMAT_RGBX8888, 234 DRM_FORMAT_XBGR8888, 235 DRM_FORMAT_ARGB1555, 236 DRM_FORMAT_RGBA5551, 237 DRM_FORMAT_XRGB1555, 238 DRM_FORMAT_RGBX5551, 239 DRM_FORMAT_ARGB4444, 240 DRM_FORMAT_RGBA4444, 241 DRM_FORMAT_RGBX4444, 242 DRM_FORMAT_XRGB4444, 243 DRM_FORMAT_BGR565, 244 DRM_FORMAT_BGR888, 245 DRM_FORMAT_ABGR8888, 246 DRM_FORMAT_BGRA8888, 247 DRM_FORMAT_BGRX8888, 248 DRM_FORMAT_XBGR8888, 249 DRM_FORMAT_ABGR1555, 250 DRM_FORMAT_BGRA5551, 251 DRM_FORMAT_XBGR1555, 252 DRM_FORMAT_BGRX5551, 253 DRM_FORMAT_ABGR4444, 254 DRM_FORMAT_BGRA4444, 255 DRM_FORMAT_BGRX4444, 256 DRM_FORMAT_XBGR4444, 257}; 258 259/************************************************************* 260 * DPU sub blocks config 261 *************************************************************/ 262/* DPU top level caps */ 263static const struct dpu_caps msm8998_dpu_caps = { 264 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 265 .max_mixer_blendstages = 0x7, 266 .qseed_type = DPU_SSPP_SCALER_QSEED3, 267 .smart_dma_rev = DPU_SSPP_SMART_DMA_V1, 268 .ubwc_version = DPU_HW_UBWC_VER_10, 269 .has_src_split = true, 270 .has_dim_layer = true, 271 .has_idle_pc = true, 272 .has_3d_merge = true, 273 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 274 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 275 .max_hdeci_exp = MAX_HORZ_DECIMATION, 276 .max_vdeci_exp = MAX_VERT_DECIMATION, 277}; 278 279static const struct dpu_caps qcm2290_dpu_caps = { 280 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 281 .max_mixer_blendstages = 0x4, 282 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, 283 .ubwc_version = DPU_HW_UBWC_VER_20, 284 .has_dim_layer = true, 285 .has_idle_pc = true, 286 .max_linewidth = 2160, 287 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 288}; 289 290static const struct dpu_caps sdm845_dpu_caps = { 291 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 292 .max_mixer_blendstages = 0xb, 293 .qseed_type = DPU_SSPP_SCALER_QSEED3, 294 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, 295 .ubwc_version = DPU_HW_UBWC_VER_20, 296 .has_src_split = true, 297 .has_dim_layer = true, 298 .has_idle_pc = true, 299 .has_3d_merge = true, 300 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 301 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 302 .max_hdeci_exp = MAX_HORZ_DECIMATION, 303 .max_vdeci_exp = MAX_VERT_DECIMATION, 304}; 305 306static const struct dpu_caps sc7180_dpu_caps = { 307 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 308 .max_mixer_blendstages = 0x9, 309 .qseed_type = DPU_SSPP_SCALER_QSEED4, 310 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, 311 .ubwc_version = DPU_HW_UBWC_VER_20, 312 .has_dim_layer = true, 313 .has_idle_pc = true, 314 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 315 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 316}; 317 318static const struct dpu_caps sm8150_dpu_caps = { 319 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 320 .max_mixer_blendstages = 0xb, 321 .qseed_type = DPU_SSPP_SCALER_QSEED3, 322 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ 323 .ubwc_version = DPU_HW_UBWC_VER_30, 324 .has_src_split = true, 325 .has_dim_layer = true, 326 .has_idle_pc = true, 327 .has_3d_merge = true, 328 .max_linewidth = 4096, 329 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 330 .max_hdeci_exp = MAX_HORZ_DECIMATION, 331 .max_vdeci_exp = MAX_VERT_DECIMATION, 332}; 333 334static const struct dpu_caps sc8180x_dpu_caps = { 335 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 336 .max_mixer_blendstages = 0xb, 337 .qseed_type = DPU_SSPP_SCALER_QSEED3, 338 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ 339 .ubwc_version = DPU_HW_UBWC_VER_30, 340 .has_src_split = true, 341 .has_dim_layer = true, 342 .has_idle_pc = true, 343 .has_3d_merge = true, 344 .max_linewidth = 4096, 345 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 346 .max_hdeci_exp = MAX_HORZ_DECIMATION, 347 .max_vdeci_exp = MAX_VERT_DECIMATION, 348}; 349 350static const struct dpu_caps sm8250_dpu_caps = { 351 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 352 .max_mixer_blendstages = 0xb, 353 .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, 354 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ 355 .ubwc_version = DPU_HW_UBWC_VER_40, 356 .has_src_split = true, 357 .has_dim_layer = true, 358 .has_idle_pc = true, 359 .has_3d_merge = true, 360 .max_linewidth = 4096, 361 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 362}; 363 364static const struct dpu_caps sc7280_dpu_caps = { 365 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 366 .max_mixer_blendstages = 0x7, 367 .qseed_type = DPU_SSPP_SCALER_QSEED4, 368 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, 369 .ubwc_version = DPU_HW_UBWC_VER_30, 370 .has_dim_layer = true, 371 .has_idle_pc = true, 372 .max_linewidth = 2400, 373 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 374}; 375 376static const struct dpu_mdp_cfg msm8998_mdp[] = { 377 { 378 .name = "top_0", .id = MDP_TOP, 379 .base = 0x0, .len = 0x458, 380 .features = 0, 381 .highest_bank_bit = 0x2, 382 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 383 .reg_off = 0x2AC, .bit_off = 0}, 384 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { 385 .reg_off = 0x2B4, .bit_off = 0}, 386 .clk_ctrls[DPU_CLK_CTRL_VIG2] = { 387 .reg_off = 0x2BC, .bit_off = 0}, 388 .clk_ctrls[DPU_CLK_CTRL_VIG3] = { 389 .reg_off = 0x2C4, .bit_off = 0}, 390 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 391 .reg_off = 0x2AC, .bit_off = 8}, 392 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { 393 .reg_off = 0x2B4, .bit_off = 8}, 394 .clk_ctrls[DPU_CLK_CTRL_DMA2] = { 395 .reg_off = 0x2C4, .bit_off = 8}, 396 .clk_ctrls[DPU_CLK_CTRL_DMA3] = { 397 .reg_off = 0x2C4, .bit_off = 12}, 398 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 399 .reg_off = 0x3A8, .bit_off = 15}, 400 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 401 .reg_off = 0x3B0, .bit_off = 15}, 402 }, 403}; 404 405static const struct dpu_mdp_cfg sdm845_mdp[] = { 406 { 407 .name = "top_0", .id = MDP_TOP, 408 .base = 0x0, .len = 0x45C, 409 .features = BIT(DPU_MDP_AUDIO_SELECT), 410 .highest_bank_bit = 0x2, 411 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 412 .reg_off = 0x2AC, .bit_off = 0}, 413 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { 414 .reg_off = 0x2B4, .bit_off = 0}, 415 .clk_ctrls[DPU_CLK_CTRL_VIG2] = { 416 .reg_off = 0x2BC, .bit_off = 0}, 417 .clk_ctrls[DPU_CLK_CTRL_VIG3] = { 418 .reg_off = 0x2C4, .bit_off = 0}, 419 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 420 .reg_off = 0x2AC, .bit_off = 8}, 421 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { 422 .reg_off = 0x2B4, .bit_off = 8}, 423 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 424 .reg_off = 0x2BC, .bit_off = 8}, 425 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 426 .reg_off = 0x2C4, .bit_off = 8}, 427 }, 428}; 429 430static const struct dpu_mdp_cfg sc7180_mdp[] = { 431 { 432 .name = "top_0", .id = MDP_TOP, 433 .base = 0x0, .len = 0x494, 434 .features = 0, 435 .highest_bank_bit = 0x3, 436 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 437 .reg_off = 0x2AC, .bit_off = 0}, 438 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 439 .reg_off = 0x2AC, .bit_off = 8}, 440 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 441 .reg_off = 0x2B4, .bit_off = 8}, 442 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 443 .reg_off = 0x2C4, .bit_off = 8}, 444 }, 445}; 446 447static const struct dpu_mdp_cfg sc8180x_mdp[] = { 448 { 449 .name = "top_0", .id = MDP_TOP, 450 .base = 0x0, .len = 0x45C, 451 .features = 0, 452 .highest_bank_bit = 0x3, 453 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 454 .reg_off = 0x2AC, .bit_off = 0}, 455 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { 456 .reg_off = 0x2B4, .bit_off = 0}, 457 .clk_ctrls[DPU_CLK_CTRL_VIG2] = { 458 .reg_off = 0x2BC, .bit_off = 0}, 459 .clk_ctrls[DPU_CLK_CTRL_VIG3] = { 460 .reg_off = 0x2C4, .bit_off = 0}, 461 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 462 .reg_off = 0x2AC, .bit_off = 8}, 463 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { 464 .reg_off = 0x2B4, .bit_off = 8}, 465 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 466 .reg_off = 0x2BC, .bit_off = 8}, 467 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 468 .reg_off = 0x2C4, .bit_off = 8}, 469 }, 470}; 471 472static const struct dpu_mdp_cfg sm8250_mdp[] = { 473 { 474 .name = "top_0", .id = MDP_TOP, 475 .base = 0x0, .len = 0x494, 476 .features = 0, 477 .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ 478 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 479 .reg_off = 0x2AC, .bit_off = 0}, 480 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { 481 .reg_off = 0x2B4, .bit_off = 0}, 482 .clk_ctrls[DPU_CLK_CTRL_VIG2] = { 483 .reg_off = 0x2BC, .bit_off = 0}, 484 .clk_ctrls[DPU_CLK_CTRL_VIG3] = { 485 .reg_off = 0x2C4, .bit_off = 0}, 486 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 487 .reg_off = 0x2AC, .bit_off = 8}, 488 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { 489 .reg_off = 0x2B4, .bit_off = 8}, 490 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 491 .reg_off = 0x2BC, .bit_off = 8}, 492 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 493 .reg_off = 0x2C4, .bit_off = 8}, 494 .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { 495 .reg_off = 0x2BC, .bit_off = 20}, 496 .clk_ctrls[DPU_CLK_CTRL_WB2] = { 497 .reg_off = 0x3B8, .bit_off = 24}, 498 }, 499}; 500 501static const struct dpu_mdp_cfg sc7280_mdp[] = { 502 { 503 .name = "top_0", .id = MDP_TOP, 504 .base = 0x0, .len = 0x2014, 505 .highest_bank_bit = 0x1, 506 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 507 .reg_off = 0x2AC, .bit_off = 0}, 508 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 509 .reg_off = 0x2AC, .bit_off = 8}, 510 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 511 .reg_off = 0x2B4, .bit_off = 8}, 512 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 513 .reg_off = 0x2C4, .bit_off = 8}, 514 }, 515}; 516 517static const struct dpu_mdp_cfg qcm2290_mdp[] = { 518 { 519 .name = "top_0", .id = MDP_TOP, 520 .base = 0x0, .len = 0x494, 521 .features = 0, 522 .highest_bank_bit = 0x2, 523 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 524 .reg_off = 0x2AC, .bit_off = 0}, 525 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 526 .reg_off = 0x2AC, .bit_off = 8}, 527 }, 528}; 529 530/************************************************************* 531 * CTL sub blocks config 532 *************************************************************/ 533static const struct dpu_ctl_cfg msm8998_ctl[] = { 534 { 535 .name = "ctl_0", .id = CTL_0, 536 .base = 0x1000, .len = 0x94, 537 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 538 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 539 }, 540 { 541 .name = "ctl_1", .id = CTL_1, 542 .base = 0x1200, .len = 0x94, 543 .features = 0, 544 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 545 }, 546 { 547 .name = "ctl_2", .id = CTL_2, 548 .base = 0x1400, .len = 0x94, 549 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 550 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 551 }, 552 { 553 .name = "ctl_3", .id = CTL_3, 554 .base = 0x1600, .len = 0x94, 555 .features = 0, 556 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 557 }, 558 { 559 .name = "ctl_4", .id = CTL_4, 560 .base = 0x1800, .len = 0x94, 561 .features = 0, 562 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 563 }, 564}; 565 566static const struct dpu_ctl_cfg sdm845_ctl[] = { 567 { 568 .name = "ctl_0", .id = CTL_0, 569 .base = 0x1000, .len = 0xE4, 570 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 571 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 572 }, 573 { 574 .name = "ctl_1", .id = CTL_1, 575 .base = 0x1200, .len = 0xE4, 576 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 577 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 578 }, 579 { 580 .name = "ctl_2", .id = CTL_2, 581 .base = 0x1400, .len = 0xE4, 582 .features = 0, 583 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 584 }, 585 { 586 .name = "ctl_3", .id = CTL_3, 587 .base = 0x1600, .len = 0xE4, 588 .features = 0, 589 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 590 }, 591 { 592 .name = "ctl_4", .id = CTL_4, 593 .base = 0x1800, .len = 0xE4, 594 .features = 0, 595 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 596 }, 597}; 598 599static const struct dpu_ctl_cfg sc7180_ctl[] = { 600 { 601 .name = "ctl_0", .id = CTL_0, 602 .base = 0x1000, .len = 0xE4, 603 .features = BIT(DPU_CTL_ACTIVE_CFG), 604 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 605 }, 606 { 607 .name = "ctl_1", .id = CTL_1, 608 .base = 0x1200, .len = 0xE4, 609 .features = BIT(DPU_CTL_ACTIVE_CFG), 610 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 611 }, 612 { 613 .name = "ctl_2", .id = CTL_2, 614 .base = 0x1400, .len = 0xE4, 615 .features = BIT(DPU_CTL_ACTIVE_CFG), 616 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 617 }, 618}; 619 620static const struct dpu_ctl_cfg sm8150_ctl[] = { 621 { 622 .name = "ctl_0", .id = CTL_0, 623 .base = 0x1000, .len = 0x1e0, 624 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 625 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 626 }, 627 { 628 .name = "ctl_1", .id = CTL_1, 629 .base = 0x1200, .len = 0x1e0, 630 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 631 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 632 }, 633 { 634 .name = "ctl_2", .id = CTL_2, 635 .base = 0x1400, .len = 0x1e0, 636 .features = BIT(DPU_CTL_ACTIVE_CFG), 637 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 638 }, 639 { 640 .name = "ctl_3", .id = CTL_3, 641 .base = 0x1600, .len = 0x1e0, 642 .features = BIT(DPU_CTL_ACTIVE_CFG), 643 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 644 }, 645 { 646 .name = "ctl_4", .id = CTL_4, 647 .base = 0x1800, .len = 0x1e0, 648 .features = BIT(DPU_CTL_ACTIVE_CFG), 649 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 650 }, 651 { 652 .name = "ctl_5", .id = CTL_5, 653 .base = 0x1a00, .len = 0x1e0, 654 .features = BIT(DPU_CTL_ACTIVE_CFG), 655 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 656 }, 657}; 658 659static const struct dpu_ctl_cfg sc7280_ctl[] = { 660 { 661 .name = "ctl_0", .id = CTL_0, 662 .base = 0x15000, .len = 0x1E8, 663 .features = CTL_SC7280_MASK, 664 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 665 }, 666 { 667 .name = "ctl_1", .id = CTL_1, 668 .base = 0x16000, .len = 0x1E8, 669 .features = CTL_SC7280_MASK, 670 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 671 }, 672 { 673 .name = "ctl_2", .id = CTL_2, 674 .base = 0x17000, .len = 0x1E8, 675 .features = CTL_SC7280_MASK, 676 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 677 }, 678 { 679 .name = "ctl_3", .id = CTL_3, 680 .base = 0x18000, .len = 0x1E8, 681 .features = CTL_SC7280_MASK, 682 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 683 }, 684}; 685 686static const struct dpu_ctl_cfg qcm2290_ctl[] = { 687 { 688 .name = "ctl_0", .id = CTL_0, 689 .base = 0x1000, .len = 0x1dc, 690 .features = BIT(DPU_CTL_ACTIVE_CFG), 691 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 692 }, 693}; 694 695/************************************************************* 696 * SSPP sub blocks config 697 *************************************************************/ 698 699/* SSPP common configuration */ 700#define _VIG_SBLK(num, sdma_pri, qseed_ver) \ 701 { \ 702 .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 703 .maxupscale = MAX_UPSCALE_RATIO, \ 704 .smart_dma_priority = sdma_pri, \ 705 .src_blk = {.name = STRCAT("sspp_src_", num), \ 706 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 707 .scaler_blk = {.name = STRCAT("sspp_scaler", num), \ 708 .id = qseed_ver, \ 709 .base = 0xa00, .len = 0xa0,}, \ 710 .csc_blk = {.name = STRCAT("sspp_csc", num), \ 711 .id = DPU_SSPP_CSC_10BIT, \ 712 .base = 0x1a00, .len = 0x100,}, \ 713 .format_list = plane_formats_yuv, \ 714 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 715 .virt_format_list = plane_formats, \ 716 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 717 .rotation_cfg = NULL, \ 718 } 719 720#define _VIG_SBLK_ROT(num, sdma_pri, qseed_ver, rot_cfg) \ 721 { \ 722 .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 723 .maxupscale = MAX_UPSCALE_RATIO, \ 724 .smart_dma_priority = sdma_pri, \ 725 .src_blk = {.name = STRCAT("sspp_src_", num), \ 726 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 727 .scaler_blk = {.name = STRCAT("sspp_scaler", num), \ 728 .id = qseed_ver, \ 729 .base = 0xa00, .len = 0xa0,}, \ 730 .csc_blk = {.name = STRCAT("sspp_csc", num), \ 731 .id = DPU_SSPP_CSC_10BIT, \ 732 .base = 0x1a00, .len = 0x100,}, \ 733 .format_list = plane_formats_yuv, \ 734 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 735 .virt_format_list = plane_formats, \ 736 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 737 .rotation_cfg = rot_cfg, \ 738 } 739 740#define _DMA_SBLK(num, sdma_pri) \ 741 { \ 742 .maxdwnscale = SSPP_UNITY_SCALE, \ 743 .maxupscale = SSPP_UNITY_SCALE, \ 744 .smart_dma_priority = sdma_pri, \ 745 .src_blk = {.name = STRCAT("sspp_src_", num), \ 746 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 747 .format_list = plane_formats, \ 748 .num_formats = ARRAY_SIZE(plane_formats), \ 749 .virt_format_list = plane_formats, \ 750 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 751 } 752 753static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 = 754 _VIG_SBLK("0", 0, DPU_SSPP_SCALER_QSEED3); 755static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 = 756 _VIG_SBLK("1", 0, DPU_SSPP_SCALER_QSEED3); 757static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 = 758 _VIG_SBLK("2", 0, DPU_SSPP_SCALER_QSEED3); 759static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 = 760 _VIG_SBLK("3", 0, DPU_SSPP_SCALER_QSEED3); 761 762static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { 763 .rot_maxheight = 1088, 764 .rot_num_formats = ARRAY_SIZE(rotation_v2_formats), 765 .rot_format_list = rotation_v2_formats, 766}; 767 768static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = 769 _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3); 770static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = 771 _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3); 772static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = 773 _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3); 774static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = 775 _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3); 776 777static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1); 778static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2); 779static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3); 780static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4); 781 782#define SSPP_BLK(_name, _id, _base, _features, \ 783 _sblk, _xinid, _type, _clkctrl) \ 784 { \ 785 .name = _name, .id = _id, \ 786 .base = _base, .len = 0x1c8, \ 787 .features = _features, \ 788 .sblk = &_sblk, \ 789 .xin_id = _xinid, \ 790 .type = _type, \ 791 .clk_ctrl = _clkctrl \ 792 } 793 794static const struct dpu_sspp_cfg msm8998_sspp[] = { 795 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_MSM8998_MASK, 796 msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 797 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_MSM8998_MASK, 798 msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 799 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_MSM8998_MASK, 800 msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 801 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_MSM8998_MASK, 802 msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 803 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_MSM8998_MASK, 804 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 805 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_MSM8998_MASK, 806 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 807 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_MSM8998_MASK, 808 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), 809 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_MSM8998_MASK, 810 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), 811}; 812 813static const struct dpu_sspp_cfg sdm845_sspp[] = { 814 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK, 815 sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 816 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK, 817 sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 818 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK, 819 sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 820 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK, 821 sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 822 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 823 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 824 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, 825 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 826 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, 827 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), 828 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, 829 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), 830}; 831 832static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = 833 _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4); 834 835static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = 836 _VIG_SBLK_ROT("0", 4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2); 837 838static const struct dpu_sspp_cfg sc7180_sspp[] = { 839 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, 840 sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 841 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 842 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 843 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, 844 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), 845 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, 846 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), 847}; 848 849static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = 850 _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE); 851static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = 852 _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE); 853static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 = 854 _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE); 855static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 = 856 _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE); 857 858static const struct dpu_sspp_cfg sm8250_sspp[] = { 859 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK, 860 sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 861 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK, 862 sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 863 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK, 864 sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 865 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK, 866 sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 867 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 868 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 869 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, 870 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 871 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, 872 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), 873 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, 874 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), 875}; 876 877static const struct dpu_sspp_cfg sc7280_sspp[] = { 878 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK, 879 sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 880 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 881 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 882 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, 883 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), 884 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, 885 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), 886}; 887 888 889#define _VIG_SBLK_NOSCALE(num, sdma_pri) \ 890 { \ 891 .maxdwnscale = SSPP_UNITY_SCALE, \ 892 .maxupscale = SSPP_UNITY_SCALE, \ 893 .smart_dma_priority = sdma_pri, \ 894 .src_blk = {.name = STRCAT("sspp_src_", num), \ 895 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 896 .format_list = plane_formats_yuv, \ 897 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 898 .virt_format_list = plane_formats, \ 899 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 900 } 901 902static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0", 2); 903static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1); 904 905static const struct dpu_sspp_cfg qcm2290_sspp[] = { 906 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK, 907 qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 908 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 909 qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 910}; 911 912/************************************************************* 913 * MIXER sub blocks config 914 *************************************************************/ 915 916#define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \ 917 { \ 918 .name = _name, .id = _id, \ 919 .base = _base, .len = 0x320, \ 920 .features = _fmask, \ 921 .sblk = _sblk, \ 922 .pingpong = _pp, \ 923 .lm_pair_mask = (1 << _lmpair), \ 924 .dspp = _dspp \ 925 } 926 927/* MSM8998 */ 928 929static const struct dpu_lm_sub_blks msm8998_lm_sblk = { 930 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 931 .maxblendstages = 7, /* excluding base layer */ 932 .blendstage_base = { /* offsets relative to mixer base */ 933 0x20, 0x50, 0x80, 0xb0, 0x230, 934 0x260, 0x290 935 }, 936}; 937 938static const struct dpu_lm_cfg msm8998_lm[] = { 939 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 940 &msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0), 941 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 942 &msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1), 943 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 944 &msm8998_lm_sblk, PINGPONG_2, LM_0, 0), 945 LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, 946 &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), 947 LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, 948 &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), 949 LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, 950 &msm8998_lm_sblk, PINGPONG_3, LM_1, 0), 951}; 952 953/* SDM845 */ 954 955static const struct dpu_lm_sub_blks sdm845_lm_sblk = { 956 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 957 .maxblendstages = 11, /* excluding base layer */ 958 .blendstage_base = { /* offsets relative to mixer base */ 959 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 960 0xb0, 0xc8, 0xe0, 0xf8, 0x110 961 }, 962}; 963 964static const struct dpu_lm_cfg sdm845_lm[] = { 965 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 966 &sdm845_lm_sblk, PINGPONG_0, LM_1, 0), 967 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 968 &sdm845_lm_sblk, PINGPONG_1, LM_0, 0), 969 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 970 &sdm845_lm_sblk, PINGPONG_2, LM_5, 0), 971 LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK, 972 &sdm845_lm_sblk, PINGPONG_MAX, 0, 0), 973 LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK, 974 &sdm845_lm_sblk, PINGPONG_MAX, 0, 0), 975 LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, 976 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), 977}; 978 979/* SC7180 */ 980 981static const struct dpu_lm_sub_blks sc7180_lm_sblk = { 982 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 983 .maxblendstages = 7, /* excluding base layer */ 984 .blendstage_base = { /* offsets relative to mixer base */ 985 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 986 }, 987}; 988 989static const struct dpu_lm_cfg sc7180_lm[] = { 990 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK, 991 &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 992 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SC7180_MASK, 993 &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), 994}; 995 996/* SM8150 */ 997 998static const struct dpu_lm_cfg sm8150_lm[] = { 999 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 1000 &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 1001 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 1002 &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), 1003 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 1004 &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), 1005 LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, 1006 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), 1007 LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, 1008 &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), 1009 LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, 1010 &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), 1011}; 1012 1013static const struct dpu_lm_cfg sc7280_lm[] = { 1014 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK, 1015 &sc7180_lm_sblk, PINGPONG_0, 0, 0), 1016 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SC7180_MASK, 1017 &sc7180_lm_sblk, PINGPONG_2, LM_3, 0), 1018 LM_BLK("lm_3", LM_3, 0x47000, MIXER_SC7180_MASK, 1019 &sc7180_lm_sblk, PINGPONG_3, LM_2, 0), 1020}; 1021 1022/* QCM2290 */ 1023 1024static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { 1025 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 1026 .maxblendstages = 4, /* excluding base layer */ 1027 .blendstage_base = { /* offsets relative to mixer base */ 1028 0x20, 0x38, 0x50, 0x68 1029 }, 1030}; 1031 1032static const struct dpu_lm_cfg qcm2290_lm[] = { 1033 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK, 1034 &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0), 1035}; 1036 1037/************************************************************* 1038 * DSPP sub blocks config 1039 *************************************************************/ 1040static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { 1041 .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, 1042 .len = 0x90, .version = 0x10007}, 1043 .gc = { .id = DPU_DSPP_GC, .base = 0x17c0, 1044 .len = 0x90, .version = 0x10007}, 1045}; 1046 1047static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = { 1048 .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, 1049 .len = 0x90, .version = 0x10000}, 1050}; 1051 1052static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = { 1053 .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, 1054 .len = 0x90, .version = 0x40000}, 1055}; 1056 1057#define DSPP_BLK(_name, _id, _base, _mask, _sblk) \ 1058 {\ 1059 .name = _name, .id = _id, \ 1060 .base = _base, .len = 0x1800, \ 1061 .features = _mask, \ 1062 .sblk = _sblk \ 1063 } 1064 1065static const struct dpu_dspp_cfg msm8998_dspp[] = { 1066 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK, 1067 &msm8998_dspp_sblk), 1068 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_MSM8998_MASK, 1069 &msm8998_dspp_sblk), 1070}; 1071 1072static const struct dpu_dspp_cfg sc7180_dspp[] = { 1073 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 1074 &sc7180_dspp_sblk), 1075}; 1076 1077static const struct dpu_dspp_cfg sm8150_dspp[] = { 1078 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 1079 &sm8150_dspp_sblk), 1080 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 1081 &sm8150_dspp_sblk), 1082 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 1083 &sm8150_dspp_sblk), 1084 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 1085 &sm8150_dspp_sblk), 1086}; 1087 1088static const struct dpu_dspp_cfg qcm2290_dspp[] = { 1089 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 1090 &sm8150_dspp_sblk), 1091}; 1092 1093/************************************************************* 1094 * PINGPONG sub blocks config 1095 *************************************************************/ 1096static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = { 1097 .te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0, 1098 .version = 0x1}, 1099 .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, 1100 .len = 0x20, .version = 0x10000}, 1101}; 1102 1103static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { 1104 .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, 1105 .len = 0x20, .version = 0x10000}, 1106}; 1107 1108static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { 1109 .dither = {.id = DPU_PINGPONG_DITHER, .base = 0xe0, 1110 .len = 0x20, .version = 0x20000}, 1111}; 1112 1113#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ 1114 {\ 1115 .name = _name, .id = _id, \ 1116 .base = _base, .len = 0xd4, \ 1117 .features = PINGPONG_SDM845_SPLIT_MASK, \ 1118 .merge_3d = _merge_3d, \ 1119 .sblk = &_sblk, \ 1120 .intr_done = _done, \ 1121 .intr_rdptr = _rdptr, \ 1122 } 1123#define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ 1124 {\ 1125 .name = _name, .id = _id, \ 1126 .base = _base, .len = 0xd4, \ 1127 .features = PINGPONG_SDM845_MASK, \ 1128 .merge_3d = _merge_3d, \ 1129 .sblk = &_sblk, \ 1130 .intr_done = _done, \ 1131 .intr_rdptr = _rdptr, \ 1132 } 1133 1134static const struct dpu_pingpong_cfg sdm845_pp[] = { 1135 PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, 1136 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 1137 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 1138 PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, 1139 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 1140 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 1141 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk, 1142 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 1143 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), 1144 PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk, 1145 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 1146 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), 1147}; 1148 1149static struct dpu_pingpong_cfg sc7180_pp[] = { 1150 PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1), 1151 PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1), 1152}; 1153 1154static const struct dpu_pingpong_cfg sm8150_pp[] = { 1155 PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te, 1156 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 1157 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 1158 PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te, 1159 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 1160 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 1161 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk, 1162 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 1163 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), 1164 PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk, 1165 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 1166 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), 1167 PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk, 1168 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 1169 -1), 1170 PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk, 1171 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 1172 -1), 1173}; 1174 1175static struct dpu_pingpong_cfg qcm2290_pp[] = { 1176 PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk, 1177 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 1178 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 1179}; 1180 1181/************************************************************* 1182 * MERGE_3D sub blocks config 1183 *************************************************************/ 1184#define MERGE_3D_BLK(_name, _id, _base) \ 1185 {\ 1186 .name = _name, .id = _id, \ 1187 .base = _base, .len = 0x100, \ 1188 .features = MERGE_3D_SM8150_MASK, \ 1189 .sblk = NULL \ 1190 } 1191 1192static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { 1193 MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000), 1194 MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100), 1195 MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), 1196}; 1197 1198static const struct dpu_pingpong_cfg sc7280_pp[] = { 1199 PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1), 1200 PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), 1201 PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1), 1202 PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1), 1203}; 1204 1205/************************************************************* 1206 * DSC sub blocks config 1207 *************************************************************/ 1208#define DSC_BLK(_name, _id, _base) \ 1209 {\ 1210 .name = _name, .id = _id, \ 1211 .base = _base, .len = 0x140, \ 1212 .features = 0, \ 1213 } 1214 1215static struct dpu_dsc_cfg sdm845_dsc[] = { 1216 DSC_BLK("dsc_0", DSC_0, 0x80000), 1217 DSC_BLK("dsc_1", DSC_1, 0x80400), 1218 DSC_BLK("dsc_2", DSC_2, 0x80800), 1219 DSC_BLK("dsc_3", DSC_3, 0x80c00), 1220}; 1221 1222/************************************************************* 1223 * INTF sub blocks config 1224 *************************************************************/ 1225#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \ 1226 {\ 1227 .name = _name, .id = _id, \ 1228 .base = _base, .len = 0x280, \ 1229 .features = _features, \ 1230 .type = _type, \ 1231 .controller_id = _ctrl_id, \ 1232 .prog_fetch_lines_worst_case = _progfetch, \ 1233 .intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \ 1234 .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \ 1235 } 1236 1237static const struct dpu_intf_cfg msm8998_intf[] = { 1238 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 1239 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 1240 INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 1241 INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 1242}; 1243 1244static const struct dpu_intf_cfg sdm845_intf[] = { 1245 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 1246 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 1247 INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 1248 INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 1249}; 1250 1251static const struct dpu_intf_cfg sc7180_intf[] = { 1252 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 1253 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 1254}; 1255 1256static const struct dpu_intf_cfg sm8150_intf[] = { 1257 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 1258 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 1259 INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 1260 INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 1261}; 1262 1263static const struct dpu_intf_cfg sc7280_intf[] = { 1264 INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 1265 INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 1266 INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), 1267}; 1268 1269static const struct dpu_intf_cfg sc8180x_intf[] = { 1270 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 1271 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 1272 INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 1273 /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */ 1274 INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 1275 INTF_BLK("intf_4", INTF_4, 0x6C000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21), 1276 INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23), 1277}; 1278 1279static const struct dpu_intf_cfg qcm2290_intf[] = { 1280 INTF_BLK("intf_0", INTF_0, 0x00000, INTF_NONE, 0, 0, 0, 0, 0, 0), 1281 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 1282}; 1283 1284/************************************************************* 1285 * Writeback blocks config 1286 *************************************************************/ 1287#define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \ 1288 __xin_id, vbif_id, _reg, _wb_done_bit) \ 1289 { \ 1290 .name = _name, .id = _id, \ 1291 .base = _base, .len = 0x2c8, \ 1292 .features = _features, \ 1293 .format_list = wb2_formats, \ 1294 .num_formats = ARRAY_SIZE(wb2_formats), \ 1295 .clk_ctrl = _clk_ctrl, \ 1296 .xin_id = __xin_id, \ 1297 .vbif_idx = vbif_id, \ 1298 .maxlinewidth = DEFAULT_DPU_LINE_WIDTH, \ 1299 .intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \ 1300 } 1301 1302static const struct dpu_wb_cfg sm8250_wb[] = { 1303 WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6, 1304 VBIF_RT, MDP_SSPP_TOP0_INTR, 4), 1305}; 1306 1307/************************************************************* 1308 * VBIF sub blocks config 1309 *************************************************************/ 1310/* VBIF QOS remap */ 1311static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2}; 1312static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1}; 1313static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6}; 1314static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; 1315 1316static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { 1317 { 1318 .pps = 1088 * 1920 * 30, 1319 .ot_limit = 2, 1320 }, 1321 { 1322 .pps = 1088 * 1920 * 60, 1323 .ot_limit = 6, 1324 }, 1325 { 1326 .pps = 3840 * 2160 * 30, 1327 .ot_limit = 16, 1328 }, 1329}; 1330 1331static const struct dpu_vbif_cfg msm8998_vbif[] = { 1332 { 1333 .name = "vbif_0", .id = VBIF_0, 1334 .base = 0, .len = 0x1040, 1335 .default_ot_rd_limit = 32, 1336 .default_ot_wr_limit = 32, 1337 .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), 1338 .xin_halt_timeout = 0x4000, 1339 .dynamic_ot_rd_tbl = { 1340 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 1341 .cfg = msm8998_ot_rdwr_cfg, 1342 }, 1343 .dynamic_ot_wr_tbl = { 1344 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 1345 .cfg = msm8998_ot_rdwr_cfg, 1346 }, 1347 .qos_rt_tbl = { 1348 .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl), 1349 .priority_lvl = msm8998_rt_pri_lvl, 1350 }, 1351 .qos_nrt_tbl = { 1352 .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl), 1353 .priority_lvl = msm8998_nrt_pri_lvl, 1354 }, 1355 .memtype_count = 14, 1356 .memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}, 1357 }, 1358}; 1359 1360static const struct dpu_vbif_cfg sdm845_vbif[] = { 1361 { 1362 .name = "vbif_0", .id = VBIF_0, 1363 .base = 0, .len = 0x1040, 1364 .features = BIT(DPU_VBIF_QOS_REMAP), 1365 .xin_halt_timeout = 0x4000, 1366 .qos_rt_tbl = { 1367 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 1368 .priority_lvl = sdm845_rt_pri_lvl, 1369 }, 1370 .qos_nrt_tbl = { 1371 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 1372 .priority_lvl = sdm845_nrt_pri_lvl, 1373 }, 1374 .memtype_count = 14, 1375 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 1376 }, 1377}; 1378 1379static const struct dpu_reg_dma_cfg sdm845_regdma = { 1380 .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c 1381}; 1382 1383static const struct dpu_reg_dma_cfg sm8150_regdma = { 1384 .base = 0x0, .version = 0x00010001, .trigger_sel_off = 0x119c 1385}; 1386 1387static const struct dpu_reg_dma_cfg sm8250_regdma = { 1388 .base = 0x0, 1389 .version = 0x00010002, 1390 .trigger_sel_off = 0x119c, 1391 .xin_id = 7, 1392 .clk_ctrl = DPU_CLK_CTRL_REG_DMA, 1393}; 1394 1395/************************************************************* 1396 * PERF data config 1397 *************************************************************/ 1398 1399/* SSPP QOS LUTs */ 1400static const struct dpu_qos_lut_entry msm8998_qos_linear[] = { 1401 {.fl = 4, .lut = 0x1b}, 1402 {.fl = 5, .lut = 0x5b}, 1403 {.fl = 6, .lut = 0x15b}, 1404 {.fl = 7, .lut = 0x55b}, 1405 {.fl = 8, .lut = 0x155b}, 1406 {.fl = 9, .lut = 0x555b}, 1407 {.fl = 10, .lut = 0x1555b}, 1408 {.fl = 11, .lut = 0x5555b}, 1409 {.fl = 12, .lut = 0x15555b}, 1410 {.fl = 13, .lut = 0x55555b}, 1411 {.fl = 14, .lut = 0}, 1412 {.fl = 1, .lut = 0x1b}, 1413 {.fl = 0, .lut = 0} 1414}; 1415 1416static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { 1417 {.fl = 4, .lut = 0x357}, 1418 {.fl = 5, .lut = 0x3357}, 1419 {.fl = 6, .lut = 0x23357}, 1420 {.fl = 7, .lut = 0x223357}, 1421 {.fl = 8, .lut = 0x2223357}, 1422 {.fl = 9, .lut = 0x22223357}, 1423 {.fl = 10, .lut = 0x222223357}, 1424 {.fl = 11, .lut = 0x2222223357}, 1425 {.fl = 12, .lut = 0x22222223357}, 1426 {.fl = 13, .lut = 0x222222223357}, 1427 {.fl = 14, .lut = 0x1222222223357}, 1428 {.fl = 0, .lut = 0x11222222223357} 1429}; 1430 1431static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = { 1432 {.fl = 10, .lut = 0x1aaff}, 1433 {.fl = 11, .lut = 0x5aaff}, 1434 {.fl = 12, .lut = 0x15aaff}, 1435 {.fl = 13, .lut = 0x55aaff}, 1436 {.fl = 1, .lut = 0x1aaff}, 1437 {.fl = 0, .lut = 0}, 1438}; 1439 1440static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { 1441 {.fl = 0, .lut = 0x0011222222335777}, 1442}; 1443 1444static const struct dpu_qos_lut_entry sm8150_qos_linear[] = { 1445 {.fl = 0, .lut = 0x0011222222223357 }, 1446}; 1447 1448static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = { 1449 {.fl = 4, .lut = 0x0000000000000357 }, 1450}; 1451 1452static const struct dpu_qos_lut_entry qcm2290_qos_linear[] = { 1453 {.fl = 0, .lut = 0x0011222222335777}, 1454}; 1455 1456static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = { 1457 {.fl = 10, .lut = 0x344556677}, 1458 {.fl = 11, .lut = 0x3344556677}, 1459 {.fl = 12, .lut = 0x23344556677}, 1460 {.fl = 13, .lut = 0x223344556677}, 1461 {.fl = 14, .lut = 0x1223344556677}, 1462 {.fl = 0, .lut = 0x112233344556677}, 1463}; 1464 1465static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { 1466 {.fl = 0, .lut = 0x0011223344556677}, 1467}; 1468 1469static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = { 1470 {.fl = 10, .lut = 0x0000000344556677}, 1471}; 1472 1473static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = { 1474 {.fl = 0, .lut = 0x0}, 1475}; 1476 1477static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = { 1478 {.fl = 0, .lut = 0x0}, 1479}; 1480 1481static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { 1482 {.fl = 0, .lut = 0x0}, 1483}; 1484 1485static const struct dpu_perf_cfg msm8998_perf_data = { 1486 .max_bw_low = 6700000, 1487 .max_bw_high = 6700000, 1488 .min_core_ib = 2400000, 1489 .min_llcc_ib = 800000, 1490 .min_dram_ib = 800000, 1491 .undersized_prefill_lines = 2, 1492 .xtra_prefill_lines = 2, 1493 .dest_scale_prefill_lines = 3, 1494 .macrotile_prefill_lines = 4, 1495 .yuv_nv12_prefill_lines = 8, 1496 .linear_prefill_lines = 1, 1497 .downscaling_prefill_lines = 1, 1498 .amortizable_threshold = 25, 1499 .min_prefill_lines = 25, 1500 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 1501 .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, 1502 .qos_lut_tbl = { 1503 {.nentry = ARRAY_SIZE(msm8998_qos_linear), 1504 .entries = msm8998_qos_linear 1505 }, 1506 {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), 1507 .entries = msm8998_qos_macrotile 1508 }, 1509 {.nentry = ARRAY_SIZE(msm8998_qos_nrt), 1510 .entries = msm8998_qos_nrt 1511 }, 1512 }, 1513 .cdp_cfg = { 1514 {.rd_enable = 1, .wr_enable = 1}, 1515 {.rd_enable = 1, .wr_enable = 0} 1516 }, 1517 .clk_inefficiency_factor = 200, 1518 .bw_inefficiency_factor = 120, 1519}; 1520 1521static const struct dpu_perf_cfg sdm845_perf_data = { 1522 .max_bw_low = 6800000, 1523 .max_bw_high = 6800000, 1524 .min_core_ib = 2400000, 1525 .min_llcc_ib = 800000, 1526 .min_dram_ib = 800000, 1527 .undersized_prefill_lines = 2, 1528 .xtra_prefill_lines = 2, 1529 .dest_scale_prefill_lines = 3, 1530 .macrotile_prefill_lines = 4, 1531 .yuv_nv12_prefill_lines = 8, 1532 .linear_prefill_lines = 1, 1533 .downscaling_prefill_lines = 1, 1534 .amortizable_threshold = 25, 1535 .min_prefill_lines = 24, 1536 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 1537 .safe_lut_tbl = {0xfff0, 0xf000, 0xffff}, 1538 .qos_lut_tbl = { 1539 {.nentry = ARRAY_SIZE(sdm845_qos_linear), 1540 .entries = sdm845_qos_linear 1541 }, 1542 {.nentry = ARRAY_SIZE(sdm845_qos_macrotile), 1543 .entries = sdm845_qos_macrotile 1544 }, 1545 {.nentry = ARRAY_SIZE(sdm845_qos_nrt), 1546 .entries = sdm845_qos_nrt 1547 }, 1548 }, 1549 .cdp_cfg = { 1550 {.rd_enable = 1, .wr_enable = 1}, 1551 {.rd_enable = 1, .wr_enable = 0} 1552 }, 1553 .clk_inefficiency_factor = 105, 1554 .bw_inefficiency_factor = 120, 1555}; 1556 1557static const struct dpu_perf_cfg sc7180_perf_data = { 1558 .max_bw_low = 6800000, 1559 .max_bw_high = 6800000, 1560 .min_core_ib = 2400000, 1561 .min_llcc_ib = 800000, 1562 .min_dram_ib = 1600000, 1563 .min_prefill_lines = 24, 1564 .danger_lut_tbl = {0xff, 0xffff, 0x0}, 1565 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, 1566 .qos_lut_tbl = { 1567 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 1568 .entries = sc7180_qos_linear 1569 }, 1570 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 1571 .entries = sc7180_qos_macrotile 1572 }, 1573 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 1574 .entries = sc7180_qos_nrt 1575 }, 1576 }, 1577 .cdp_cfg = { 1578 {.rd_enable = 1, .wr_enable = 1}, 1579 {.rd_enable = 1, .wr_enable = 0} 1580 }, 1581 .clk_inefficiency_factor = 105, 1582 .bw_inefficiency_factor = 120, 1583}; 1584 1585static const struct dpu_perf_cfg sm8150_perf_data = { 1586 .max_bw_low = 12800000, 1587 .max_bw_high = 12800000, 1588 .min_core_ib = 2400000, 1589 .min_llcc_ib = 800000, 1590 .min_dram_ib = 800000, 1591 .min_prefill_lines = 24, 1592 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 1593 .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, 1594 .qos_lut_tbl = { 1595 {.nentry = ARRAY_SIZE(sm8150_qos_linear), 1596 .entries = sm8150_qos_linear 1597 }, 1598 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 1599 .entries = sc7180_qos_macrotile 1600 }, 1601 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 1602 .entries = sc7180_qos_nrt 1603 }, 1604 /* TODO: macrotile-qseed is different from macrotile */ 1605 }, 1606 .cdp_cfg = { 1607 {.rd_enable = 1, .wr_enable = 1}, 1608 {.rd_enable = 1, .wr_enable = 0} 1609 }, 1610 .clk_inefficiency_factor = 105, 1611 .bw_inefficiency_factor = 120, 1612}; 1613 1614static const struct dpu_perf_cfg sc8180x_perf_data = { 1615 .max_bw_low = 9600000, 1616 .max_bw_high = 9600000, 1617 .min_core_ib = 2400000, 1618 .min_llcc_ib = 800000, 1619 .min_dram_ib = 800000, 1620 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 1621 .qos_lut_tbl = { 1622 {.nentry = ARRAY_SIZE(sc8180x_qos_linear), 1623 .entries = sc8180x_qos_linear 1624 }, 1625 {.nentry = ARRAY_SIZE(sc8180x_qos_macrotile), 1626 .entries = sc8180x_qos_macrotile 1627 }, 1628 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 1629 .entries = sc7180_qos_nrt 1630 }, 1631 /* TODO: macrotile-qseed is different from macrotile */ 1632 }, 1633 .cdp_cfg = { 1634 {.rd_enable = 1, .wr_enable = 1}, 1635 {.rd_enable = 1, .wr_enable = 0} 1636 }, 1637 .clk_inefficiency_factor = 105, 1638 .bw_inefficiency_factor = 120, 1639}; 1640 1641static const struct dpu_perf_cfg sm8250_perf_data = { 1642 .max_bw_low = 13700000, 1643 .max_bw_high = 16600000, 1644 .min_core_ib = 4800000, 1645 .min_llcc_ib = 0, 1646 .min_dram_ib = 800000, 1647 .min_prefill_lines = 35, 1648 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 1649 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, 1650 .qos_lut_tbl = { 1651 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 1652 .entries = sc7180_qos_linear 1653 }, 1654 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 1655 .entries = sc7180_qos_macrotile 1656 }, 1657 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 1658 .entries = sc7180_qos_nrt 1659 }, 1660 /* TODO: macrotile-qseed is different from macrotile */ 1661 }, 1662 .cdp_cfg = { 1663 {.rd_enable = 1, .wr_enable = 1}, 1664 {.rd_enable = 1, .wr_enable = 0} 1665 }, 1666 .clk_inefficiency_factor = 105, 1667 .bw_inefficiency_factor = 120, 1668}; 1669 1670static const struct dpu_perf_cfg sc7280_perf_data = { 1671 .max_bw_low = 4700000, 1672 .max_bw_high = 8800000, 1673 .min_core_ib = 2500000, 1674 .min_llcc_ib = 0, 1675 .min_dram_ib = 1600000, 1676 .min_prefill_lines = 24, 1677 .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 1678 .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, 1679 .qos_lut_tbl = { 1680 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 1681 .entries = sc7180_qos_macrotile 1682 }, 1683 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 1684 .entries = sc7180_qos_macrotile 1685 }, 1686 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 1687 .entries = sc7180_qos_nrt 1688 }, 1689 }, 1690 .cdp_cfg = { 1691 {.rd_enable = 1, .wr_enable = 1}, 1692 {.rd_enable = 1, .wr_enable = 0} 1693 }, 1694 .clk_inefficiency_factor = 105, 1695 .bw_inefficiency_factor = 120, 1696}; 1697 1698static const struct dpu_perf_cfg qcm2290_perf_data = { 1699 .max_bw_low = 2700000, 1700 .max_bw_high = 2700000, 1701 .min_core_ib = 1300000, 1702 .min_llcc_ib = 0, 1703 .min_dram_ib = 1600000, 1704 .min_prefill_lines = 24, 1705 .danger_lut_tbl = {0xff, 0x0, 0x0}, 1706 .safe_lut_tbl = {0xfff0, 0x0, 0x0}, 1707 .qos_lut_tbl = { 1708 {.nentry = ARRAY_SIZE(qcm2290_qos_linear), 1709 .entries = qcm2290_qos_linear 1710 }, 1711 }, 1712 .cdp_cfg = { 1713 {.rd_enable = 1, .wr_enable = 1}, 1714 {.rd_enable = 1, .wr_enable = 0} 1715 }, 1716 .clk_inefficiency_factor = 105, 1717 .bw_inefficiency_factor = 120, 1718}; 1719/************************************************************* 1720 * Hardware catalog init 1721 *************************************************************/ 1722 1723/* 1724 * msm8998_cfg_init(): populate sdm845 dpu sub-blocks reg offsets 1725 * and instance counts. 1726 */ 1727static void msm8998_cfg_init(struct dpu_mdss_cfg *dpu_cfg) 1728{ 1729 *dpu_cfg = (struct dpu_mdss_cfg){ 1730 .caps = &msm8998_dpu_caps, 1731 .mdp_count = ARRAY_SIZE(msm8998_mdp), 1732 .mdp = msm8998_mdp, 1733 .ctl_count = ARRAY_SIZE(msm8998_ctl), 1734 .ctl = msm8998_ctl, 1735 .sspp_count = ARRAY_SIZE(msm8998_sspp), 1736 .sspp = msm8998_sspp, 1737 .mixer_count = ARRAY_SIZE(msm8998_lm), 1738 .mixer = msm8998_lm, 1739 .dspp_count = ARRAY_SIZE(msm8998_dspp), 1740 .dspp = msm8998_dspp, 1741 .pingpong_count = ARRAY_SIZE(sdm845_pp), 1742 .pingpong = sdm845_pp, 1743 .intf_count = ARRAY_SIZE(msm8998_intf), 1744 .intf = msm8998_intf, 1745 .vbif_count = ARRAY_SIZE(msm8998_vbif), 1746 .vbif = msm8998_vbif, 1747 .reg_dma_count = 0, 1748 .perf = msm8998_perf_data, 1749 .mdss_irqs = IRQ_SM8250_MASK, 1750 }; 1751} 1752 1753/* 1754 * sdm845_cfg_init(): populate sdm845 dpu sub-blocks reg offsets 1755 * and instance counts. 1756 */ 1757static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg) 1758{ 1759 *dpu_cfg = (struct dpu_mdss_cfg){ 1760 .caps = &sdm845_dpu_caps, 1761 .mdp_count = ARRAY_SIZE(sdm845_mdp), 1762 .mdp = sdm845_mdp, 1763 .ctl_count = ARRAY_SIZE(sdm845_ctl), 1764 .ctl = sdm845_ctl, 1765 .sspp_count = ARRAY_SIZE(sdm845_sspp), 1766 .sspp = sdm845_sspp, 1767 .mixer_count = ARRAY_SIZE(sdm845_lm), 1768 .mixer = sdm845_lm, 1769 .pingpong_count = ARRAY_SIZE(sdm845_pp), 1770 .pingpong = sdm845_pp, 1771 .dsc_count = ARRAY_SIZE(sdm845_dsc), 1772 .dsc = sdm845_dsc, 1773 .intf_count = ARRAY_SIZE(sdm845_intf), 1774 .intf = sdm845_intf, 1775 .vbif_count = ARRAY_SIZE(sdm845_vbif), 1776 .vbif = sdm845_vbif, 1777 .reg_dma_count = 1, 1778 .dma_cfg = sdm845_regdma, 1779 .perf = sdm845_perf_data, 1780 .mdss_irqs = IRQ_SDM845_MASK, 1781 }; 1782} 1783 1784/* 1785 * sc7180_cfg_init(): populate sc7180 dpu sub-blocks reg offsets 1786 * and instance counts. 1787 */ 1788static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg) 1789{ 1790 *dpu_cfg = (struct dpu_mdss_cfg){ 1791 .caps = &sc7180_dpu_caps, 1792 .mdp_count = ARRAY_SIZE(sc7180_mdp), 1793 .mdp = sc7180_mdp, 1794 .ctl_count = ARRAY_SIZE(sc7180_ctl), 1795 .ctl = sc7180_ctl, 1796 .sspp_count = ARRAY_SIZE(sc7180_sspp), 1797 .sspp = sc7180_sspp, 1798 .mixer_count = ARRAY_SIZE(sc7180_lm), 1799 .mixer = sc7180_lm, 1800 .dspp_count = ARRAY_SIZE(sc7180_dspp), 1801 .dspp = sc7180_dspp, 1802 .pingpong_count = ARRAY_SIZE(sc7180_pp), 1803 .pingpong = sc7180_pp, 1804 .intf_count = ARRAY_SIZE(sc7180_intf), 1805 .intf = sc7180_intf, 1806 .vbif_count = ARRAY_SIZE(sdm845_vbif), 1807 .vbif = sdm845_vbif, 1808 .reg_dma_count = 1, 1809 .dma_cfg = sdm845_regdma, 1810 .perf = sc7180_perf_data, 1811 .mdss_irqs = IRQ_SC7180_MASK, 1812 }; 1813} 1814 1815/* 1816 * sm8150_cfg_init(): populate sm8150 dpu sub-blocks reg offsets 1817 * and instance counts. 1818 */ 1819static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg) 1820{ 1821 *dpu_cfg = (struct dpu_mdss_cfg){ 1822 .caps = &sm8150_dpu_caps, 1823 .mdp_count = ARRAY_SIZE(sdm845_mdp), 1824 .mdp = sdm845_mdp, 1825 .ctl_count = ARRAY_SIZE(sm8150_ctl), 1826 .ctl = sm8150_ctl, 1827 .sspp_count = ARRAY_SIZE(sdm845_sspp), 1828 .sspp = sdm845_sspp, 1829 .mixer_count = ARRAY_SIZE(sm8150_lm), 1830 .mixer = sm8150_lm, 1831 .dspp_count = ARRAY_SIZE(sm8150_dspp), 1832 .dspp = sm8150_dspp, 1833 .pingpong_count = ARRAY_SIZE(sm8150_pp), 1834 .pingpong = sm8150_pp, 1835 .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), 1836 .merge_3d = sm8150_merge_3d, 1837 .intf_count = ARRAY_SIZE(sm8150_intf), 1838 .intf = sm8150_intf, 1839 .vbif_count = ARRAY_SIZE(sdm845_vbif), 1840 .vbif = sdm845_vbif, 1841 .reg_dma_count = 1, 1842 .dma_cfg = sm8150_regdma, 1843 .perf = sm8150_perf_data, 1844 .mdss_irqs = IRQ_SDM845_MASK, 1845 }; 1846} 1847 1848/* 1849 * sc8180x_cfg_init(): populate sc8180 dpu sub-blocks reg offsets 1850 * and instance counts. 1851 */ 1852static void sc8180x_cfg_init(struct dpu_mdss_cfg *dpu_cfg) 1853{ 1854 *dpu_cfg = (struct dpu_mdss_cfg){ 1855 .caps = &sc8180x_dpu_caps, 1856 .mdp_count = ARRAY_SIZE(sc8180x_mdp), 1857 .mdp = sc8180x_mdp, 1858 .ctl_count = ARRAY_SIZE(sm8150_ctl), 1859 .ctl = sm8150_ctl, 1860 .sspp_count = ARRAY_SIZE(sdm845_sspp), 1861 .sspp = sdm845_sspp, 1862 .mixer_count = ARRAY_SIZE(sm8150_lm), 1863 .mixer = sm8150_lm, 1864 .pingpong_count = ARRAY_SIZE(sm8150_pp), 1865 .pingpong = sm8150_pp, 1866 .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), 1867 .merge_3d = sm8150_merge_3d, 1868 .intf_count = ARRAY_SIZE(sc8180x_intf), 1869 .intf = sc8180x_intf, 1870 .vbif_count = ARRAY_SIZE(sdm845_vbif), 1871 .vbif = sdm845_vbif, 1872 .reg_dma_count = 1, 1873 .dma_cfg = sm8150_regdma, 1874 .perf = sc8180x_perf_data, 1875 .mdss_irqs = IRQ_SC8180X_MASK, 1876 }; 1877} 1878 1879/* 1880 * sm8250_cfg_init(): populate sm8250 dpu sub-blocks reg offsets 1881 * and instance counts. 1882 */ 1883static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg) 1884{ 1885 *dpu_cfg = (struct dpu_mdss_cfg){ 1886 .caps = &sm8250_dpu_caps, 1887 .mdp_count = ARRAY_SIZE(sm8250_mdp), 1888 .mdp = sm8250_mdp, 1889 .ctl_count = ARRAY_SIZE(sm8150_ctl), 1890 .ctl = sm8150_ctl, 1891 .sspp_count = ARRAY_SIZE(sm8250_sspp), 1892 .sspp = sm8250_sspp, 1893 .mixer_count = ARRAY_SIZE(sm8150_lm), 1894 .mixer = sm8150_lm, 1895 .dspp_count = ARRAY_SIZE(sm8150_dspp), 1896 .dspp = sm8150_dspp, 1897 .pingpong_count = ARRAY_SIZE(sm8150_pp), 1898 .pingpong = sm8150_pp, 1899 .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), 1900 .merge_3d = sm8150_merge_3d, 1901 .intf_count = ARRAY_SIZE(sm8150_intf), 1902 .intf = sm8150_intf, 1903 .vbif_count = ARRAY_SIZE(sdm845_vbif), 1904 .vbif = sdm845_vbif, 1905 .wb_count = ARRAY_SIZE(sm8250_wb), 1906 .wb = sm8250_wb, 1907 .reg_dma_count = 1, 1908 .dma_cfg = sm8250_regdma, 1909 .perf = sm8250_perf_data, 1910 .mdss_irqs = IRQ_SM8250_MASK, 1911 }; 1912} 1913 1914static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg) 1915{ 1916 *dpu_cfg = (struct dpu_mdss_cfg){ 1917 .caps = &sc7280_dpu_caps, 1918 .mdp_count = ARRAY_SIZE(sc7280_mdp), 1919 .mdp = sc7280_mdp, 1920 .ctl_count = ARRAY_SIZE(sc7280_ctl), 1921 .ctl = sc7280_ctl, 1922 .sspp_count = ARRAY_SIZE(sc7280_sspp), 1923 .sspp = sc7280_sspp, 1924 .mixer_count = ARRAY_SIZE(sc7280_lm), 1925 .mixer = sc7280_lm, 1926 .pingpong_count = ARRAY_SIZE(sc7280_pp), 1927 .pingpong = sc7280_pp, 1928 .intf_count = ARRAY_SIZE(sc7280_intf), 1929 .intf = sc7280_intf, 1930 .vbif_count = ARRAY_SIZE(sdm845_vbif), 1931 .vbif = sdm845_vbif, 1932 .perf = sc7280_perf_data, 1933 .mdss_irqs = IRQ_SC7280_MASK, 1934 }; 1935} 1936 1937 1938/* 1939 * qcm2290_cfg_init(): populate qcm2290 dpu sub-blocks reg offsets 1940 * and instance counts. 1941 */ 1942static void qcm2290_cfg_init(struct dpu_mdss_cfg *dpu_cfg) 1943{ 1944 *dpu_cfg = (struct dpu_mdss_cfg){ 1945 .caps = &qcm2290_dpu_caps, 1946 .mdp_count = ARRAY_SIZE(qcm2290_mdp), 1947 .mdp = qcm2290_mdp, 1948 .ctl_count = ARRAY_SIZE(qcm2290_ctl), 1949 .ctl = qcm2290_ctl, 1950 .sspp_count = ARRAY_SIZE(qcm2290_sspp), 1951 .sspp = qcm2290_sspp, 1952 .mixer_count = ARRAY_SIZE(qcm2290_lm), 1953 .mixer = qcm2290_lm, 1954 .dspp_count = ARRAY_SIZE(qcm2290_dspp), 1955 .dspp = qcm2290_dspp, 1956 .pingpong_count = ARRAY_SIZE(qcm2290_pp), 1957 .pingpong = qcm2290_pp, 1958 .intf_count = ARRAY_SIZE(qcm2290_intf), 1959 .intf = qcm2290_intf, 1960 .vbif_count = ARRAY_SIZE(sdm845_vbif), 1961 .vbif = sdm845_vbif, 1962 .reg_dma_count = 1, 1963 .dma_cfg = sdm845_regdma, 1964 .perf = qcm2290_perf_data, 1965 .mdss_irqs = IRQ_SC7180_MASK, 1966 }; 1967} 1968 1969static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { 1970 { .hw_rev = DPU_HW_VER_300, .cfg_init = msm8998_cfg_init}, 1971 { .hw_rev = DPU_HW_VER_301, .cfg_init = msm8998_cfg_init}, 1972 { .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init}, 1973 { .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init}, 1974 { .hw_rev = DPU_HW_VER_500, .cfg_init = sm8150_cfg_init}, 1975 { .hw_rev = DPU_HW_VER_501, .cfg_init = sm8150_cfg_init}, 1976 { .hw_rev = DPU_HW_VER_510, .cfg_init = sc8180x_cfg_init}, 1977 { .hw_rev = DPU_HW_VER_600, .cfg_init = sm8250_cfg_init}, 1978 { .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init}, 1979 { .hw_rev = DPU_HW_VER_650, .cfg_init = qcm2290_cfg_init}, 1980 { .hw_rev = DPU_HW_VER_720, .cfg_init = sc7280_cfg_init}, 1981}; 1982 1983void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg) 1984{ 1985 kfree(dpu_cfg); 1986} 1987 1988struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) 1989{ 1990 int i; 1991 struct dpu_mdss_cfg *dpu_cfg; 1992 1993 dpu_cfg = kzalloc(sizeof(*dpu_cfg), GFP_KERNEL); 1994 if (!dpu_cfg) 1995 return ERR_PTR(-ENOMEM); 1996 1997 for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) { 1998 if (cfg_handler[i].hw_rev == hw_rev) { 1999 cfg_handler[i].cfg_init(dpu_cfg); 2000 dpu_cfg->hwversion = hw_rev; 2001 return dpu_cfg; 2002 } 2003 } 2004 2005 DPU_ERROR("unsupported chipset id:%X\n", hw_rev); 2006 dpu_hw_catalog_deinit(dpu_cfg); 2007 return ERR_PTR(-ENODEV); 2008} 2009