cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

dpu_hw_interrupts.h (1984B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
      3 */
      4
      5#ifndef _DPU_HW_INTERRUPTS_H
      6#define _DPU_HW_INTERRUPTS_H
      7
      8#include <linux/types.h>
      9
     10#include "dpu_hwio.h"
     11#include "dpu_hw_catalog.h"
     12#include "dpu_hw_util.h"
     13#include "dpu_hw_mdss.h"
     14
     15/* When making changes be sure to sync with dpu_intr_set */
     16enum dpu_hw_intr_reg {
     17	MDP_SSPP_TOP0_INTR,
     18	MDP_SSPP_TOP0_INTR2,
     19	MDP_SSPP_TOP0_HIST_INTR,
     20	MDP_INTF0_INTR,
     21	MDP_INTF1_INTR,
     22	MDP_INTF2_INTR,
     23	MDP_INTF3_INTR,
     24	MDP_INTF4_INTR,
     25	MDP_INTF5_INTR,
     26	MDP_AD4_0_INTR,
     27	MDP_AD4_1_INTR,
     28	MDP_INTF0_7xxx_INTR,
     29	MDP_INTF1_7xxx_INTR,
     30	MDP_INTF2_7xxx_INTR,
     31	MDP_INTF3_7xxx_INTR,
     32	MDP_INTF4_7xxx_INTR,
     33	MDP_INTF5_7xxx_INTR,
     34	MDP_INTR_MAX,
     35};
     36
     37#define DPU_IRQ_IDX(reg_idx, offset)	(reg_idx * 32 + offset)
     38
     39/**
     40 * struct dpu_hw_intr: hw interrupts handling data structure
     41 * @hw:               virtual address mapping
     42 * @ops:              function pointer mapping for IRQ handling
     43 * @cache_irq_mask:   array of IRQ enable masks reg storage created during init
     44 * @save_irq_status:  array of IRQ status reg storage created during init
     45 * @total_irqs: total number of irq_idx mapped in the hw_interrupts
     46 * @irq_lock:         spinlock for accessing IRQ resources
     47 * @irq_cb_tbl:       array of IRQ callbacks
     48 */
     49struct dpu_hw_intr {
     50	struct dpu_hw_blk_reg_map hw;
     51	u32 cache_irq_mask[MDP_INTR_MAX];
     52	u32 *save_irq_status;
     53	u32 total_irqs;
     54	spinlock_t irq_lock;
     55	unsigned long irq_mask;
     56
     57	struct {
     58		void (*cb)(void *arg, int irq_idx);
     59		void *arg;
     60		atomic_t count;
     61	} irq_tbl[];
     62};
     63
     64/**
     65 * dpu_hw_intr_init(): Initializes the interrupts hw object
     66 * @addr: mapped register io address of MDP
     67 * @m :   pointer to mdss catalog data
     68 */
     69struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
     70		struct dpu_mdss_cfg *m);
     71
     72/**
     73 * dpu_hw_intr_destroy(): Cleanup interrutps hw object
     74 * @intr: pointer to interrupts hw object
     75 */
     76void dpu_hw_intr_destroy(struct dpu_hw_intr *intr);
     77#endif