cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mdp5_ctl.h (2627B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
      4 */
      5
      6#ifndef __MDP5_CTL_H__
      7#define __MDP5_CTL_H__
      8
      9#include "msm_drv.h"
     10
     11/*
     12 * CTL Manager prototypes:
     13 * mdp5_ctlm_init() returns a ctlm (CTL Manager) handler,
     14 * which is then used to call the other mdp5_ctlm_*(ctlm, ...) functions.
     15 */
     16struct mdp5_ctl_manager;
     17struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,
     18		void __iomem *mmio_base, struct mdp5_cfg_handler *cfg_hnd);
     19void mdp5_ctlm_hw_reset(struct mdp5_ctl_manager *ctlm);
     20void mdp5_ctlm_destroy(struct mdp5_ctl_manager *ctlm);
     21
     22/*
     23 * CTL prototypes:
     24 * mdp5_ctl_request(ctlm, ...) returns a ctl (CTL resource) handler,
     25 * which is then used to call the other mdp5_ctl_*(ctl, ...) functions.
     26 */
     27struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctlm, int intf_num);
     28
     29int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl);
     30
     31struct mdp5_interface;
     32struct mdp5_pipeline;
     33int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *p);
     34int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, struct mdp5_pipeline *p,
     35			       bool enabled);
     36
     37int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
     38			int cursor_id, bool enable);
     39int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable);
     40
     41#define MAX_PIPE_STAGE		2
     42
     43/*
     44 * mdp5_ctl_blend() - Blend multiple layers on a Layer Mixer (LM)
     45 *
     46 * @stage: array to contain the pipe num for each stage
     47 * @stage_cnt: valid stage number in stage array
     48 * @ctl_blend_op_flags: blender operation mode flags
     49 *
     50 * Note:
     51 * CTL registers need to be flushed after calling this function
     52 * (call mdp5_ctl_commit() with mdp_ctl_flush_mask_ctl() mask)
     53 */
     54#define MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT	BIT(0)
     55int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
     56		   enum mdp5_pipe stage[][MAX_PIPE_STAGE],
     57		   enum mdp5_pipe r_stage[][MAX_PIPE_STAGE],
     58		   u32 stage_cnt, u32 ctl_blend_op_flags);
     59
     60/**
     61 * mdp_ctl_flush_mask...() - Register FLUSH masks
     62 *
     63 * These masks are used to specify which block(s) need to be flushed
     64 * through @flush_mask parameter in mdp5_ctl_commit(.., flush_mask).
     65 */
     66u32 mdp_ctl_flush_mask_lm(int lm);
     67u32 mdp_ctl_flush_mask_pipe(enum mdp5_pipe pipe);
     68u32 mdp_ctl_flush_mask_cursor(int cursor_id);
     69u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf);
     70
     71/* @flush_mask: see CTL flush masks definitions below */
     72u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
     73		    u32 flush_mask, bool start);
     74u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl);
     75
     76
     77
     78#endif /* __MDP5_CTL_H__ */