cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dsi_host.c (73173B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
      4 */
      5
      6#include <linux/clk.h>
      7#include <linux/delay.h>
      8#include <linux/dma-mapping.h>
      9#include <linux/err.h>
     10#include <linux/gpio/consumer.h>
     11#include <linux/interrupt.h>
     12#include <linux/mfd/syscon.h>
     13#include <linux/of_device.h>
     14#include <linux/of_graph.h>
     15#include <linux/of_irq.h>
     16#include <linux/pinctrl/consumer.h>
     17#include <linux/pm_opp.h>
     18#include <linux/regmap.h>
     19#include <linux/regulator/consumer.h>
     20#include <linux/spinlock.h>
     21
     22#include <video/mipi_display.h>
     23
     24#include "dsi.h"
     25#include "dsi.xml.h"
     26#include "sfpb.xml.h"
     27#include "dsi_cfg.h"
     28#include "msm_kms.h"
     29#include "msm_gem.h"
     30#include "phy/dsi_phy.h"
     31
     32#define DSI_RESET_TOGGLE_DELAY_MS 20
     33
     34static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc);
     35
     36static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
     37{
     38	u32 ver;
     39
     40	if (!major || !minor)
     41		return -EINVAL;
     42
     43	/*
     44	 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
     45	 * makes all other registers 4-byte shifted down.
     46	 *
     47	 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
     48	 * older, we read the DSI_VERSION register without any shift(offset
     49	 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
     50	 * the case of DSI6G, this has to be zero (the offset points to a
     51	 * scratch register which we never touch)
     52	 */
     53
     54	ver = msm_readl(base + REG_DSI_VERSION);
     55	if (ver) {
     56		/* older dsi host, there is no register shift */
     57		ver = FIELD(ver, DSI_VERSION_MAJOR);
     58		if (ver <= MSM_DSI_VER_MAJOR_V2) {
     59			/* old versions */
     60			*major = ver;
     61			*minor = 0;
     62			return 0;
     63		} else {
     64			return -EINVAL;
     65		}
     66	} else {
     67		/*
     68		 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
     69		 * registers are shifted down, read DSI_VERSION again with
     70		 * the shifted offset
     71		 */
     72		ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
     73		ver = FIELD(ver, DSI_VERSION_MAJOR);
     74		if (ver == MSM_DSI_VER_MAJOR_6G) {
     75			/* 6G version */
     76			*major = ver;
     77			*minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
     78			return 0;
     79		} else {
     80			return -EINVAL;
     81		}
     82	}
     83}
     84
     85#define DSI_ERR_STATE_ACK			0x0000
     86#define DSI_ERR_STATE_TIMEOUT			0x0001
     87#define DSI_ERR_STATE_DLN0_PHY			0x0002
     88#define DSI_ERR_STATE_FIFO			0x0004
     89#define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW	0x0008
     90#define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION	0x0010
     91#define DSI_ERR_STATE_PLL_UNLOCKED		0x0020
     92
     93#define DSI_CLK_CTRL_ENABLE_CLKS	\
     94		(DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
     95		DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
     96		DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
     97		DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
     98
     99struct msm_dsi_host {
    100	struct mipi_dsi_host base;
    101
    102	struct platform_device *pdev;
    103	struct drm_device *dev;
    104
    105	int id;
    106
    107	void __iomem *ctrl_base;
    108	phys_addr_t ctrl_size;
    109	struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
    110
    111	int num_bus_clks;
    112	struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX];
    113
    114	struct clk *byte_clk;
    115	struct clk *esc_clk;
    116	struct clk *pixel_clk;
    117	struct clk *byte_clk_src;
    118	struct clk *pixel_clk_src;
    119	struct clk *byte_intf_clk;
    120
    121	unsigned long byte_clk_rate;
    122	unsigned long pixel_clk_rate;
    123	unsigned long esc_clk_rate;
    124
    125	/* DSI v2 specific clocks */
    126	struct clk *src_clk;
    127	struct clk *esc_clk_src;
    128	struct clk *dsi_clk_src;
    129
    130	unsigned long src_clk_rate;
    131
    132	struct gpio_desc *disp_en_gpio;
    133	struct gpio_desc *te_gpio;
    134
    135	const struct msm_dsi_cfg_handler *cfg_hnd;
    136
    137	struct completion dma_comp;
    138	struct completion video_comp;
    139	struct mutex dev_mutex;
    140	struct mutex cmd_mutex;
    141	spinlock_t intr_lock; /* Protect interrupt ctrl register */
    142
    143	u32 err_work_state;
    144	struct work_struct err_work;
    145	struct work_struct hpd_work;
    146	struct workqueue_struct *workqueue;
    147
    148	/* DSI 6G TX buffer*/
    149	struct drm_gem_object *tx_gem_obj;
    150
    151	/* DSI v2 TX buffer */
    152	void *tx_buf;
    153	dma_addr_t tx_buf_paddr;
    154
    155	int tx_size;
    156
    157	u8 *rx_buf;
    158
    159	struct regmap *sfpb;
    160
    161	struct drm_display_mode *mode;
    162	struct msm_display_dsc_config *dsc;
    163
    164	/* connected device info */
    165	struct device_node *device_node;
    166	unsigned int channel;
    167	unsigned int lanes;
    168	enum mipi_dsi_pixel_format format;
    169	unsigned long mode_flags;
    170
    171	/* lane data parsed via DT */
    172	int dlane_swap;
    173	int num_data_lanes;
    174
    175	/* from phy DT */
    176	bool cphy_mode;
    177
    178	u32 dma_cmd_ctrl_restore;
    179
    180	bool registered;
    181	bool power_on;
    182	bool enabled;
    183	int irq;
    184};
    185
    186static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
    187{
    188	switch (fmt) {
    189	case MIPI_DSI_FMT_RGB565:		return 16;
    190	case MIPI_DSI_FMT_RGB666_PACKED:	return 18;
    191	case MIPI_DSI_FMT_RGB666:
    192	case MIPI_DSI_FMT_RGB888:
    193	default:				return 24;
    194	}
    195}
    196
    197static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
    198{
    199	return msm_readl(msm_host->ctrl_base + reg);
    200}
    201static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
    202{
    203	msm_writel(data, msm_host->ctrl_base + reg);
    204}
    205
    206static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
    207static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
    208
    209static const struct msm_dsi_cfg_handler *dsi_get_config(
    210						struct msm_dsi_host *msm_host)
    211{
    212	const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
    213	struct device *dev = &msm_host->pdev->dev;
    214	struct clk *ahb_clk;
    215	int ret;
    216	u32 major = 0, minor = 0;
    217
    218	cfg_hnd = device_get_match_data(dev);
    219	if (cfg_hnd)
    220		return cfg_hnd;
    221
    222	ahb_clk = msm_clk_get(msm_host->pdev, "iface");
    223	if (IS_ERR(ahb_clk)) {
    224		pr_err("%s: cannot get interface clock\n", __func__);
    225		goto exit;
    226	}
    227
    228	pm_runtime_get_sync(dev);
    229
    230	ret = clk_prepare_enable(ahb_clk);
    231	if (ret) {
    232		pr_err("%s: unable to enable ahb_clk\n", __func__);
    233		goto runtime_put;
    234	}
    235
    236	ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
    237	if (ret) {
    238		pr_err("%s: Invalid version\n", __func__);
    239		goto disable_clks;
    240	}
    241
    242	cfg_hnd = msm_dsi_cfg_get(major, minor);
    243
    244	DBG("%s: Version %x:%x\n", __func__, major, minor);
    245
    246disable_clks:
    247	clk_disable_unprepare(ahb_clk);
    248runtime_put:
    249	pm_runtime_put_sync(dev);
    250exit:
    251	return cfg_hnd;
    252}
    253
    254static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
    255{
    256	return container_of(host, struct msm_dsi_host, base);
    257}
    258
    259static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
    260{
    261	struct regulator_bulk_data *s = msm_host->supplies;
    262	const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
    263	int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
    264	int i;
    265
    266	DBG("");
    267	for (i = num - 1; i >= 0; i--)
    268		if (regs[i].disable_load >= 0)
    269			regulator_set_load(s[i].consumer,
    270					   regs[i].disable_load);
    271
    272	regulator_bulk_disable(num, s);
    273}
    274
    275static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
    276{
    277	struct regulator_bulk_data *s = msm_host->supplies;
    278	const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
    279	int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
    280	int ret, i;
    281
    282	DBG("");
    283	for (i = 0; i < num; i++) {
    284		if (regs[i].enable_load >= 0) {
    285			ret = regulator_set_load(s[i].consumer,
    286						 regs[i].enable_load);
    287			if (ret < 0) {
    288				pr_err("regulator %d set op mode failed, %d\n",
    289					i, ret);
    290				goto fail;
    291			}
    292		}
    293	}
    294
    295	ret = regulator_bulk_enable(num, s);
    296	if (ret < 0) {
    297		pr_err("regulator enable failed, %d\n", ret);
    298		goto fail;
    299	}
    300
    301	return 0;
    302
    303fail:
    304	for (i--; i >= 0; i--)
    305		regulator_set_load(s[i].consumer, regs[i].disable_load);
    306	return ret;
    307}
    308
    309static int dsi_regulator_init(struct msm_dsi_host *msm_host)
    310{
    311	struct regulator_bulk_data *s = msm_host->supplies;
    312	const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
    313	int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
    314	int i, ret;
    315
    316	for (i = 0; i < num; i++)
    317		s[i].supply = regs[i].name;
    318
    319	ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
    320	if (ret < 0) {
    321		pr_err("%s: failed to init regulator, ret=%d\n",
    322						__func__, ret);
    323		return ret;
    324	}
    325
    326	return 0;
    327}
    328
    329int dsi_clk_init_v2(struct msm_dsi_host *msm_host)
    330{
    331	struct platform_device *pdev = msm_host->pdev;
    332	int ret = 0;
    333
    334	msm_host->src_clk = msm_clk_get(pdev, "src");
    335
    336	if (IS_ERR(msm_host->src_clk)) {
    337		ret = PTR_ERR(msm_host->src_clk);
    338		pr_err("%s: can't find src clock. ret=%d\n",
    339			__func__, ret);
    340		msm_host->src_clk = NULL;
    341		return ret;
    342	}
    343
    344	msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
    345	if (!msm_host->esc_clk_src) {
    346		ret = -ENODEV;
    347		pr_err("%s: can't get esc clock parent. ret=%d\n",
    348			__func__, ret);
    349		return ret;
    350	}
    351
    352	msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
    353	if (!msm_host->dsi_clk_src) {
    354		ret = -ENODEV;
    355		pr_err("%s: can't get src clock parent. ret=%d\n",
    356			__func__, ret);
    357	}
    358
    359	return ret;
    360}
    361
    362int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host)
    363{
    364	struct platform_device *pdev = msm_host->pdev;
    365	int ret = 0;
    366
    367	msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf");
    368	if (IS_ERR(msm_host->byte_intf_clk)) {
    369		ret = PTR_ERR(msm_host->byte_intf_clk);
    370		pr_err("%s: can't find byte_intf clock. ret=%d\n",
    371			__func__, ret);
    372	}
    373
    374	return ret;
    375}
    376
    377static int dsi_clk_init(struct msm_dsi_host *msm_host)
    378{
    379	struct platform_device *pdev = msm_host->pdev;
    380	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
    381	const struct msm_dsi_config *cfg = cfg_hnd->cfg;
    382	int i, ret = 0;
    383
    384	/* get bus clocks */
    385	for (i = 0; i < cfg->num_bus_clks; i++)
    386		msm_host->bus_clks[i].id = cfg->bus_clk_names[i];
    387	msm_host->num_bus_clks = cfg->num_bus_clks;
    388
    389	ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks);
    390	if (ret < 0) {
    391		dev_err(&pdev->dev, "Unable to get clocks, ret = %d\n", ret);
    392		goto exit;
    393	}
    394
    395	/* get link and source clocks */
    396	msm_host->byte_clk = msm_clk_get(pdev, "byte");
    397	if (IS_ERR(msm_host->byte_clk)) {
    398		ret = PTR_ERR(msm_host->byte_clk);
    399		pr_err("%s: can't find dsi_byte clock. ret=%d\n",
    400			__func__, ret);
    401		msm_host->byte_clk = NULL;
    402		goto exit;
    403	}
    404
    405	msm_host->pixel_clk = msm_clk_get(pdev, "pixel");
    406	if (IS_ERR(msm_host->pixel_clk)) {
    407		ret = PTR_ERR(msm_host->pixel_clk);
    408		pr_err("%s: can't find dsi_pixel clock. ret=%d\n",
    409			__func__, ret);
    410		msm_host->pixel_clk = NULL;
    411		goto exit;
    412	}
    413
    414	msm_host->esc_clk = msm_clk_get(pdev, "core");
    415	if (IS_ERR(msm_host->esc_clk)) {
    416		ret = PTR_ERR(msm_host->esc_clk);
    417		pr_err("%s: can't find dsi_esc clock. ret=%d\n",
    418			__func__, ret);
    419		msm_host->esc_clk = NULL;
    420		goto exit;
    421	}
    422
    423	msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
    424	if (IS_ERR(msm_host->byte_clk_src)) {
    425		ret = PTR_ERR(msm_host->byte_clk_src);
    426		pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret);
    427		goto exit;
    428	}
    429
    430	msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk);
    431	if (IS_ERR(msm_host->pixel_clk_src)) {
    432		ret = PTR_ERR(msm_host->pixel_clk_src);
    433		pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret);
    434		goto exit;
    435	}
    436
    437	if (cfg_hnd->ops->clk_init_ver)
    438		ret = cfg_hnd->ops->clk_init_ver(msm_host);
    439exit:
    440	return ret;
    441}
    442
    443int msm_dsi_runtime_suspend(struct device *dev)
    444{
    445	struct platform_device *pdev = to_platform_device(dev);
    446	struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
    447	struct mipi_dsi_host *host = msm_dsi->host;
    448	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
    449
    450	if (!msm_host->cfg_hnd)
    451		return 0;
    452
    453	clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks);
    454
    455	return 0;
    456}
    457
    458int msm_dsi_runtime_resume(struct device *dev)
    459{
    460	struct platform_device *pdev = to_platform_device(dev);
    461	struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
    462	struct mipi_dsi_host *host = msm_dsi->host;
    463	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
    464
    465	if (!msm_host->cfg_hnd)
    466		return 0;
    467
    468	return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks);
    469}
    470
    471int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
    472{
    473	unsigned long byte_intf_rate;
    474	int ret;
    475
    476	DBG("Set clk rates: pclk=%d, byteclk=%lu",
    477		msm_host->mode->clock, msm_host->byte_clk_rate);
    478
    479	ret = dev_pm_opp_set_rate(&msm_host->pdev->dev,
    480				  msm_host->byte_clk_rate);
    481	if (ret) {
    482		pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret);
    483		return ret;
    484	}
    485
    486	ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
    487	if (ret) {
    488		pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
    489		return ret;
    490	}
    491
    492	if (msm_host->byte_intf_clk) {
    493		/* For CPHY, byte_intf_clk is same as byte_clk */
    494		if (msm_host->cphy_mode)
    495			byte_intf_rate = msm_host->byte_clk_rate;
    496		else
    497			byte_intf_rate = msm_host->byte_clk_rate / 2;
    498
    499		ret = clk_set_rate(msm_host->byte_intf_clk, byte_intf_rate);
    500		if (ret) {
    501			pr_err("%s: Failed to set rate byte intf clk, %d\n",
    502			       __func__, ret);
    503			return ret;
    504		}
    505	}
    506
    507	return 0;
    508}
    509
    510
    511int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
    512{
    513	int ret;
    514
    515	ret = clk_prepare_enable(msm_host->esc_clk);
    516	if (ret) {
    517		pr_err("%s: Failed to enable dsi esc clk\n", __func__);
    518		goto error;
    519	}
    520
    521	ret = clk_prepare_enable(msm_host->byte_clk);
    522	if (ret) {
    523		pr_err("%s: Failed to enable dsi byte clk\n", __func__);
    524		goto byte_clk_err;
    525	}
    526
    527	ret = clk_prepare_enable(msm_host->pixel_clk);
    528	if (ret) {
    529		pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
    530		goto pixel_clk_err;
    531	}
    532
    533	ret = clk_prepare_enable(msm_host->byte_intf_clk);
    534	if (ret) {
    535		pr_err("%s: Failed to enable byte intf clk\n",
    536			   __func__);
    537		goto byte_intf_clk_err;
    538	}
    539
    540	return 0;
    541
    542byte_intf_clk_err:
    543	clk_disable_unprepare(msm_host->pixel_clk);
    544pixel_clk_err:
    545	clk_disable_unprepare(msm_host->byte_clk);
    546byte_clk_err:
    547	clk_disable_unprepare(msm_host->esc_clk);
    548error:
    549	return ret;
    550}
    551
    552int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host)
    553{
    554	int ret;
    555
    556	DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu",
    557		msm_host->mode->clock, msm_host->byte_clk_rate,
    558		msm_host->esc_clk_rate, msm_host->src_clk_rate);
    559
    560	ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
    561	if (ret) {
    562		pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
    563		return ret;
    564	}
    565
    566	ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
    567	if (ret) {
    568		pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
    569		return ret;
    570	}
    571
    572	ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
    573	if (ret) {
    574		pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
    575		return ret;
    576	}
    577
    578	ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
    579	if (ret) {
    580		pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
    581		return ret;
    582	}
    583
    584	return 0;
    585}
    586
    587int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
    588{
    589	int ret;
    590
    591	ret = clk_prepare_enable(msm_host->byte_clk);
    592	if (ret) {
    593		pr_err("%s: Failed to enable dsi byte clk\n", __func__);
    594		goto error;
    595	}
    596
    597	ret = clk_prepare_enable(msm_host->esc_clk);
    598	if (ret) {
    599		pr_err("%s: Failed to enable dsi esc clk\n", __func__);
    600		goto esc_clk_err;
    601	}
    602
    603	ret = clk_prepare_enable(msm_host->src_clk);
    604	if (ret) {
    605		pr_err("%s: Failed to enable dsi src clk\n", __func__);
    606		goto src_clk_err;
    607	}
    608
    609	ret = clk_prepare_enable(msm_host->pixel_clk);
    610	if (ret) {
    611		pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
    612		goto pixel_clk_err;
    613	}
    614
    615	return 0;
    616
    617pixel_clk_err:
    618	clk_disable_unprepare(msm_host->src_clk);
    619src_clk_err:
    620	clk_disable_unprepare(msm_host->esc_clk);
    621esc_clk_err:
    622	clk_disable_unprepare(msm_host->byte_clk);
    623error:
    624	return ret;
    625}
    626
    627void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host)
    628{
    629	/* Drop the performance state vote */
    630	dev_pm_opp_set_rate(&msm_host->pdev->dev, 0);
    631	clk_disable_unprepare(msm_host->esc_clk);
    632	clk_disable_unprepare(msm_host->pixel_clk);
    633	clk_disable_unprepare(msm_host->byte_intf_clk);
    634	clk_disable_unprepare(msm_host->byte_clk);
    635}
    636
    637void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
    638{
    639	clk_disable_unprepare(msm_host->pixel_clk);
    640	clk_disable_unprepare(msm_host->src_clk);
    641	clk_disable_unprepare(msm_host->esc_clk);
    642	clk_disable_unprepare(msm_host->byte_clk);
    643}
    644
    645static unsigned long dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
    646{
    647	struct drm_display_mode *mode = msm_host->mode;
    648	unsigned long pclk_rate;
    649
    650	pclk_rate = mode->clock * 1000;
    651
    652	/*
    653	 * For bonded DSI mode, the current DRM mode has the complete width of the
    654	 * panel. Since, the complete panel is driven by two DSI controllers,
    655	 * the clock rates have to be split between the two dsi controllers.
    656	 * Adjust the byte and pixel clock rates for each dsi host accordingly.
    657	 */
    658	if (is_bonded_dsi)
    659		pclk_rate /= 2;
    660
    661	return pclk_rate;
    662}
    663
    664static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
    665{
    666	u8 lanes = msm_host->lanes;
    667	u32 bpp = dsi_get_bpp(msm_host->format);
    668	unsigned long pclk_rate = dsi_get_pclk_rate(msm_host, is_bonded_dsi);
    669	u64 pclk_bpp = (u64)pclk_rate * bpp;
    670
    671	if (lanes == 0) {
    672		pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
    673		lanes = 1;
    674	}
    675
    676	/* CPHY "byte_clk" is in units of 16 bits */
    677	if (msm_host->cphy_mode)
    678		do_div(pclk_bpp, (16 * lanes));
    679	else
    680		do_div(pclk_bpp, (8 * lanes));
    681
    682	msm_host->pixel_clk_rate = pclk_rate;
    683	msm_host->byte_clk_rate = pclk_bpp;
    684
    685	DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate,
    686				msm_host->byte_clk_rate);
    687
    688}
    689
    690int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
    691{
    692	if (!msm_host->mode) {
    693		pr_err("%s: mode not set\n", __func__);
    694		return -EINVAL;
    695	}
    696
    697	dsi_calc_pclk(msm_host, is_bonded_dsi);
    698	msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
    699	return 0;
    700}
    701
    702int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
    703{
    704	u32 bpp = dsi_get_bpp(msm_host->format);
    705	u64 pclk_bpp;
    706	unsigned int esc_mhz, esc_div;
    707	unsigned long byte_mhz;
    708
    709	dsi_calc_pclk(msm_host, is_bonded_dsi);
    710
    711	pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_bonded_dsi) * bpp;
    712	do_div(pclk_bpp, 8);
    713	msm_host->src_clk_rate = pclk_bpp;
    714
    715	/*
    716	 * esc clock is byte clock followed by a 4 bit divider,
    717	 * we need to find an escape clock frequency within the
    718	 * mipi DSI spec range within the maximum divider limit
    719	 * We iterate here between an escape clock frequencey
    720	 * between 20 Mhz to 5 Mhz and pick up the first one
    721	 * that can be supported by our divider
    722	 */
    723
    724	byte_mhz = msm_host->byte_clk_rate / 1000000;
    725
    726	for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
    727		esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
    728
    729		/*
    730		 * TODO: Ideally, we shouldn't know what sort of divider
    731		 * is available in mmss_cc, we're just assuming that
    732		 * it'll always be a 4 bit divider. Need to come up with
    733		 * a better way here.
    734		 */
    735		if (esc_div >= 1 && esc_div <= 16)
    736			break;
    737	}
    738
    739	if (esc_mhz < 5)
    740		return -EINVAL;
    741
    742	msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
    743
    744	DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate,
    745		msm_host->src_clk_rate);
    746
    747	return 0;
    748}
    749
    750static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
    751{
    752	u32 intr;
    753	unsigned long flags;
    754
    755	spin_lock_irqsave(&msm_host->intr_lock, flags);
    756	intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
    757
    758	if (enable)
    759		intr |= mask;
    760	else
    761		intr &= ~mask;
    762
    763	DBG("intr=%x enable=%d", intr, enable);
    764
    765	dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
    766	spin_unlock_irqrestore(&msm_host->intr_lock, flags);
    767}
    768
    769static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
    770{
    771	if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
    772		return BURST_MODE;
    773	else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
    774		return NON_BURST_SYNCH_PULSE;
    775
    776	return NON_BURST_SYNCH_EVENT;
    777}
    778
    779static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
    780				const enum mipi_dsi_pixel_format mipi_fmt)
    781{
    782	switch (mipi_fmt) {
    783	case MIPI_DSI_FMT_RGB888:	return VID_DST_FORMAT_RGB888;
    784	case MIPI_DSI_FMT_RGB666:	return VID_DST_FORMAT_RGB666_LOOSE;
    785	case MIPI_DSI_FMT_RGB666_PACKED:	return VID_DST_FORMAT_RGB666;
    786	case MIPI_DSI_FMT_RGB565:	return VID_DST_FORMAT_RGB565;
    787	default:			return VID_DST_FORMAT_RGB888;
    788	}
    789}
    790
    791static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
    792				const enum mipi_dsi_pixel_format mipi_fmt)
    793{
    794	switch (mipi_fmt) {
    795	case MIPI_DSI_FMT_RGB888:	return CMD_DST_FORMAT_RGB888;
    796	case MIPI_DSI_FMT_RGB666_PACKED:
    797	case MIPI_DSI_FMT_RGB666:	return CMD_DST_FORMAT_RGB666;
    798	case MIPI_DSI_FMT_RGB565:	return CMD_DST_FORMAT_RGB565;
    799	default:			return CMD_DST_FORMAT_RGB888;
    800	}
    801}
    802
    803static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
    804			struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy)
    805{
    806	u32 flags = msm_host->mode_flags;
    807	enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
    808	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
    809	u32 data = 0, lane_ctrl = 0;
    810
    811	if (!enable) {
    812		dsi_write(msm_host, REG_DSI_CTRL, 0);
    813		return;
    814	}
    815
    816	if (flags & MIPI_DSI_MODE_VIDEO) {
    817		if (flags & MIPI_DSI_MODE_VIDEO_HSE)
    818			data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
    819		if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
    820			data |= DSI_VID_CFG0_HFP_POWER_STOP;
    821		if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
    822			data |= DSI_VID_CFG0_HBP_POWER_STOP;
    823		if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
    824			data |= DSI_VID_CFG0_HSA_POWER_STOP;
    825		/* Always set low power stop mode for BLLP
    826		 * to let command engine send packets
    827		 */
    828		data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
    829			DSI_VID_CFG0_BLLP_POWER_STOP;
    830		data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
    831		data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
    832		data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
    833		dsi_write(msm_host, REG_DSI_VID_CFG0, data);
    834
    835		/* Do not swap RGB colors */
    836		data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
    837		dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
    838	} else {
    839		/* Do not swap RGB colors */
    840		data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
    841		data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
    842		dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
    843
    844		data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
    845			DSI_CMD_CFG1_WR_MEM_CONTINUE(
    846					MIPI_DCS_WRITE_MEMORY_CONTINUE);
    847		/* Always insert DCS command */
    848		data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
    849		dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
    850	}
    851
    852	dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
    853			DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
    854			DSI_CMD_DMA_CTRL_LOW_POWER);
    855
    856	data = 0;
    857	/* Always assume dedicated TE pin */
    858	data |= DSI_TRIG_CTRL_TE;
    859	data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
    860	data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
    861	data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
    862	if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
    863		(cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
    864		data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
    865	dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
    866
    867	data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) |
    868		DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre);
    869	dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
    870
    871	if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
    872	    (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) &&
    873	    phy_shared_timings->clk_pre_inc_by_2)
    874		dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,
    875			  DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK);
    876
    877	data = 0;
    878	if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET))
    879		data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
    880	dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
    881
    882	/* allow only ack-err-status to generate interrupt */
    883	dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
    884
    885	dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
    886
    887	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
    888
    889	data = DSI_CTRL_CLK_EN;
    890
    891	DBG("lane number=%d", msm_host->lanes);
    892	data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
    893
    894	dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
    895		  DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
    896
    897	if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) {
    898		lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL);
    899
    900		if (msm_dsi_phy_set_continuous_clock(phy, enable))
    901			lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY;
    902
    903		dsi_write(msm_host, REG_DSI_LANE_CTRL,
    904			lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
    905	}
    906
    907	data |= DSI_CTRL_ENABLE;
    908
    909	dsi_write(msm_host, REG_DSI_CTRL, data);
    910
    911	if (msm_host->cphy_mode)
    912		dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
    913}
    914
    915static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay)
    916{
    917	struct msm_display_dsc_config *dsc = msm_host->dsc;
    918	u32 reg, intf_width, reg_ctrl, reg_ctrl2;
    919	u32 slice_per_intf, total_bytes_per_intf;
    920	u32 pkt_per_line;
    921	u32 bytes_in_slice;
    922	u32 eol_byte_num;
    923
    924	/* first calculate dsc parameters and then program
    925	 * compress mode registers
    926	 */
    927	intf_width = hdisplay;
    928	slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
    929
    930	/* If slice_per_pkt is greater than slice_per_intf
    931	 * then default to 1. This can happen during partial
    932	 * update.
    933	 */
    934	if (slice_per_intf > dsc->drm->slice_count)
    935		dsc->drm->slice_count = 1;
    936
    937	slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width);
    938	bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * dsc->drm->bits_per_pixel, 8);
    939
    940	dsc->drm->slice_chunk_size = bytes_in_slice;
    941
    942	total_bytes_per_intf = bytes_in_slice * slice_per_intf;
    943
    944	eol_byte_num = total_bytes_per_intf % 3;
    945	pkt_per_line = slice_per_intf / dsc->drm->slice_count;
    946
    947	if (is_cmd_mode) /* packet data type */
    948		reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
    949	else
    950		reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM);
    951
    952	/* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE
    953	 * registers have similar offsets, so for below common code use
    954	 * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits
    955	 */
    956	reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1);
    957	reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num);
    958	reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN;
    959
    960	if (is_cmd_mode) {
    961		reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
    962		reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
    963
    964		reg_ctrl &= ~0xffff;
    965		reg_ctrl |= reg;
    966
    967		reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK;
    968		reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(bytes_in_slice);
    969
    970		dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl);
    971		dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
    972	} else {
    973		dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
    974	}
    975}
    976
    977static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
    978{
    979	struct drm_display_mode *mode = msm_host->mode;
    980	u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
    981	u32 h_total = mode->htotal;
    982	u32 v_total = mode->vtotal;
    983	u32 hs_end = mode->hsync_end - mode->hsync_start;
    984	u32 vs_end = mode->vsync_end - mode->vsync_start;
    985	u32 ha_start = h_total - mode->hsync_start;
    986	u32 ha_end = ha_start + mode->hdisplay;
    987	u32 va_start = v_total - mode->vsync_start;
    988	u32 va_end = va_start + mode->vdisplay;
    989	u32 hdisplay = mode->hdisplay;
    990	u32 wc;
    991
    992	DBG("");
    993
    994	/*
    995	 * For bonded DSI mode, the current DRM mode has
    996	 * the complete width of the panel. Since, the complete
    997	 * panel is driven by two DSI controllers, the horizontal
    998	 * timings have to be split between the two dsi controllers.
    999	 * Adjust the DSI host timing values accordingly.
   1000	 */
   1001	if (is_bonded_dsi) {
   1002		h_total /= 2;
   1003		hs_end /= 2;
   1004		ha_start /= 2;
   1005		ha_end /= 2;
   1006		hdisplay /= 2;
   1007	}
   1008
   1009	if (msm_host->dsc) {
   1010		struct msm_display_dsc_config *dsc = msm_host->dsc;
   1011
   1012		/* update dsc params with timing params */
   1013		if (!dsc || !mode->hdisplay || !mode->vdisplay) {
   1014			pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n",
   1015			       mode->hdisplay, mode->vdisplay);
   1016			return;
   1017		}
   1018
   1019		dsc->drm->pic_width = mode->hdisplay;
   1020		dsc->drm->pic_height = mode->vdisplay;
   1021		DBG("Mode %dx%d\n", dsc->drm->pic_width, dsc->drm->pic_height);
   1022
   1023		/* we do the calculations for dsc parameters here so that
   1024		 * panel can use these parameters
   1025		 */
   1026		dsi_populate_dsc_params(dsc);
   1027
   1028		/* Divide the display by 3 but keep back/font porch and
   1029		 * pulse width same
   1030		 */
   1031		h_total -= hdisplay;
   1032		hdisplay /= 3;
   1033		h_total += hdisplay;
   1034		ha_end = ha_start + hdisplay;
   1035	}
   1036
   1037	if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
   1038		if (msm_host->dsc)
   1039			dsi_update_dsc_timing(msm_host, false, mode->hdisplay);
   1040
   1041		dsi_write(msm_host, REG_DSI_ACTIVE_H,
   1042			DSI_ACTIVE_H_START(ha_start) |
   1043			DSI_ACTIVE_H_END(ha_end));
   1044		dsi_write(msm_host, REG_DSI_ACTIVE_V,
   1045			DSI_ACTIVE_V_START(va_start) |
   1046			DSI_ACTIVE_V_END(va_end));
   1047		dsi_write(msm_host, REG_DSI_TOTAL,
   1048			DSI_TOTAL_H_TOTAL(h_total - 1) |
   1049			DSI_TOTAL_V_TOTAL(v_total - 1));
   1050
   1051		dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
   1052			DSI_ACTIVE_HSYNC_START(hs_start) |
   1053			DSI_ACTIVE_HSYNC_END(hs_end));
   1054		dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
   1055		dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
   1056			DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
   1057			DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
   1058	} else {		/* command mode */
   1059		if (msm_host->dsc)
   1060			dsi_update_dsc_timing(msm_host, true, mode->hdisplay);
   1061
   1062		/* image data and 1 byte write_memory_start cmd */
   1063		if (!msm_host->dsc)
   1064			wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
   1065		else
   1066			wc = mode->hdisplay / 2 + 1;
   1067
   1068		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
   1069			DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
   1070			DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(
   1071					msm_host->channel) |
   1072			DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(
   1073					MIPI_DSI_DCS_LONG_WRITE));
   1074
   1075		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL,
   1076			DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) |
   1077			DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay));
   1078	}
   1079}
   1080
   1081static void dsi_sw_reset(struct msm_dsi_host *msm_host)
   1082{
   1083	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
   1084	wmb(); /* clocks need to be enabled before reset */
   1085
   1086	dsi_write(msm_host, REG_DSI_RESET, 1);
   1087	msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
   1088	dsi_write(msm_host, REG_DSI_RESET, 0);
   1089}
   1090
   1091static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
   1092					bool video_mode, bool enable)
   1093{
   1094	u32 dsi_ctrl;
   1095
   1096	dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
   1097
   1098	if (!enable) {
   1099		dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
   1100				DSI_CTRL_CMD_MODE_EN);
   1101		dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
   1102					DSI_IRQ_MASK_VIDEO_DONE, 0);
   1103	} else {
   1104		if (video_mode) {
   1105			dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
   1106		} else {		/* command mode */
   1107			dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
   1108			dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
   1109		}
   1110		dsi_ctrl |= DSI_CTRL_ENABLE;
   1111	}
   1112
   1113	dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
   1114}
   1115
   1116static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
   1117{
   1118	u32 data;
   1119
   1120	data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
   1121
   1122	if (mode == 0)
   1123		data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
   1124	else
   1125		data |= DSI_CMD_DMA_CTRL_LOW_POWER;
   1126
   1127	dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
   1128}
   1129
   1130static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
   1131{
   1132	u32 ret = 0;
   1133	struct device *dev = &msm_host->pdev->dev;
   1134
   1135	dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
   1136
   1137	reinit_completion(&msm_host->video_comp);
   1138
   1139	ret = wait_for_completion_timeout(&msm_host->video_comp,
   1140			msecs_to_jiffies(70));
   1141
   1142	if (ret == 0)
   1143		DRM_DEV_ERROR(dev, "wait for video done timed out\n");
   1144
   1145	dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
   1146}
   1147
   1148static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
   1149{
   1150	if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
   1151		return;
   1152
   1153	if (msm_host->power_on && msm_host->enabled) {
   1154		dsi_wait4video_done(msm_host);
   1155		/* delay 4 ms to skip BLLP */
   1156		usleep_range(2000, 4000);
   1157	}
   1158}
   1159
   1160int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size)
   1161{
   1162	struct drm_device *dev = msm_host->dev;
   1163	struct msm_drm_private *priv = dev->dev_private;
   1164	uint64_t iova;
   1165	u8 *data;
   1166
   1167	data = msm_gem_kernel_new(dev, size, MSM_BO_WC,
   1168					priv->kms->aspace,
   1169					&msm_host->tx_gem_obj, &iova);
   1170
   1171	if (IS_ERR(data)) {
   1172		msm_host->tx_gem_obj = NULL;
   1173		return PTR_ERR(data);
   1174	}
   1175
   1176	msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem");
   1177
   1178	msm_host->tx_size = msm_host->tx_gem_obj->size;
   1179
   1180	return 0;
   1181}
   1182
   1183int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size)
   1184{
   1185	struct drm_device *dev = msm_host->dev;
   1186
   1187	msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
   1188					&msm_host->tx_buf_paddr, GFP_KERNEL);
   1189	if (!msm_host->tx_buf)
   1190		return -ENOMEM;
   1191
   1192	msm_host->tx_size = size;
   1193
   1194	return 0;
   1195}
   1196
   1197static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
   1198{
   1199	struct drm_device *dev = msm_host->dev;
   1200	struct msm_drm_private *priv;
   1201
   1202	/*
   1203	 * This is possible if we're tearing down before we've had a chance to
   1204	 * fully initialize. A very real possibility if our probe is deferred,
   1205	 * in which case we'll hit msm_dsi_host_destroy() without having run
   1206	 * through the dsi_tx_buf_alloc().
   1207	 */
   1208	if (!dev)
   1209		return;
   1210
   1211	priv = dev->dev_private;
   1212	if (msm_host->tx_gem_obj) {
   1213		msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace);
   1214		drm_gem_object_put(msm_host->tx_gem_obj);
   1215		msm_host->tx_gem_obj = NULL;
   1216	}
   1217
   1218	if (msm_host->tx_buf)
   1219		dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
   1220			msm_host->tx_buf_paddr);
   1221}
   1222
   1223void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host)
   1224{
   1225	return msm_gem_get_vaddr(msm_host->tx_gem_obj);
   1226}
   1227
   1228void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host)
   1229{
   1230	return msm_host->tx_buf;
   1231}
   1232
   1233void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host)
   1234{
   1235	msm_gem_put_vaddr(msm_host->tx_gem_obj);
   1236}
   1237
   1238/*
   1239 * prepare cmd buffer to be txed
   1240 */
   1241static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
   1242			   const struct mipi_dsi_msg *msg)
   1243{
   1244	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
   1245	struct mipi_dsi_packet packet;
   1246	int len;
   1247	int ret;
   1248	u8 *data;
   1249
   1250	ret = mipi_dsi_create_packet(&packet, msg);
   1251	if (ret) {
   1252		pr_err("%s: create packet failed, %d\n", __func__, ret);
   1253		return ret;
   1254	}
   1255	len = (packet.size + 3) & (~0x3);
   1256
   1257	if (len > msm_host->tx_size) {
   1258		pr_err("%s: packet size is too big\n", __func__);
   1259		return -EINVAL;
   1260	}
   1261
   1262	data = cfg_hnd->ops->tx_buf_get(msm_host);
   1263	if (IS_ERR(data)) {
   1264		ret = PTR_ERR(data);
   1265		pr_err("%s: get vaddr failed, %d\n", __func__, ret);
   1266		return ret;
   1267	}
   1268
   1269	/* MSM specific command format in memory */
   1270	data[0] = packet.header[1];
   1271	data[1] = packet.header[2];
   1272	data[2] = packet.header[0];
   1273	data[3] = BIT(7); /* Last packet */
   1274	if (mipi_dsi_packet_format_is_long(msg->type))
   1275		data[3] |= BIT(6);
   1276	if (msg->rx_buf && msg->rx_len)
   1277		data[3] |= BIT(5);
   1278
   1279	/* Long packet */
   1280	if (packet.payload && packet.payload_length)
   1281		memcpy(data + 4, packet.payload, packet.payload_length);
   1282
   1283	/* Append 0xff to the end */
   1284	if (packet.size < len)
   1285		memset(data + packet.size, 0xff, len - packet.size);
   1286
   1287	if (cfg_hnd->ops->tx_buf_put)
   1288		cfg_hnd->ops->tx_buf_put(msm_host);
   1289
   1290	return len;
   1291}
   1292
   1293/*
   1294 * dsi_short_read1_resp: 1 parameter
   1295 */
   1296static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
   1297{
   1298	u8 *data = msg->rx_buf;
   1299	if (data && (msg->rx_len >= 1)) {
   1300		*data = buf[1]; /* strip out dcs type */
   1301		return 1;
   1302	} else {
   1303		pr_err("%s: read data does not match with rx_buf len %zu\n",
   1304			__func__, msg->rx_len);
   1305		return -EINVAL;
   1306	}
   1307}
   1308
   1309/*
   1310 * dsi_short_read2_resp: 2 parameter
   1311 */
   1312static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
   1313{
   1314	u8 *data = msg->rx_buf;
   1315	if (data && (msg->rx_len >= 2)) {
   1316		data[0] = buf[1]; /* strip out dcs type */
   1317		data[1] = buf[2];
   1318		return 2;
   1319	} else {
   1320		pr_err("%s: read data does not match with rx_buf len %zu\n",
   1321			__func__, msg->rx_len);
   1322		return -EINVAL;
   1323	}
   1324}
   1325
   1326static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
   1327{
   1328	/* strip out 4 byte dcs header */
   1329	if (msg->rx_buf && msg->rx_len)
   1330		memcpy(msg->rx_buf, buf + 4, msg->rx_len);
   1331
   1332	return msg->rx_len;
   1333}
   1334
   1335int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base)
   1336{
   1337	struct drm_device *dev = msm_host->dev;
   1338	struct msm_drm_private *priv = dev->dev_private;
   1339
   1340	if (!dma_base)
   1341		return -EINVAL;
   1342
   1343	return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj,
   1344				priv->kms->aspace, dma_base);
   1345}
   1346
   1347int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base)
   1348{
   1349	if (!dma_base)
   1350		return -EINVAL;
   1351
   1352	*dma_base = msm_host->tx_buf_paddr;
   1353	return 0;
   1354}
   1355
   1356static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
   1357{
   1358	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
   1359	int ret;
   1360	uint64_t dma_base;
   1361	bool triggered;
   1362
   1363	ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base);
   1364	if (ret) {
   1365		pr_err("%s: failed to get iova: %d\n", __func__, ret);
   1366		return ret;
   1367	}
   1368
   1369	reinit_completion(&msm_host->dma_comp);
   1370
   1371	dsi_wait4video_eng_busy(msm_host);
   1372
   1373	triggered = msm_dsi_manager_cmd_xfer_trigger(
   1374						msm_host->id, dma_base, len);
   1375	if (triggered) {
   1376		ret = wait_for_completion_timeout(&msm_host->dma_comp,
   1377					msecs_to_jiffies(200));
   1378		DBG("ret=%d", ret);
   1379		if (ret == 0)
   1380			ret = -ETIMEDOUT;
   1381		else
   1382			ret = len;
   1383	} else
   1384		ret = len;
   1385
   1386	return ret;
   1387}
   1388
   1389static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
   1390			u8 *buf, int rx_byte, int pkt_size)
   1391{
   1392	u32 *temp, data;
   1393	int i, j = 0, cnt;
   1394	u32 read_cnt;
   1395	u8 reg[16];
   1396	int repeated_bytes = 0;
   1397	int buf_offset = buf - msm_host->rx_buf;
   1398
   1399	temp = (u32 *)reg;
   1400	cnt = (rx_byte + 3) >> 2;
   1401	if (cnt > 4)
   1402		cnt = 4; /* 4 x 32 bits registers only */
   1403
   1404	if (rx_byte == 4)
   1405		read_cnt = 4;
   1406	else
   1407		read_cnt = pkt_size + 6;
   1408
   1409	/*
   1410	 * In case of multiple reads from the panel, after the first read, there
   1411	 * is possibility that there are some bytes in the payload repeating in
   1412	 * the RDBK_DATA registers. Since we read all the parameters from the
   1413	 * panel right from the first byte for every pass. We need to skip the
   1414	 * repeating bytes and then append the new parameters to the rx buffer.
   1415	 */
   1416	if (read_cnt > 16) {
   1417		int bytes_shifted;
   1418		/* Any data more than 16 bytes will be shifted out.
   1419		 * The temp read buffer should already contain these bytes.
   1420		 * The remaining bytes in read buffer are the repeated bytes.
   1421		 */
   1422		bytes_shifted = read_cnt - 16;
   1423		repeated_bytes = buf_offset - bytes_shifted;
   1424	}
   1425
   1426	for (i = cnt - 1; i >= 0; i--) {
   1427		data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
   1428		*temp++ = ntohl(data); /* to host byte order */
   1429		DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
   1430	}
   1431
   1432	for (i = repeated_bytes; i < 16; i++)
   1433		buf[j++] = reg[i];
   1434
   1435	return j;
   1436}
   1437
   1438static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
   1439				const struct mipi_dsi_msg *msg)
   1440{
   1441	int len, ret;
   1442	int bllp_len = msm_host->mode->hdisplay *
   1443			dsi_get_bpp(msm_host->format) / 8;
   1444
   1445	len = dsi_cmd_dma_add(msm_host, msg);
   1446	if (len < 0) {
   1447		pr_err("%s: failed to add cmd type = 0x%x\n",
   1448			__func__,  msg->type);
   1449		return len;
   1450	}
   1451
   1452	/* for video mode, do not send cmds more than
   1453	* one pixel line, since it only transmit it
   1454	* during BLLP.
   1455	*/
   1456	/* TODO: if the command is sent in LP mode, the bit rate is only
   1457	 * half of esc clk rate. In this case, if the video is already
   1458	 * actively streaming, we need to check more carefully if the
   1459	 * command can be fit into one BLLP.
   1460	 */
   1461	if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
   1462		pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
   1463			__func__, len);
   1464		return -EINVAL;
   1465	}
   1466
   1467	ret = dsi_cmd_dma_tx(msm_host, len);
   1468	if (ret < 0) {
   1469		pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n",
   1470			__func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret);
   1471		return ret;
   1472	} else if (ret < len) {
   1473		pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n",
   1474			__func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len);
   1475		return -EIO;
   1476	}
   1477
   1478	return len;
   1479}
   1480
   1481static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
   1482{
   1483	u32 data0, data1;
   1484
   1485	data0 = dsi_read(msm_host, REG_DSI_CTRL);
   1486	data1 = data0;
   1487	data1 &= ~DSI_CTRL_ENABLE;
   1488	dsi_write(msm_host, REG_DSI_CTRL, data1);
   1489	/*
   1490	 * dsi controller need to be disabled before
   1491	 * clocks turned on
   1492	 */
   1493	wmb();
   1494
   1495	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
   1496	wmb();	/* make sure clocks enabled */
   1497
   1498	/* dsi controller can only be reset while clocks are running */
   1499	dsi_write(msm_host, REG_DSI_RESET, 1);
   1500	msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
   1501	dsi_write(msm_host, REG_DSI_RESET, 0);
   1502	wmb();	/* controller out of reset */
   1503	dsi_write(msm_host, REG_DSI_CTRL, data0);
   1504	wmb();	/* make sure dsi controller enabled again */
   1505}
   1506
   1507static void dsi_hpd_worker(struct work_struct *work)
   1508{
   1509	struct msm_dsi_host *msm_host =
   1510		container_of(work, struct msm_dsi_host, hpd_work);
   1511
   1512	drm_helper_hpd_irq_event(msm_host->dev);
   1513}
   1514
   1515static void dsi_err_worker(struct work_struct *work)
   1516{
   1517	struct msm_dsi_host *msm_host =
   1518		container_of(work, struct msm_dsi_host, err_work);
   1519	u32 status = msm_host->err_work_state;
   1520
   1521	pr_err_ratelimited("%s: status=%x\n", __func__, status);
   1522	if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
   1523		dsi_sw_reset_restore(msm_host);
   1524
   1525	/* It is safe to clear here because error irq is disabled. */
   1526	msm_host->err_work_state = 0;
   1527
   1528	/* enable dsi error interrupt */
   1529	dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
   1530}
   1531
   1532static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
   1533{
   1534	u32 status;
   1535
   1536	status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
   1537
   1538	if (status) {
   1539		dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
   1540		/* Writing of an extra 0 needed to clear error bits */
   1541		dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
   1542		msm_host->err_work_state |= DSI_ERR_STATE_ACK;
   1543	}
   1544}
   1545
   1546static void dsi_timeout_status(struct msm_dsi_host *msm_host)
   1547{
   1548	u32 status;
   1549
   1550	status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
   1551
   1552	if (status) {
   1553		dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
   1554		msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
   1555	}
   1556}
   1557
   1558static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
   1559{
   1560	u32 status;
   1561
   1562	status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
   1563
   1564	if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
   1565			DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
   1566			DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
   1567			DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
   1568			DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
   1569		dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
   1570		msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
   1571	}
   1572}
   1573
   1574static void dsi_fifo_status(struct msm_dsi_host *msm_host)
   1575{
   1576	u32 status;
   1577
   1578	status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
   1579
   1580	/* fifo underflow, overflow */
   1581	if (status) {
   1582		dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
   1583		msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
   1584		if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
   1585			msm_host->err_work_state |=
   1586					DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
   1587	}
   1588}
   1589
   1590static void dsi_status(struct msm_dsi_host *msm_host)
   1591{
   1592	u32 status;
   1593
   1594	status = dsi_read(msm_host, REG_DSI_STATUS0);
   1595
   1596	if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
   1597		dsi_write(msm_host, REG_DSI_STATUS0, status);
   1598		msm_host->err_work_state |=
   1599			DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
   1600	}
   1601}
   1602
   1603static void dsi_clk_status(struct msm_dsi_host *msm_host)
   1604{
   1605	u32 status;
   1606
   1607	status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
   1608
   1609	if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
   1610		dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
   1611		msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
   1612	}
   1613}
   1614
   1615static void dsi_error(struct msm_dsi_host *msm_host)
   1616{
   1617	/* disable dsi error interrupt */
   1618	dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
   1619
   1620	dsi_clk_status(msm_host);
   1621	dsi_fifo_status(msm_host);
   1622	dsi_ack_err_status(msm_host);
   1623	dsi_timeout_status(msm_host);
   1624	dsi_status(msm_host);
   1625	dsi_dln0_phy_err(msm_host);
   1626
   1627	queue_work(msm_host->workqueue, &msm_host->err_work);
   1628}
   1629
   1630static irqreturn_t dsi_host_irq(int irq, void *ptr)
   1631{
   1632	struct msm_dsi_host *msm_host = ptr;
   1633	u32 isr;
   1634	unsigned long flags;
   1635
   1636	if (!msm_host->ctrl_base)
   1637		return IRQ_HANDLED;
   1638
   1639	spin_lock_irqsave(&msm_host->intr_lock, flags);
   1640	isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
   1641	dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
   1642	spin_unlock_irqrestore(&msm_host->intr_lock, flags);
   1643
   1644	DBG("isr=0x%x, id=%d", isr, msm_host->id);
   1645
   1646	if (isr & DSI_IRQ_ERROR)
   1647		dsi_error(msm_host);
   1648
   1649	if (isr & DSI_IRQ_VIDEO_DONE)
   1650		complete(&msm_host->video_comp);
   1651
   1652	if (isr & DSI_IRQ_CMD_DMA_DONE)
   1653		complete(&msm_host->dma_comp);
   1654
   1655	return IRQ_HANDLED;
   1656}
   1657
   1658static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
   1659			struct device *panel_device)
   1660{
   1661	msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
   1662							 "disp-enable",
   1663							 GPIOD_OUT_LOW);
   1664	if (IS_ERR(msm_host->disp_en_gpio)) {
   1665		DBG("cannot get disp-enable-gpios %ld",
   1666				PTR_ERR(msm_host->disp_en_gpio));
   1667		return PTR_ERR(msm_host->disp_en_gpio);
   1668	}
   1669
   1670	msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
   1671								GPIOD_IN);
   1672	if (IS_ERR(msm_host->te_gpio)) {
   1673		DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
   1674		return PTR_ERR(msm_host->te_gpio);
   1675	}
   1676
   1677	return 0;
   1678}
   1679
   1680static int dsi_host_attach(struct mipi_dsi_host *host,
   1681					struct mipi_dsi_device *dsi)
   1682{
   1683	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   1684	int ret;
   1685
   1686	if (dsi->lanes > msm_host->num_data_lanes)
   1687		return -EINVAL;
   1688
   1689	msm_host->channel = dsi->channel;
   1690	msm_host->lanes = dsi->lanes;
   1691	msm_host->format = dsi->format;
   1692	msm_host->mode_flags = dsi->mode_flags;
   1693
   1694	/* Some gpios defined in panel DT need to be controlled by host */
   1695	ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
   1696	if (ret)
   1697		return ret;
   1698
   1699	ret = dsi_dev_attach(msm_host->pdev);
   1700	if (ret)
   1701		return ret;
   1702
   1703	DBG("id=%d", msm_host->id);
   1704	if (msm_host->dev)
   1705		queue_work(msm_host->workqueue, &msm_host->hpd_work);
   1706
   1707	return 0;
   1708}
   1709
   1710static int dsi_host_detach(struct mipi_dsi_host *host,
   1711					struct mipi_dsi_device *dsi)
   1712{
   1713	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   1714
   1715	dsi_dev_detach(msm_host->pdev);
   1716
   1717	msm_host->device_node = NULL;
   1718
   1719	DBG("id=%d", msm_host->id);
   1720	if (msm_host->dev)
   1721		queue_work(msm_host->workqueue, &msm_host->hpd_work);
   1722
   1723	return 0;
   1724}
   1725
   1726static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
   1727					const struct mipi_dsi_msg *msg)
   1728{
   1729	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   1730	int ret;
   1731
   1732	if (!msg || !msm_host->power_on)
   1733		return -EINVAL;
   1734
   1735	mutex_lock(&msm_host->cmd_mutex);
   1736	ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
   1737	mutex_unlock(&msm_host->cmd_mutex);
   1738
   1739	return ret;
   1740}
   1741
   1742static const struct mipi_dsi_host_ops dsi_host_ops = {
   1743	.attach = dsi_host_attach,
   1744	.detach = dsi_host_detach,
   1745	.transfer = dsi_host_transfer,
   1746};
   1747
   1748/*
   1749 * List of supported physical to logical lane mappings.
   1750 * For example, the 2nd entry represents the following mapping:
   1751 *
   1752 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
   1753 */
   1754static const int supported_data_lane_swaps[][4] = {
   1755	{ 0, 1, 2, 3 },
   1756	{ 3, 0, 1, 2 },
   1757	{ 2, 3, 0, 1 },
   1758	{ 1, 2, 3, 0 },
   1759	{ 0, 3, 2, 1 },
   1760	{ 1, 0, 3, 2 },
   1761	{ 2, 1, 0, 3 },
   1762	{ 3, 2, 1, 0 },
   1763};
   1764
   1765static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
   1766				    struct device_node *ep)
   1767{
   1768	struct device *dev = &msm_host->pdev->dev;
   1769	struct property *prop;
   1770	u32 lane_map[4];
   1771	int ret, i, len, num_lanes;
   1772
   1773	prop = of_find_property(ep, "data-lanes", &len);
   1774	if (!prop) {
   1775		DRM_DEV_DEBUG(dev,
   1776			"failed to find data lane mapping, using default\n");
   1777		/* Set the number of date lanes to 4 by default. */
   1778		msm_host->num_data_lanes = 4;
   1779		return 0;
   1780	}
   1781
   1782	num_lanes = len / sizeof(u32);
   1783
   1784	if (num_lanes < 1 || num_lanes > 4) {
   1785		DRM_DEV_ERROR(dev, "bad number of data lanes\n");
   1786		return -EINVAL;
   1787	}
   1788
   1789	msm_host->num_data_lanes = num_lanes;
   1790
   1791	ret = of_property_read_u32_array(ep, "data-lanes", lane_map,
   1792					 num_lanes);
   1793	if (ret) {
   1794		DRM_DEV_ERROR(dev, "failed to read lane data\n");
   1795		return ret;
   1796	}
   1797
   1798	/*
   1799	 * compare DT specified physical-logical lane mappings with the ones
   1800	 * supported by hardware
   1801	 */
   1802	for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
   1803		const int *swap = supported_data_lane_swaps[i];
   1804		int j;
   1805
   1806		/*
   1807		 * the data-lanes array we get from DT has a logical->physical
   1808		 * mapping. The "data lane swap" register field represents
   1809		 * supported configurations in a physical->logical mapping.
   1810		 * Translate the DT mapping to what we understand and find a
   1811		 * configuration that works.
   1812		 */
   1813		for (j = 0; j < num_lanes; j++) {
   1814			if (lane_map[j] < 0 || lane_map[j] > 3)
   1815				DRM_DEV_ERROR(dev, "bad physical lane entry %u\n",
   1816					lane_map[j]);
   1817
   1818			if (swap[lane_map[j]] != j)
   1819				break;
   1820		}
   1821
   1822		if (j == num_lanes) {
   1823			msm_host->dlane_swap = i;
   1824			return 0;
   1825		}
   1826	}
   1827
   1828	return -EINVAL;
   1829}
   1830
   1831static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
   1832	0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
   1833	0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
   1834};
   1835
   1836/* only 8bpc, 8bpp added */
   1837static char min_qp[DSC_NUM_BUF_RANGES] = {
   1838	0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13
   1839};
   1840
   1841static char max_qp[DSC_NUM_BUF_RANGES] = {
   1842	4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15
   1843};
   1844
   1845static char bpg_offset[DSC_NUM_BUF_RANGES] = {
   1846	2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
   1847};
   1848
   1849static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc)
   1850{
   1851	int mux_words_size;
   1852	int groups_per_line, groups_total;
   1853	int min_rate_buffer_size;
   1854	int hrd_delay;
   1855	int pre_num_extra_mux_bits, num_extra_mux_bits;
   1856	int slice_bits;
   1857	int target_bpp_x16;
   1858	int data;
   1859	int final_value, final_scale;
   1860	int i;
   1861
   1862	dsc->drm->rc_model_size = 8192;
   1863	dsc->drm->first_line_bpg_offset = 12;
   1864	dsc->drm->rc_edge_factor = 6;
   1865	dsc->drm->rc_tgt_offset_high = 3;
   1866	dsc->drm->rc_tgt_offset_low = 3;
   1867	dsc->drm->simple_422 = 0;
   1868	dsc->drm->convert_rgb = 1;
   1869	dsc->drm->vbr_enable = 0;
   1870
   1871	/* handle only bpp = bpc = 8 */
   1872	for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
   1873		dsc->drm->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
   1874
   1875	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
   1876		dsc->drm->rc_range_params[i].range_min_qp = min_qp[i];
   1877		dsc->drm->rc_range_params[i].range_max_qp = max_qp[i];
   1878		dsc->drm->rc_range_params[i].range_bpg_offset = bpg_offset[i];
   1879	}
   1880
   1881	dsc->drm->initial_offset = 6144; /* Not bpp 12 */
   1882	if (dsc->drm->bits_per_pixel != 8)
   1883		dsc->drm->initial_offset = 2048;	/* bpp = 12 */
   1884
   1885	mux_words_size = 48;		/* bpc == 8/10 */
   1886	if (dsc->drm->bits_per_component == 12)
   1887		mux_words_size = 64;
   1888
   1889	dsc->drm->initial_xmit_delay = 512;
   1890	dsc->drm->initial_scale_value = 32;
   1891	dsc->drm->first_line_bpg_offset = 12;
   1892	dsc->drm->line_buf_depth = dsc->drm->bits_per_component + 1;
   1893
   1894	/* bpc 8 */
   1895	dsc->drm->flatness_min_qp = 3;
   1896	dsc->drm->flatness_max_qp = 12;
   1897	dsc->drm->rc_quant_incr_limit0 = 11;
   1898	dsc->drm->rc_quant_incr_limit1 = 11;
   1899	dsc->drm->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
   1900
   1901	/* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of
   1902	 * params are calculated
   1903	 */
   1904	groups_per_line = DIV_ROUND_UP(dsc->drm->slice_width, 3);
   1905	dsc->drm->slice_chunk_size = dsc->drm->slice_width * dsc->drm->bits_per_pixel / 8;
   1906	if ((dsc->drm->slice_width * dsc->drm->bits_per_pixel) % 8)
   1907		dsc->drm->slice_chunk_size++;
   1908
   1909	/* rbs-min */
   1910	min_rate_buffer_size =  dsc->drm->rc_model_size - dsc->drm->initial_offset +
   1911				dsc->drm->initial_xmit_delay * dsc->drm->bits_per_pixel +
   1912				groups_per_line * dsc->drm->first_line_bpg_offset;
   1913
   1914	hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->drm->bits_per_pixel);
   1915
   1916	dsc->drm->initial_dec_delay = hrd_delay - dsc->drm->initial_xmit_delay;
   1917
   1918	dsc->drm->initial_scale_value = 8 * dsc->drm->rc_model_size /
   1919				       (dsc->drm->rc_model_size - dsc->drm->initial_offset);
   1920
   1921	slice_bits = 8 * dsc->drm->slice_chunk_size * dsc->drm->slice_height;
   1922
   1923	groups_total = groups_per_line * dsc->drm->slice_height;
   1924
   1925	data = dsc->drm->first_line_bpg_offset * 2048;
   1926
   1927	dsc->drm->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->drm->slice_height - 1));
   1928
   1929	pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->drm->bits_per_component + 4) - 2);
   1930
   1931	num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size -
   1932			     ((slice_bits - pre_num_extra_mux_bits) % mux_words_size));
   1933
   1934	data = 2048 * (dsc->drm->rc_model_size - dsc->drm->initial_offset + num_extra_mux_bits);
   1935	dsc->drm->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
   1936
   1937	/* bpp * 16 + 0.5 */
   1938	data = dsc->drm->bits_per_pixel * 16;
   1939	data *= 2;
   1940	data++;
   1941	data /= 2;
   1942	target_bpp_x16 = data;
   1943
   1944	data = (dsc->drm->initial_xmit_delay * target_bpp_x16) / 16;
   1945	final_value =  dsc->drm->rc_model_size - data + num_extra_mux_bits;
   1946	dsc->drm->final_offset = final_value;
   1947
   1948	final_scale = 8 * dsc->drm->rc_model_size / (dsc->drm->rc_model_size - final_value);
   1949
   1950	data = (final_scale - 9) * (dsc->drm->nfl_bpg_offset + dsc->drm->slice_bpg_offset);
   1951	dsc->drm->scale_increment_interval = (2048 * dsc->drm->final_offset) / data;
   1952
   1953	dsc->drm->scale_decrement_interval = groups_per_line / (dsc->drm->initial_scale_value - 8);
   1954
   1955	return 0;
   1956}
   1957
   1958static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
   1959{
   1960	struct device *dev = &msm_host->pdev->dev;
   1961	struct device_node *np = dev->of_node;
   1962	struct device_node *endpoint, *device_node;
   1963	int ret = 0;
   1964
   1965	/*
   1966	 * Get the endpoint of the output port of the DSI host. In our case,
   1967	 * this is mapped to port number with reg = 1. Don't return an error if
   1968	 * the remote endpoint isn't defined. It's possible that there is
   1969	 * nothing connected to the dsi output.
   1970	 */
   1971	endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
   1972	if (!endpoint) {
   1973		DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__);
   1974		return 0;
   1975	}
   1976
   1977	ret = dsi_host_parse_lane_data(msm_host, endpoint);
   1978	if (ret) {
   1979		DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n",
   1980			__func__, ret);
   1981		ret = -EINVAL;
   1982		goto err;
   1983	}
   1984
   1985	/* Get panel node from the output port's endpoint data */
   1986	device_node = of_graph_get_remote_node(np, 1, 0);
   1987	if (!device_node) {
   1988		DRM_DEV_DEBUG(dev, "%s: no valid device\n", __func__);
   1989		ret = -ENODEV;
   1990		goto err;
   1991	}
   1992
   1993	msm_host->device_node = device_node;
   1994
   1995	if (of_property_read_bool(np, "syscon-sfpb")) {
   1996		msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
   1997					"syscon-sfpb");
   1998		if (IS_ERR(msm_host->sfpb)) {
   1999			DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n",
   2000				__func__);
   2001			ret = PTR_ERR(msm_host->sfpb);
   2002		}
   2003	}
   2004
   2005	of_node_put(device_node);
   2006
   2007err:
   2008	of_node_put(endpoint);
   2009
   2010	return ret;
   2011}
   2012
   2013static int dsi_host_get_id(struct msm_dsi_host *msm_host)
   2014{
   2015	struct platform_device *pdev = msm_host->pdev;
   2016	const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
   2017	struct resource *res;
   2018	int i;
   2019
   2020	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl");
   2021	if (!res)
   2022		return -EINVAL;
   2023
   2024	for (i = 0; i < cfg->num_dsi; i++) {
   2025		if (cfg->io_start[i] == res->start)
   2026			return i;
   2027	}
   2028
   2029	return -EINVAL;
   2030}
   2031
   2032int msm_dsi_host_init(struct msm_dsi *msm_dsi)
   2033{
   2034	struct msm_dsi_host *msm_host = NULL;
   2035	struct platform_device *pdev = msm_dsi->pdev;
   2036	int ret;
   2037
   2038	msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
   2039	if (!msm_host) {
   2040		ret = -ENOMEM;
   2041		goto fail;
   2042	}
   2043
   2044	msm_host->pdev = pdev;
   2045	msm_dsi->host = &msm_host->base;
   2046
   2047	ret = dsi_host_parse_dt(msm_host);
   2048	if (ret) {
   2049		pr_err("%s: failed to parse dt\n", __func__);
   2050		goto fail;
   2051	}
   2052
   2053	msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size);
   2054	if (IS_ERR(msm_host->ctrl_base)) {
   2055		pr_err("%s: unable to map Dsi ctrl base\n", __func__);
   2056		ret = PTR_ERR(msm_host->ctrl_base);
   2057		goto fail;
   2058	}
   2059
   2060	pm_runtime_enable(&pdev->dev);
   2061
   2062	msm_host->cfg_hnd = dsi_get_config(msm_host);
   2063	if (!msm_host->cfg_hnd) {
   2064		ret = -EINVAL;
   2065		pr_err("%s: get config failed\n", __func__);
   2066		goto fail;
   2067	}
   2068
   2069	msm_host->id = dsi_host_get_id(msm_host);
   2070	if (msm_host->id < 0) {
   2071		ret = msm_host->id;
   2072		pr_err("%s: unable to identify DSI host index\n", __func__);
   2073		goto fail;
   2074	}
   2075
   2076	/* fixup base address by io offset */
   2077	msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset;
   2078
   2079	ret = dsi_regulator_init(msm_host);
   2080	if (ret) {
   2081		pr_err("%s: regulator init failed\n", __func__);
   2082		goto fail;
   2083	}
   2084
   2085	ret = dsi_clk_init(msm_host);
   2086	if (ret) {
   2087		pr_err("%s: unable to initialize dsi clks\n", __func__);
   2088		goto fail;
   2089	}
   2090
   2091	msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
   2092	if (!msm_host->rx_buf) {
   2093		ret = -ENOMEM;
   2094		pr_err("%s: alloc rx temp buf failed\n", __func__);
   2095		goto fail;
   2096	}
   2097
   2098	ret = devm_pm_opp_set_clkname(&pdev->dev, "byte");
   2099	if (ret)
   2100		return ret;
   2101	/* OPP table is optional */
   2102	ret = devm_pm_opp_of_add_table(&pdev->dev);
   2103	if (ret && ret != -ENODEV) {
   2104		dev_err(&pdev->dev, "invalid OPP table in device tree\n");
   2105		return ret;
   2106	}
   2107
   2108	msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
   2109	if (msm_host->irq < 0) {
   2110		ret = msm_host->irq;
   2111		dev_err(&pdev->dev, "failed to get irq: %d\n", ret);
   2112		return ret;
   2113	}
   2114
   2115	/* do not autoenable, will be enabled later */
   2116	ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq,
   2117			IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN,
   2118			"dsi_isr", msm_host);
   2119	if (ret < 0) {
   2120		dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
   2121				msm_host->irq, ret);
   2122		return ret;
   2123	}
   2124
   2125	init_completion(&msm_host->dma_comp);
   2126	init_completion(&msm_host->video_comp);
   2127	mutex_init(&msm_host->dev_mutex);
   2128	mutex_init(&msm_host->cmd_mutex);
   2129	spin_lock_init(&msm_host->intr_lock);
   2130
   2131	/* setup workqueue */
   2132	msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
   2133	INIT_WORK(&msm_host->err_work, dsi_err_worker);
   2134	INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker);
   2135
   2136	msm_dsi->id = msm_host->id;
   2137
   2138	DBG("Dsi Host %d initialized", msm_host->id);
   2139	return 0;
   2140
   2141fail:
   2142	return ret;
   2143}
   2144
   2145void msm_dsi_host_destroy(struct mipi_dsi_host *host)
   2146{
   2147	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2148
   2149	DBG("");
   2150	dsi_tx_buf_free(msm_host);
   2151	if (msm_host->workqueue) {
   2152		destroy_workqueue(msm_host->workqueue);
   2153		msm_host->workqueue = NULL;
   2154	}
   2155
   2156	mutex_destroy(&msm_host->cmd_mutex);
   2157	mutex_destroy(&msm_host->dev_mutex);
   2158
   2159	pm_runtime_disable(&msm_host->pdev->dev);
   2160}
   2161
   2162int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
   2163					struct drm_device *dev)
   2164{
   2165	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2166	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
   2167	struct drm_panel *panel;
   2168	int ret;
   2169
   2170	msm_host->dev = dev;
   2171	panel = msm_dsi_host_get_panel(&msm_host->base);
   2172
   2173	if (!IS_ERR(panel) && panel->dsc) {
   2174		struct msm_display_dsc_config *dsc = msm_host->dsc;
   2175
   2176		if (!dsc) {
   2177			dsc = devm_kzalloc(&msm_host->pdev->dev, sizeof(*dsc), GFP_KERNEL);
   2178			if (!dsc)
   2179				return -ENOMEM;
   2180			dsc->drm = panel->dsc;
   2181			msm_host->dsc = dsc;
   2182		}
   2183	}
   2184
   2185	ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
   2186	if (ret) {
   2187		pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
   2188		return ret;
   2189	}
   2190
   2191	return 0;
   2192}
   2193
   2194int msm_dsi_host_register(struct mipi_dsi_host *host)
   2195{
   2196	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2197	int ret;
   2198
   2199	/* Register mipi dsi host */
   2200	if (!msm_host->registered) {
   2201		host->dev = &msm_host->pdev->dev;
   2202		host->ops = &dsi_host_ops;
   2203		ret = mipi_dsi_host_register(host);
   2204		if (ret)
   2205			return ret;
   2206
   2207		msm_host->registered = true;
   2208	}
   2209
   2210	return 0;
   2211}
   2212
   2213void msm_dsi_host_unregister(struct mipi_dsi_host *host)
   2214{
   2215	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2216
   2217	if (msm_host->registered) {
   2218		mipi_dsi_host_unregister(host);
   2219		host->dev = NULL;
   2220		host->ops = NULL;
   2221		msm_host->registered = false;
   2222	}
   2223}
   2224
   2225int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
   2226				const struct mipi_dsi_msg *msg)
   2227{
   2228	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2229	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
   2230
   2231	/* TODO: make sure dsi_cmd_mdp is idle.
   2232	 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
   2233	 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
   2234	 * How to handle the old versions? Wait for mdp cmd done?
   2235	 */
   2236
   2237	/*
   2238	 * mdss interrupt is generated in mdp core clock domain
   2239	 * mdp clock need to be enabled to receive dsi interrupt
   2240	 */
   2241	pm_runtime_get_sync(&msm_host->pdev->dev);
   2242	cfg_hnd->ops->link_clk_set_rate(msm_host);
   2243	cfg_hnd->ops->link_clk_enable(msm_host);
   2244
   2245	/* TODO: vote for bus bandwidth */
   2246
   2247	if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
   2248		dsi_set_tx_power_mode(0, msm_host);
   2249
   2250	msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
   2251	dsi_write(msm_host, REG_DSI_CTRL,
   2252		msm_host->dma_cmd_ctrl_restore |
   2253		DSI_CTRL_CMD_MODE_EN |
   2254		DSI_CTRL_ENABLE);
   2255	dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
   2256
   2257	return 0;
   2258}
   2259
   2260void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
   2261				const struct mipi_dsi_msg *msg)
   2262{
   2263	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2264	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
   2265
   2266	dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
   2267	dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
   2268
   2269	if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
   2270		dsi_set_tx_power_mode(1, msm_host);
   2271
   2272	/* TODO: unvote for bus bandwidth */
   2273
   2274	cfg_hnd->ops->link_clk_disable(msm_host);
   2275	pm_runtime_put(&msm_host->pdev->dev);
   2276}
   2277
   2278int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
   2279				const struct mipi_dsi_msg *msg)
   2280{
   2281	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2282
   2283	return dsi_cmds2buf_tx(msm_host, msg);
   2284}
   2285
   2286int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
   2287				const struct mipi_dsi_msg *msg)
   2288{
   2289	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2290	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
   2291	int data_byte, rx_byte, dlen, end;
   2292	int short_response, diff, pkt_size, ret = 0;
   2293	char cmd;
   2294	int rlen = msg->rx_len;
   2295	u8 *buf;
   2296
   2297	if (rlen <= 2) {
   2298		short_response = 1;
   2299		pkt_size = rlen;
   2300		rx_byte = 4;
   2301	} else {
   2302		short_response = 0;
   2303		data_byte = 10;	/* first read */
   2304		if (rlen < data_byte)
   2305			pkt_size = rlen;
   2306		else
   2307			pkt_size = data_byte;
   2308		rx_byte = data_byte + 6; /* 4 header + 2 crc */
   2309	}
   2310
   2311	buf = msm_host->rx_buf;
   2312	end = 0;
   2313	while (!end) {
   2314		u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
   2315		struct mipi_dsi_msg max_pkt_size_msg = {
   2316			.channel = msg->channel,
   2317			.type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
   2318			.tx_len = 2,
   2319			.tx_buf = tx,
   2320		};
   2321
   2322		DBG("rlen=%d pkt_size=%d rx_byte=%d",
   2323			rlen, pkt_size, rx_byte);
   2324
   2325		ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
   2326		if (ret < 2) {
   2327			pr_err("%s: Set max pkt size failed, %d\n",
   2328				__func__, ret);
   2329			return -EINVAL;
   2330		}
   2331
   2332		if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
   2333			(cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
   2334			/* Clear the RDBK_DATA registers */
   2335			dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
   2336					DSI_RDBK_DATA_CTRL_CLR);
   2337			wmb(); /* make sure the RDBK registers are cleared */
   2338			dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
   2339			wmb(); /* release cleared status before transfer */
   2340		}
   2341
   2342		ret = dsi_cmds2buf_tx(msm_host, msg);
   2343		if (ret < 0) {
   2344			pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
   2345			return ret;
   2346		} else if (ret < msg->tx_len) {
   2347			pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret);
   2348			return -ECOMM;
   2349		}
   2350
   2351		/*
   2352		 * once cmd_dma_done interrupt received,
   2353		 * return data from client is ready and stored
   2354		 * at RDBK_DATA register already
   2355		 * since rx fifo is 16 bytes, dcs header is kept at first loop,
   2356		 * after that dcs header lost during shift into registers
   2357		 */
   2358		dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
   2359
   2360		if (dlen <= 0)
   2361			return 0;
   2362
   2363		if (short_response)
   2364			break;
   2365
   2366		if (rlen <= data_byte) {
   2367			diff = data_byte - rlen;
   2368			end = 1;
   2369		} else {
   2370			diff = 0;
   2371			rlen -= data_byte;
   2372		}
   2373
   2374		if (!end) {
   2375			dlen -= 2; /* 2 crc */
   2376			dlen -= diff;
   2377			buf += dlen;	/* next start position */
   2378			data_byte = 14;	/* NOT first read */
   2379			if (rlen < data_byte)
   2380				pkt_size += rlen;
   2381			else
   2382				pkt_size += data_byte;
   2383			DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
   2384		}
   2385	}
   2386
   2387	/*
   2388	 * For single Long read, if the requested rlen < 10,
   2389	 * we need to shift the start position of rx
   2390	 * data buffer to skip the bytes which are not
   2391	 * updated.
   2392	 */
   2393	if (pkt_size < 10 && !short_response)
   2394		buf = msm_host->rx_buf + (10 - rlen);
   2395	else
   2396		buf = msm_host->rx_buf;
   2397
   2398	cmd = buf[0];
   2399	switch (cmd) {
   2400	case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
   2401		pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
   2402		ret = 0;
   2403		break;
   2404	case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
   2405	case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
   2406		ret = dsi_short_read1_resp(buf, msg);
   2407		break;
   2408	case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
   2409	case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
   2410		ret = dsi_short_read2_resp(buf, msg);
   2411		break;
   2412	case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
   2413	case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
   2414		ret = dsi_long_read_resp(buf, msg);
   2415		break;
   2416	default:
   2417		pr_warn("%s:Invalid response cmd\n", __func__);
   2418		ret = 0;
   2419	}
   2420
   2421	return ret;
   2422}
   2423
   2424void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
   2425				  u32 len)
   2426{
   2427	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2428
   2429	dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
   2430	dsi_write(msm_host, REG_DSI_DMA_LEN, len);
   2431	dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
   2432
   2433	/* Make sure trigger happens */
   2434	wmb();
   2435}
   2436
   2437void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host,
   2438	struct msm_dsi_phy *src_phy)
   2439{
   2440	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2441
   2442	msm_host->cphy_mode = src_phy->cphy_mode;
   2443}
   2444
   2445void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
   2446{
   2447	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2448
   2449	DBG("");
   2450	dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
   2451	/* Make sure fully reset */
   2452	wmb();
   2453	udelay(1000);
   2454	dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
   2455	udelay(100);
   2456}
   2457
   2458void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
   2459			struct msm_dsi_phy_clk_request *clk_req,
   2460			bool is_bonded_dsi)
   2461{
   2462	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2463	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
   2464	int ret;
   2465
   2466	ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi);
   2467	if (ret) {
   2468		pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
   2469		return;
   2470	}
   2471
   2472	/* CPHY transmits 16 bits over 7 clock cycles
   2473	 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk),
   2474	 * so multiply by 7 to get the "bitclk rate"
   2475	 */
   2476	if (msm_host->cphy_mode)
   2477		clk_req->bitclk_rate = msm_host->byte_clk_rate * 7;
   2478	else
   2479		clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;
   2480	clk_req->escclk_rate = msm_host->esc_clk_rate;
   2481}
   2482
   2483void msm_dsi_host_enable_irq(struct mipi_dsi_host *host)
   2484{
   2485	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2486
   2487	enable_irq(msm_host->irq);
   2488}
   2489
   2490void msm_dsi_host_disable_irq(struct mipi_dsi_host *host)
   2491{
   2492	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2493
   2494	disable_irq(msm_host->irq);
   2495}
   2496
   2497int msm_dsi_host_enable(struct mipi_dsi_host *host)
   2498{
   2499	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2500
   2501	dsi_op_mode_config(msm_host,
   2502		!!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
   2503
   2504	/* TODO: clock should be turned off for command mode,
   2505	 * and only turned on before MDP START.
   2506	 * This part of code should be enabled once mdp driver support it.
   2507	 */
   2508	/* if (msm_panel->mode == MSM_DSI_CMD_MODE) {
   2509	 *	dsi_link_clk_disable(msm_host);
   2510	 *	pm_runtime_put(&msm_host->pdev->dev);
   2511	 * }
   2512	 */
   2513	msm_host->enabled = true;
   2514	return 0;
   2515}
   2516
   2517int msm_dsi_host_disable(struct mipi_dsi_host *host)
   2518{
   2519	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2520
   2521	msm_host->enabled = false;
   2522	dsi_op_mode_config(msm_host,
   2523		!!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
   2524
   2525	/* Since we have disabled INTF, the video engine won't stop so that
   2526	 * the cmd engine will be blocked.
   2527	 * Reset to disable video engine so that we can send off cmd.
   2528	 */
   2529	dsi_sw_reset(msm_host);
   2530
   2531	return 0;
   2532}
   2533
   2534static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
   2535{
   2536	enum sfpb_ahb_arb_master_port_en en;
   2537
   2538	if (!msm_host->sfpb)
   2539		return;
   2540
   2541	en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE;
   2542
   2543	regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG,
   2544			SFPB_GPREG_MASTER_PORT_EN__MASK,
   2545			SFPB_GPREG_MASTER_PORT_EN(en));
   2546}
   2547
   2548int msm_dsi_host_power_on(struct mipi_dsi_host *host,
   2549			struct msm_dsi_phy_shared_timings *phy_shared_timings,
   2550			bool is_bonded_dsi, struct msm_dsi_phy *phy)
   2551{
   2552	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2553	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
   2554	int ret = 0;
   2555
   2556	mutex_lock(&msm_host->dev_mutex);
   2557	if (msm_host->power_on) {
   2558		DBG("dsi host already on");
   2559		goto unlock_ret;
   2560	}
   2561
   2562	msm_dsi_sfpb_config(msm_host, true);
   2563
   2564	ret = dsi_host_regulator_enable(msm_host);
   2565	if (ret) {
   2566		pr_err("%s:Failed to enable vregs.ret=%d\n",
   2567			__func__, ret);
   2568		goto unlock_ret;
   2569	}
   2570
   2571	pm_runtime_get_sync(&msm_host->pdev->dev);
   2572	ret = cfg_hnd->ops->link_clk_set_rate(msm_host);
   2573	if (!ret)
   2574		ret = cfg_hnd->ops->link_clk_enable(msm_host);
   2575	if (ret) {
   2576		pr_err("%s: failed to enable link clocks. ret=%d\n",
   2577		       __func__, ret);
   2578		goto fail_disable_reg;
   2579	}
   2580
   2581	ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
   2582	if (ret) {
   2583		pr_err("%s: failed to set pinctrl default state, %d\n",
   2584			__func__, ret);
   2585		goto fail_disable_clk;
   2586	}
   2587
   2588	dsi_timing_setup(msm_host, is_bonded_dsi);
   2589	dsi_sw_reset(msm_host);
   2590	dsi_ctrl_config(msm_host, true, phy_shared_timings, phy);
   2591
   2592	if (msm_host->disp_en_gpio)
   2593		gpiod_set_value(msm_host->disp_en_gpio, 1);
   2594
   2595	msm_host->power_on = true;
   2596	mutex_unlock(&msm_host->dev_mutex);
   2597
   2598	return 0;
   2599
   2600fail_disable_clk:
   2601	cfg_hnd->ops->link_clk_disable(msm_host);
   2602	pm_runtime_put(&msm_host->pdev->dev);
   2603fail_disable_reg:
   2604	dsi_host_regulator_disable(msm_host);
   2605unlock_ret:
   2606	mutex_unlock(&msm_host->dev_mutex);
   2607	return ret;
   2608}
   2609
   2610int msm_dsi_host_power_off(struct mipi_dsi_host *host)
   2611{
   2612	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2613	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
   2614
   2615	mutex_lock(&msm_host->dev_mutex);
   2616	if (!msm_host->power_on) {
   2617		DBG("dsi host already off");
   2618		goto unlock_ret;
   2619	}
   2620
   2621	dsi_ctrl_config(msm_host, false, NULL, NULL);
   2622
   2623	if (msm_host->disp_en_gpio)
   2624		gpiod_set_value(msm_host->disp_en_gpio, 0);
   2625
   2626	pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
   2627
   2628	cfg_hnd->ops->link_clk_disable(msm_host);
   2629	pm_runtime_put(&msm_host->pdev->dev);
   2630
   2631	dsi_host_regulator_disable(msm_host);
   2632
   2633	msm_dsi_sfpb_config(msm_host, false);
   2634
   2635	DBG("-");
   2636
   2637	msm_host->power_on = false;
   2638
   2639unlock_ret:
   2640	mutex_unlock(&msm_host->dev_mutex);
   2641	return 0;
   2642}
   2643
   2644int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
   2645				  const struct drm_display_mode *mode)
   2646{
   2647	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2648
   2649	if (msm_host->mode) {
   2650		drm_mode_destroy(msm_host->dev, msm_host->mode);
   2651		msm_host->mode = NULL;
   2652	}
   2653
   2654	msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
   2655	if (!msm_host->mode) {
   2656		pr_err("%s: cannot duplicate mode\n", __func__);
   2657		return -ENOMEM;
   2658	}
   2659
   2660	return 0;
   2661}
   2662
   2663enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host,
   2664					    const struct drm_display_mode *mode)
   2665{
   2666	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2667	struct msm_display_dsc_config *dsc = msm_host->dsc;
   2668	int pic_width = mode->hdisplay;
   2669	int pic_height = mode->vdisplay;
   2670
   2671	if (!msm_host->dsc)
   2672		return MODE_OK;
   2673
   2674	if (pic_width % dsc->drm->slice_width) {
   2675		pr_err("DSI: pic_width %d has to be multiple of slice %d\n",
   2676		       pic_width, dsc->drm->slice_width);
   2677		return MODE_H_ILLEGAL;
   2678	}
   2679
   2680	if (pic_height % dsc->drm->slice_height) {
   2681		pr_err("DSI: pic_height %d has to be multiple of slice %d\n",
   2682		       pic_height, dsc->drm->slice_height);
   2683		return MODE_V_ILLEGAL;
   2684	}
   2685
   2686	return MODE_OK;
   2687}
   2688
   2689struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host)
   2690{
   2691	return of_drm_find_panel(to_msm_dsi_host(host)->device_node);
   2692}
   2693
   2694unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host)
   2695{
   2696	return to_msm_dsi_host(host)->mode_flags;
   2697}
   2698
   2699struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host)
   2700{
   2701	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2702
   2703	return of_drm_find_bridge(msm_host->device_node);
   2704}
   2705
   2706void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host)
   2707{
   2708	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2709
   2710	pm_runtime_get_sync(&msm_host->pdev->dev);
   2711
   2712	msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size,
   2713			msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id);
   2714
   2715	pm_runtime_put_sync(&msm_host->pdev->dev);
   2716}
   2717
   2718static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host)
   2719{
   2720	u32 reg;
   2721
   2722	reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
   2723
   2724	dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff);
   2725	/* draw checkered rectangle pattern */
   2726	dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL,
   2727			DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN);
   2728	/* use 24-bit RGB test pttern */
   2729	dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG,
   2730			DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) |
   2731			DSI_TPG_VIDEO_CONFIG_RGB);
   2732
   2733	reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN);
   2734	dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
   2735
   2736	DBG("Video test pattern setup done\n");
   2737}
   2738
   2739static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host)
   2740{
   2741	u32 reg;
   2742
   2743	reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
   2744
   2745	/* initial value for test pattern */
   2746	dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff);
   2747
   2748	reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN);
   2749
   2750	dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
   2751	/* draw checkered rectangle pattern */
   2752	dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2,
   2753			DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN);
   2754
   2755	DBG("Cmd test pattern setup done\n");
   2756}
   2757
   2758void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host)
   2759{
   2760	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2761	bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO);
   2762	u32 reg;
   2763
   2764	if (is_video_mode)
   2765		msm_dsi_host_video_test_pattern_setup(msm_host);
   2766	else
   2767		msm_dsi_host_cmd_test_pattern_setup(msm_host);
   2768
   2769	reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
   2770	/* enable the test pattern generator */
   2771	dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN));
   2772
   2773	/* for command mode need to trigger one frame from tpg */
   2774	if (!is_video_mode)
   2775		dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,
   2776				DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
   2777}
   2778
   2779struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
   2780{
   2781	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
   2782
   2783	return msm_host->dsc;
   2784}