hdmi.h (6690B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7#ifndef __HDMI_CONNECTOR_H__ 8#define __HDMI_CONNECTOR_H__ 9 10#include <linux/i2c.h> 11#include <linux/clk.h> 12#include <linux/platform_device.h> 13#include <linux/regulator/consumer.h> 14#include <linux/gpio/consumer.h> 15#include <linux/hdmi.h> 16 17#include <drm/drm_bridge.h> 18 19#include "msm_drv.h" 20#include "hdmi.xml.h" 21 22#define HDMI_MAX_NUM_GPIO 6 23 24struct hdmi_phy; 25struct hdmi_platform_config; 26 27struct hdmi_gpio_data { 28 struct gpio_desc *gpiod; 29 bool output; 30 int value; 31}; 32 33struct hdmi_audio { 34 bool enabled; 35 struct hdmi_audio_infoframe infoframe; 36 int rate; 37}; 38 39struct hdmi_hdcp_ctrl; 40 41struct hdmi { 42 struct drm_device *dev; 43 struct platform_device *pdev; 44 struct platform_device *audio_pdev; 45 46 const struct hdmi_platform_config *config; 47 48 /* audio state: */ 49 struct hdmi_audio audio; 50 51 /* video state: */ 52 bool power_on; 53 unsigned long int pixclock; 54 55 void __iomem *mmio; 56 void __iomem *qfprom_mmio; 57 phys_addr_t mmio_phy_addr; 58 59 struct regulator_bulk_data *hpd_regs; 60 struct regulator_bulk_data *pwr_regs; 61 struct clk **hpd_clks; 62 struct clk **pwr_clks; 63 64 struct hdmi_phy *phy; 65 struct device *phy_dev; 66 67 struct i2c_adapter *i2c; 68 struct drm_connector *connector; 69 struct drm_bridge *bridge; 70 71 /* the encoder we are hooked to (outside of hdmi block) */ 72 struct drm_encoder *encoder; 73 74 bool hdmi_mode; /* are we in hdmi mode? */ 75 76 int irq; 77 struct workqueue_struct *workq; 78 79 struct hdmi_hdcp_ctrl *hdcp_ctrl; 80 81 /* 82 * spinlock to protect registers shared by different execution 83 * REG_HDMI_CTRL 84 * REG_HDMI_DDC_ARBITRATION 85 * REG_HDMI_HDCP_INT_CTRL 86 * REG_HDMI_HPD_CTRL 87 */ 88 spinlock_t reg_lock; 89}; 90 91/* platform config data (ie. from DT, or pdata) */ 92struct hdmi_platform_config { 93 const char *mmio_name; 94 const char *qfprom_mmio_name; 95 96 /* regulators that need to be on for hpd: */ 97 const char **hpd_reg_names; 98 int hpd_reg_cnt; 99 100 /* regulators that need to be on for screen pwr: */ 101 const char **pwr_reg_names; 102 int pwr_reg_cnt; 103 104 /* clks that need to be on for hpd: */ 105 const char **hpd_clk_names; 106 const long unsigned *hpd_freq; 107 int hpd_clk_cnt; 108 109 /* clks that need to be on for screen pwr (ie pixel clk): */ 110 const char **pwr_clk_names; 111 int pwr_clk_cnt; 112 113 /* gpio's: */ 114 struct hdmi_gpio_data gpios[HDMI_MAX_NUM_GPIO]; 115}; 116 117struct hdmi_bridge { 118 struct drm_bridge base; 119 struct hdmi *hdmi; 120 struct work_struct hpd_work; 121}; 122#define to_hdmi_bridge(x) container_of(x, struct hdmi_bridge, base) 123 124void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on); 125 126static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data) 127{ 128 msm_writel(data, hdmi->mmio + reg); 129} 130 131static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg) 132{ 133 return msm_readl(hdmi->mmio + reg); 134} 135 136static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg) 137{ 138 return msm_readl(hdmi->qfprom_mmio + reg); 139} 140 141/* 142 * hdmi phy: 143 */ 144 145enum hdmi_phy_type { 146 MSM_HDMI_PHY_8x60, 147 MSM_HDMI_PHY_8960, 148 MSM_HDMI_PHY_8x74, 149 MSM_HDMI_PHY_8996, 150 MSM_HDMI_PHY_MAX, 151}; 152 153struct hdmi_phy_cfg { 154 enum hdmi_phy_type type; 155 void (*powerup)(struct hdmi_phy *phy, unsigned long int pixclock); 156 void (*powerdown)(struct hdmi_phy *phy); 157 const char * const *reg_names; 158 int num_regs; 159 const char * const *clk_names; 160 int num_clks; 161}; 162 163extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg; 164extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg; 165extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg; 166extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg; 167 168struct hdmi_phy { 169 struct platform_device *pdev; 170 void __iomem *mmio; 171 struct hdmi_phy_cfg *cfg; 172 const struct hdmi_phy_funcs *funcs; 173 struct regulator_bulk_data *regs; 174 struct clk **clks; 175}; 176 177static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data) 178{ 179 msm_writel(data, phy->mmio + reg); 180} 181 182static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg) 183{ 184 return msm_readl(phy->mmio + reg); 185} 186 187int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy); 188void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy); 189void msm_hdmi_phy_powerup(struct hdmi_phy *phy, unsigned long int pixclock); 190void msm_hdmi_phy_powerdown(struct hdmi_phy *phy); 191void __init msm_hdmi_phy_driver_register(void); 192void __exit msm_hdmi_phy_driver_unregister(void); 193 194#ifdef CONFIG_COMMON_CLK 195int msm_hdmi_pll_8960_init(struct platform_device *pdev); 196int msm_hdmi_pll_8996_init(struct platform_device *pdev); 197#else 198static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev) 199{ 200 return -ENODEV; 201} 202 203static inline int msm_hdmi_pll_8996_init(struct platform_device *pdev) 204{ 205 return -ENODEV; 206} 207#endif 208 209/* 210 * audio: 211 */ 212/* Supported HDMI Audio channels and rates */ 213#define MSM_HDMI_AUDIO_CHANNEL_2 0 214#define MSM_HDMI_AUDIO_CHANNEL_4 1 215#define MSM_HDMI_AUDIO_CHANNEL_6 2 216#define MSM_HDMI_AUDIO_CHANNEL_8 3 217 218#define HDMI_SAMPLE_RATE_32KHZ 0 219#define HDMI_SAMPLE_RATE_44_1KHZ 1 220#define HDMI_SAMPLE_RATE_48KHZ 2 221#define HDMI_SAMPLE_RATE_88_2KHZ 3 222#define HDMI_SAMPLE_RATE_96KHZ 4 223#define HDMI_SAMPLE_RATE_176_4KHZ 5 224#define HDMI_SAMPLE_RATE_192KHZ 6 225 226int msm_hdmi_audio_update(struct hdmi *hdmi); 227int msm_hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled, 228 uint32_t num_of_channels, uint32_t channel_allocation, 229 uint32_t level_shift, bool down_mix); 230void msm_hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate); 231 232 233/* 234 * hdmi bridge: 235 */ 236 237struct drm_bridge *msm_hdmi_bridge_init(struct hdmi *hdmi); 238void msm_hdmi_bridge_destroy(struct drm_bridge *bridge); 239 240void msm_hdmi_hpd_irq(struct drm_bridge *bridge); 241enum drm_connector_status msm_hdmi_bridge_detect( 242 struct drm_bridge *bridge); 243int msm_hdmi_hpd_enable(struct drm_bridge *bridge); 244void msm_hdmi_hpd_disable(struct hdmi_bridge *hdmi_bridge); 245 246/* 247 * i2c adapter for ddc: 248 */ 249 250void msm_hdmi_i2c_irq(struct i2c_adapter *i2c); 251void msm_hdmi_i2c_destroy(struct i2c_adapter *i2c); 252struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi); 253 254/* 255 * hdcp 256 */ 257#ifdef CONFIG_DRM_MSM_HDMI_HDCP 258struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi); 259void msm_hdmi_hdcp_destroy(struct hdmi *hdmi); 260void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl); 261void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl); 262void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl); 263#else 264static inline struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi) 265{ 266 return ERR_PTR(-ENXIO); 267} 268static inline void msm_hdmi_hdcp_destroy(struct hdmi *hdmi) {} 269static inline void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl) {} 270static inline void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) {} 271static inline void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl) {} 272#endif 273 274#endif /* __HDMI_CONNECTOR_H__ */