cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

cl887d.h (4989B)


      1/*
      2 * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
     20 * DEALINGS IN THE SOFTWARE.
     21 */
     22
     23
     24#ifndef _cl887d_h_
     25#define _cl887d_h_
     26
     27#define NV887D_SOR_SET_CONTROL(a)                                               (0x00000600 + (a)*0x00000040)
     28#define NV887D_SOR_SET_CONTROL_OWNER                                            3:0
     29#define NV887D_SOR_SET_CONTROL_OWNER_NONE                                       (0x00000000)
     30#define NV887D_SOR_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
     31#define NV887D_SOR_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
     32#define NV887D_SOR_SET_CONTROL_SUB_OWNER                                        5:4
     33#define NV887D_SOR_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
     34#define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
     35#define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
     36#define NV887D_SOR_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
     37#define NV887D_SOR_SET_CONTROL_PROTOCOL                                         11:8
     38#define NV887D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
     39#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
     40#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
     41#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB                          (0x00000003)
     42#define NV887D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS                        (0x00000004)
     43#define NV887D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
     44#define NV887D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT                                 (0x00000007)
     45#define NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A                                    (0x00000008)
     46#define NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B                                    (0x00000009)
     47#define NV887D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
     48#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY                                   12:12
     49#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
     50#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
     51#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY                                   13:13
     52#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
     53#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
     54#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
     55#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
     56#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
     57#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH                                      19:16
     58#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT                              (0x00000000)
     59#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422                           (0x00000001)
     60#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444                           (0x00000002)
     61#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422                           (0x00000003)
     62#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422                           (0x00000004)
     63#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444                           (0x00000005)
     64#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444                           (0x00000006)
     65#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422                           (0x00000007)
     66#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444                           (0x00000008)
     67#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444                           (0x00000009)
     68#endif // _cl887d_h