cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

nv50_fence.c (3103B)

      1/*
      2 * Copyright 2012 Red Hat Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: Ben Skeggs <bskeggs@redhat.com>
     23 */
     24
     25#include <nvif/os.h>
     26#include <nvif/class.h>
     27#include <nvif/cl0002.h>
     28
     29#include "nouveau_drv.h"
     30#include "nouveau_dma.h"
     31#include "nv10_fence.h"
     32
     33#include "nv50_display.h"
     34
     35static int
     36nv50_fence_context_new(struct nouveau_channel *chan)
     37{
     38	struct nv10_fence_priv *priv = chan->drm->fence;
     39	struct nv10_fence_chan *fctx;
     40	struct ttm_resource *reg = priv->bo->bo.resource;
     41	u32 start = reg->start * PAGE_SIZE;
     42	u32 limit = start + priv->bo->bo.base.size - 1;
     43	int ret;
     44
     45	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
     46	if (!fctx)
     47		return -ENOMEM;
     48
     49	nouveau_fence_context_new(chan, &fctx->base);
     50	fctx->base.emit = nv10_fence_emit;
     51	fctx->base.read = nv10_fence_read;
     52	fctx->base.sync = nv17_fence_sync;
     53
     54	ret = nvif_object_ctor(&chan->user, "fenceCtxDma", NvSema,
     55			       NV_DMA_IN_MEMORY,
     56			       &(struct nv_dma_v0) {
     57					.target = NV_DMA_V0_TARGET_VRAM,
     58					.access = NV_DMA_V0_ACCESS_RDWR,
     59					.start = start,
     60					.limit = limit,
     61			       }, sizeof(struct nv_dma_v0),
     62			       &fctx->sema);
     63	if (ret)
     64		nv10_fence_context_del(chan);
     65	return ret;
     66}
     67
     68int
     69nv50_fence_create(struct nouveau_drm *drm)
     70{
     71	struct nv10_fence_priv *priv;
     72	int ret = 0;
     73
     74	priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
     75	if (!priv)
     76		return -ENOMEM;
     77
     78	priv->base.dtor = nv10_fence_destroy;
     79	priv->base.resume = nv17_fence_resume;
     80	priv->base.context_new = nv50_fence_context_new;
     81	priv->base.context_del = nv10_fence_context_del;
     82	spin_lock_init(&priv->lock);
     83
     84	ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
     85			     NOUVEAU_GEM_DOMAIN_VRAM,
     86			     0, 0x0000, NULL, NULL, &priv->bo);
     87	if (!ret) {
     88		ret = nouveau_bo_pin(priv->bo, NOUVEAU_GEM_DOMAIN_VRAM, false);
     89		if (!ret) {
     90			ret = nouveau_bo_map(priv->bo);
     91			if (ret)
     92				nouveau_bo_unpin(priv->bo);
     93		}
     94		if (ret)
     95			nouveau_bo_ref(NULL, &priv->bo);
     96	}
     97
     98	if (ret) {
     99		nv10_fence_destroy(drm);
    100		return ret;
    101	}
    102
    103	nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
    104	return ret;
    105}