cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

baseg84.c (2288B)

      1/*
      2 * Copyright 2012 Red Hat Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: Ben Skeggs
     23 */
     24#include "channv50.h"
     25
     26static const struct nv50_disp_mthd_list
     27g84_disp_base_mthd_base = {
     28	.mthd = 0x0000,
     29	.addr = 0x000000,
     30	.data = {
     31		{ 0x0080, 0x000000 },
     32		{ 0x0084, 0x0008c4 },
     33		{ 0x0088, 0x0008d0 },
     34		{ 0x008c, 0x0008dc },
     35		{ 0x0090, 0x0008e4 },
     36		{ 0x0094, 0x610884 },
     37		{ 0x00a0, 0x6108a0 },
     38		{ 0x00a4, 0x610878 },
     39		{ 0x00c0, 0x61086c },
     40		{ 0x00c4, 0x610800 },
     41		{ 0x00c8, 0x61080c },
     42		{ 0x00cc, 0x610818 },
     43		{ 0x00e0, 0x610858 },
     44		{ 0x00e4, 0x610860 },
     45		{ 0x00e8, 0x6108ac },
     46		{ 0x00ec, 0x6108b4 },
     47		{ 0x00fc, 0x610824 },
     48		{ 0x0100, 0x610894 },
     49		{ 0x0104, 0x61082c },
     50		{ 0x0110, 0x6108bc },
     51		{ 0x0114, 0x61088c },
     52		{}
     53	}
     54};
     55
     56static const struct nv50_disp_chan_mthd
     57g84_disp_base_mthd = {
     58	.name = "Base",
     59	.addr = 0x000540,
     60	.prev = 0x000004,
     61	.data = {
     62		{ "Global", 1, &g84_disp_base_mthd_base },
     63		{  "Image", 2, &nv50_disp_base_mthd_image },
     64		{}
     65	}
     66};
     67
     68int
     69g84_disp_base_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
     70		  struct nv50_disp *disp, struct nvkm_object **pobject)
     71{
     72	return nv50_disp_base_new_(&nv50_disp_dmac_func, &g84_disp_base_mthd,
     73				   disp, 1, oclass, argv, argc, pobject);
     74}