cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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coreg84.c (3129B)


      1/*
      2 * Copyright 2012 Red Hat Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: Ben Skeggs
     23 */
     24#include "channv50.h"
     25
     26const struct nv50_disp_mthd_list
     27g84_disp_core_mthd_dac = {
     28	.mthd = 0x0080,
     29	.addr = 0x000008,
     30	.data = {
     31		{ 0x0400, 0x610b58 },
     32		{ 0x0404, 0x610bdc },
     33		{ 0x0420, 0x610bc4 },
     34		{}
     35	}
     36};
     37
     38const struct nv50_disp_mthd_list
     39g84_disp_core_mthd_head = {
     40	.mthd = 0x0400,
     41	.addr = 0x000540,
     42	.data = {
     43		{ 0x0800, 0x610ad8 },
     44		{ 0x0804, 0x610ad0 },
     45		{ 0x0808, 0x610a48 },
     46		{ 0x080c, 0x610a78 },
     47		{ 0x0810, 0x610ac0 },
     48		{ 0x0814, 0x610af8 },
     49		{ 0x0818, 0x610b00 },
     50		{ 0x081c, 0x610ae8 },
     51		{ 0x0820, 0x610af0 },
     52		{ 0x0824, 0x610b08 },
     53		{ 0x0828, 0x610b10 },
     54		{ 0x082c, 0x610a68 },
     55		{ 0x0830, 0x610a60 },
     56		{ 0x0834, 0x000000 },
     57		{ 0x0838, 0x610a40 },
     58		{ 0x0840, 0x610a24 },
     59		{ 0x0844, 0x610a2c },
     60		{ 0x0848, 0x610aa8 },
     61		{ 0x084c, 0x610ab0 },
     62		{ 0x085c, 0x610c5c },
     63		{ 0x0860, 0x610a84 },
     64		{ 0x0864, 0x610a90 },
     65		{ 0x0868, 0x610b18 },
     66		{ 0x086c, 0x610b20 },
     67		{ 0x0870, 0x610ac8 },
     68		{ 0x0874, 0x610a38 },
     69		{ 0x0878, 0x610c50 },
     70		{ 0x0880, 0x610a58 },
     71		{ 0x0884, 0x610a9c },
     72		{ 0x089c, 0x610c68 },
     73		{ 0x08a0, 0x610a70 },
     74		{ 0x08a4, 0x610a50 },
     75		{ 0x08a8, 0x610ae0 },
     76		{ 0x08c0, 0x610b28 },
     77		{ 0x08c4, 0x610b30 },
     78		{ 0x08c8, 0x610b40 },
     79		{ 0x08d4, 0x610b38 },
     80		{ 0x08d8, 0x610b48 },
     81		{ 0x08dc, 0x610b50 },
     82		{ 0x0900, 0x610a18 },
     83		{ 0x0904, 0x610ab8 },
     84		{ 0x0910, 0x610c70 },
     85		{ 0x0914, 0x610c78 },
     86		{}
     87	}
     88};
     89
     90const struct nv50_disp_chan_mthd
     91g84_disp_core_mthd = {
     92	.name = "Core",
     93	.addr = 0x000000,
     94	.prev = 0x000004,
     95	.data = {
     96		{ "Global", 1, &nv50_disp_core_mthd_base },
     97		{    "DAC", 3, &g84_disp_core_mthd_dac  },
     98		{    "SOR", 2, &nv50_disp_core_mthd_sor  },
     99		{   "PIOR", 3, &nv50_disp_core_mthd_pior },
    100		{   "HEAD", 2, &g84_disp_core_mthd_head },
    101		{}
    102	}
    103};
    104
    105int
    106g84_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
    107		  struct nv50_disp *disp, struct nvkm_object **pobject)
    108{
    109	return nv50_disp_core_new_(&nv50_disp_core_func, &g84_disp_core_mthd,
    110				   disp, 0, oclass, argv, argc, pobject);
    111}