corenv50.c (6247B)
1/* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24#include "channv50.h" 25 26#include <core/client.h> 27#include <subdev/timer.h> 28 29#include <nvif/cl507d.h> 30#include <nvif/unpack.h> 31 32int 33nv50_disp_core_new_(const struct nv50_disp_chan_func *func, 34 const struct nv50_disp_chan_mthd *mthd, 35 struct nv50_disp *disp, int chid, 36 const struct nvkm_oclass *oclass, void *argv, u32 argc, 37 struct nvkm_object **pobject) 38{ 39 union { 40 struct nv50_disp_core_channel_dma_v0 v0; 41 } *args = argv; 42 struct nvkm_object *parent = oclass->parent; 43 u64 push; 44 int ret = -ENOSYS; 45 46 nvif_ioctl(parent, "create disp core channel dma size %d\n", argc); 47 if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) { 48 nvif_ioctl(parent, "create disp core channel dma vers %d " 49 "pushbuf %016llx\n", 50 args->v0.version, args->v0.pushbuf); 51 push = args->v0.pushbuf; 52 } else 53 return ret; 54 55 return nv50_disp_dmac_new_(func, mthd, disp, chid, 0, 56 push, oclass, pobject); 57} 58 59const struct nv50_disp_mthd_list 60nv50_disp_core_mthd_base = { 61 .mthd = 0x0000, 62 .addr = 0x000000, 63 .data = { 64 { 0x0080, 0x000000 }, 65 { 0x0084, 0x610bb8 }, 66 { 0x0088, 0x610b9c }, 67 { 0x008c, 0x000000 }, 68 {} 69 } 70}; 71 72static const struct nv50_disp_mthd_list 73nv50_disp_core_mthd_dac = { 74 .mthd = 0x0080, 75 .addr = 0x000008, 76 .data = { 77 { 0x0400, 0x610b58 }, 78 { 0x0404, 0x610bdc }, 79 { 0x0420, 0x610828 }, 80 {} 81 } 82}; 83 84const struct nv50_disp_mthd_list 85nv50_disp_core_mthd_sor = { 86 .mthd = 0x0040, 87 .addr = 0x000008, 88 .data = { 89 { 0x0600, 0x610b70 }, 90 {} 91 } 92}; 93 94const struct nv50_disp_mthd_list 95nv50_disp_core_mthd_pior = { 96 .mthd = 0x0040, 97 .addr = 0x000008, 98 .data = { 99 { 0x0700, 0x610b80 }, 100 {} 101 } 102}; 103 104static const struct nv50_disp_mthd_list 105nv50_disp_core_mthd_head = { 106 .mthd = 0x0400, 107 .addr = 0x000540, 108 .data = { 109 { 0x0800, 0x610ad8 }, 110 { 0x0804, 0x610ad0 }, 111 { 0x0808, 0x610a48 }, 112 { 0x080c, 0x610a78 }, 113 { 0x0810, 0x610ac0 }, 114 { 0x0814, 0x610af8 }, 115 { 0x0818, 0x610b00 }, 116 { 0x081c, 0x610ae8 }, 117 { 0x0820, 0x610af0 }, 118 { 0x0824, 0x610b08 }, 119 { 0x0828, 0x610b10 }, 120 { 0x082c, 0x610a68 }, 121 { 0x0830, 0x610a60 }, 122 { 0x0834, 0x000000 }, 123 { 0x0838, 0x610a40 }, 124 { 0x0840, 0x610a24 }, 125 { 0x0844, 0x610a2c }, 126 { 0x0848, 0x610aa8 }, 127 { 0x084c, 0x610ab0 }, 128 { 0x0860, 0x610a84 }, 129 { 0x0864, 0x610a90 }, 130 { 0x0868, 0x610b18 }, 131 { 0x086c, 0x610b20 }, 132 { 0x0870, 0x610ac8 }, 133 { 0x0874, 0x610a38 }, 134 { 0x0880, 0x610a58 }, 135 { 0x0884, 0x610a9c }, 136 { 0x08a0, 0x610a70 }, 137 { 0x08a4, 0x610a50 }, 138 { 0x08a8, 0x610ae0 }, 139 { 0x08c0, 0x610b28 }, 140 { 0x08c4, 0x610b30 }, 141 { 0x08c8, 0x610b40 }, 142 { 0x08d4, 0x610b38 }, 143 { 0x08d8, 0x610b48 }, 144 { 0x08dc, 0x610b50 }, 145 { 0x0900, 0x610a18 }, 146 { 0x0904, 0x610ab8 }, 147 {} 148 } 149}; 150 151static const struct nv50_disp_chan_mthd 152nv50_disp_core_mthd = { 153 .name = "Core", 154 .addr = 0x000000, 155 .prev = 0x000004, 156 .data = { 157 { "Global", 1, &nv50_disp_core_mthd_base }, 158 { "DAC", 3, &nv50_disp_core_mthd_dac }, 159 { "SOR", 2, &nv50_disp_core_mthd_sor }, 160 { "PIOR", 3, &nv50_disp_core_mthd_pior }, 161 { "HEAD", 2, &nv50_disp_core_mthd_head }, 162 {} 163 } 164}; 165 166static void 167nv50_disp_core_fini(struct nv50_disp_chan *chan) 168{ 169 struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; 170 struct nvkm_device *device = subdev->device; 171 172 /* deactivate channel */ 173 nvkm_mask(device, 0x610200, 0x00000010, 0x00000000); 174 nvkm_mask(device, 0x610200, 0x00000003, 0x00000000); 175 if (nvkm_msec(device, 2000, 176 if (!(nvkm_rd32(device, 0x610200) & 0x001e0000)) 177 break; 178 ) < 0) { 179 nvkm_error(subdev, "core fini: %08x\n", 180 nvkm_rd32(device, 0x610200)); 181 } 182 183 chan->suspend_put = nvkm_rd32(device, 0x640000); 184} 185 186static int 187nv50_disp_core_init(struct nv50_disp_chan *chan) 188{ 189 struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev; 190 struct nvkm_device *device = subdev->device; 191 192 /* attempt to unstick channel from some unknown state */ 193 if ((nvkm_rd32(device, 0x610200) & 0x009f0000) == 0x00020000) 194 nvkm_mask(device, 0x610200, 0x00800000, 0x00800000); 195 if ((nvkm_rd32(device, 0x610200) & 0x003f0000) == 0x00030000) 196 nvkm_mask(device, 0x610200, 0x00600000, 0x00600000); 197 198 /* initialise channel for dma command submission */ 199 nvkm_wr32(device, 0x610204, chan->push); 200 nvkm_wr32(device, 0x610208, 0x00010000); 201 nvkm_wr32(device, 0x61020c, 0x00000000); 202 nvkm_mask(device, 0x610200, 0x00000010, 0x00000010); 203 nvkm_wr32(device, 0x640000, chan->suspend_put); 204 nvkm_wr32(device, 0x610200, 0x01000013); 205 206 /* wait for it to go inactive */ 207 if (nvkm_msec(device, 2000, 208 if (!(nvkm_rd32(device, 0x610200) & 0x80000000)) 209 break; 210 ) < 0) { 211 nvkm_error(subdev, "core init: %08x\n", 212 nvkm_rd32(device, 0x610200)); 213 return -EBUSY; 214 } 215 216 return 0; 217} 218 219const struct nv50_disp_chan_func 220nv50_disp_core_func = { 221 .init = nv50_disp_core_init, 222 .fini = nv50_disp_core_fini, 223 .intr = nv50_disp_chan_intr, 224 .user = nv50_disp_chan_user, 225 .bind = nv50_disp_dmac_bind, 226}; 227 228int 229nv50_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, 230 struct nv50_disp *disp, struct nvkm_object **pobject) 231{ 232 return nv50_disp_core_new_(&nv50_disp_core_func, &nv50_disp_core_mthd, 233 disp, 0, oclass, argv, argc, pobject); 234}