dp.h (7557B)
1/* SPDX-License-Identifier: MIT */ 2#ifndef __NVKM_DISP_DP_H__ 3#define __NVKM_DISP_DP_H__ 4#define nvkm_dp(p) container_of((p), struct nvkm_dp, outp) 5#include "outp.h" 6 7#include <core/notify.h> 8#include <subdev/bios.h> 9#include <subdev/bios/dp.h> 10 11struct nvkm_dp { 12 struct nvkm_outp outp; 13 14 struct nvbios_dpout info; 15 u8 version; 16 17 struct nvkm_i2c_aux *aux; 18 19 struct nvkm_notify hpd; 20 bool present; 21 u8 lttpr[6]; 22 u8 lttprs; 23 u8 dpcd[16]; 24 25 struct { 26 int dpcd; /* -1, or index into SUPPORTED_LINK_RATES table */ 27 u32 rate; 28 } rate[8]; 29 int rates; 30 int links; 31 32 struct mutex mutex; 33 struct { 34 atomic_t done; 35 bool mst; 36 } lt; 37}; 38 39int nvkm_dp_new(struct nvkm_disp *, int index, struct dcb_output *, 40 struct nvkm_outp **); 41void nvkm_dp_disable(struct nvkm_outp *, struct nvkm_ior *); 42 43/* DPCD Receiver Capabilities */ 44#define DPCD_RC00_DPCD_REV 0x00000 45#define DPCD_RC01_MAX_LINK_RATE 0x00001 46#define DPCD_RC02 0x00002 47#define DPCD_RC02_ENHANCED_FRAME_CAP 0x80 48#define DPCD_RC02_TPS3_SUPPORTED 0x40 49#define DPCD_RC02_MAX_LANE_COUNT 0x1f 50#define DPCD_RC03 0x00003 51#define DPCD_RC03_TPS4_SUPPORTED 0x80 52#define DPCD_RC03_MAX_DOWNSPREAD 0x01 53#define DPCD_RC0E 0x0000e 54#define DPCD_RC0E_AUX_RD_INTERVAL 0x7f 55#define DPCD_RC10_SUPPORTED_LINK_RATES(i) 0x00010 56#define DPCD_RC10_SUPPORTED_LINK_RATES__SIZE 16 57 58/* DPCD Link Configuration */ 59#define DPCD_LC00_LINK_BW_SET 0x00100 60#define DPCD_LC01 0x00101 61#define DPCD_LC01_ENHANCED_FRAME_EN 0x80 62#define DPCD_LC01_LANE_COUNT_SET 0x1f 63#define DPCD_LC02 0x00102 64#define DPCD_LC02_TRAINING_PATTERN_SET 0x0f 65#define DPCD_LC02_SCRAMBLING_DISABLE 0x20 66#define DPCD_LC03(l) ((l) + 0x00103) 67#define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED 0x20 68#define DPCD_LC03_PRE_EMPHASIS_SET 0x18 69#define DPCD_LC03_MAX_SWING_REACHED 0x04 70#define DPCD_LC03_VOLTAGE_SWING_SET 0x03 71#define DPCD_LC0F 0x0010f 72#define DPCD_LC0F_LANE1_MAX_POST_CURSOR2_REACHED 0x40 73#define DPCD_LC0F_LANE1_POST_CURSOR2_SET 0x30 74#define DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED 0x04 75#define DPCD_LC0F_LANE0_POST_CURSOR2_SET 0x03 76#define DPCD_LC10 0x00110 77#define DPCD_LC10_LANE3_MAX_POST_CURSOR2_REACHED 0x40 78#define DPCD_LC10_LANE3_POST_CURSOR2_SET 0x30 79#define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED 0x04 80#define DPCD_LC10_LANE2_POST_CURSOR2_SET 0x03 81#define DPCD_LC15_LINK_RATE_SET 0x00115 82#define DPCD_LC15_LINK_RATE_SET_MASK 0x07 83 84/* DPCD Link/Sink Status */ 85#define DPCD_LS02 0x00202 86#define DPCD_LS02_LANE1_SYMBOL_LOCKED 0x40 87#define DPCD_LS02_LANE1_CHANNEL_EQ_DONE 0x20 88#define DPCD_LS02_LANE1_CR_DONE 0x10 89#define DPCD_LS02_LANE0_SYMBOL_LOCKED 0x04 90#define DPCD_LS02_LANE0_CHANNEL_EQ_DONE 0x02 91#define DPCD_LS02_LANE0_CR_DONE 0x01 92#define DPCD_LS03 0x00203 93#define DPCD_LS03_LANE3_SYMBOL_LOCKED 0x40 94#define DPCD_LS03_LANE3_CHANNEL_EQ_DONE 0x20 95#define DPCD_LS03_LANE3_CR_DONE 0x10 96#define DPCD_LS03_LANE2_SYMBOL_LOCKED 0x04 97#define DPCD_LS03_LANE2_CHANNEL_EQ_DONE 0x02 98#define DPCD_LS03_LANE2_CR_DONE 0x01 99#define DPCD_LS04 0x00204 100#define DPCD_LS04_LINK_STATUS_UPDATED 0x80 101#define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED 0x40 102#define DPCD_LS04_INTERLANE_ALIGN_DONE 0x01 103#define DPCD_LS06 0x00206 104#define DPCD_LS06_LANE1_PRE_EMPHASIS 0xc0 105#define DPCD_LS06_LANE1_VOLTAGE_SWING 0x30 106#define DPCD_LS06_LANE0_PRE_EMPHASIS 0x0c 107#define DPCD_LS06_LANE0_VOLTAGE_SWING 0x03 108#define DPCD_LS07 0x00207 109#define DPCD_LS07_LANE3_PRE_EMPHASIS 0xc0 110#define DPCD_LS07_LANE3_VOLTAGE_SWING 0x30 111#define DPCD_LS07_LANE2_PRE_EMPHASIS 0x0c 112#define DPCD_LS07_LANE2_VOLTAGE_SWING 0x03 113#define DPCD_LS0C 0x0020c 114#define DPCD_LS0C_LANE3_POST_CURSOR2 0xc0 115#define DPCD_LS0C_LANE2_POST_CURSOR2 0x30 116#define DPCD_LS0C_LANE1_POST_CURSOR2 0x0c 117#define DPCD_LS0C_LANE0_POST_CURSOR2 0x03 118 119/* DPCD Sink Control */ 120#define DPCD_SC00 0x00600 121#define DPCD_SC00_SET_POWER 0x03 122#define DPCD_SC00_SET_POWER_D0 0x01 123#define DPCD_SC00_SET_POWER_D3 0x03 124 125#define DPCD_LTTPR_REV 0xf0000 126#define DPCD_LTTPR_MODE 0xf0003 127#define DPCD_LTTPR_MODE_TRANSPARENT 0x55 128#define DPCD_LTTPR_MODE_NON_TRANSPARENT 0xaa 129#define DPCD_LTTPR_PATTERN_SET(i) ((i - 1) * 0x50 + 0xf0010) 130#define DPCD_LTTPR_LANE0_SET(i) ((i - 1) * 0x50 + 0xf0011) 131#define DPCD_LTTPR_AUX_RD_INTERVAL(i) ((i - 1) * 0x50 + 0xf0020) 132#define DPCD_LTTPR_LANE0_1_STATUS(i) ((i - 1) * 0x50 + 0xf0030) 133#define DPCD_LTTPR_LANE0_1_ADJUST(i) ((i - 1) * 0x50 + 0xf0033) 134#endif