cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

rootgp102.c (2038B)

      1/*
      2 * Copyright 2016 Red Hat Inc.
      3 *
      4 * Permission is hereby granted, free of charge, to any person obtaining a
      5 * copy of this software and associated documentation files (the "Software"),
      6 * to deal in the Software without restriction, including without limitation
      7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
      8 * and/or sell copies of the Software, and to permit persons to whom the
      9 * Software is furnished to do so, subject to the following conditions:
     10 *
     11 * The above copyright notice and this permission notice shall be included in
     12 * all copies or substantial portions of the Software.
     13 *
     14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     20 * OTHER DEALINGS IN THE SOFTWARE.
     21 *
     22 * Authors: Ben Skeggs <bskeggs@redhat.com>
     23 */
     24#include "rootnv50.h"
     25#include "channv50.h"
     26
     27#include <nvif/class.h>
     28
     29static const struct nv50_disp_root_func
     30gp102_disp_root = {
     31	.user = {
     32		{{0,0,GK104_DISP_CURSOR             }, gp102_disp_curs_new },
     33		{{0,0,GK104_DISP_OVERLAY            }, gp102_disp_oimm_new },
     34		{{0,0,GK110_DISP_BASE_CHANNEL_DMA   }, gp102_disp_base_new },
     35		{{0,0,GP102_DISP_CORE_CHANNEL_DMA   }, gp102_disp_core_new },
     36		{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, gp102_disp_ovly_new },
     37		{}
     38	},
     39};
     40
     41static int
     42gp102_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass,
     43		    void *data, u32 size, struct nvkm_object **pobject)
     44{
     45	return nv50_disp_root_new_(&gp102_disp_root, disp, oclass,
     46				   data, size, pobject);
     47}
     48
     49const struct nvkm_disp_oclass
     50gp102_disp_root_oclass = {
     51	.base.oclass = GP102_DISP,
     52	.base.minver = -1,
     53	.base.maxver = -1,
     54	.ctor = gp102_disp_root_new,
     55};