sornv50.c (3252B)
1/* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24#include "ior.h" 25 26#include <subdev/timer.h> 27 28void 29nv50_sor_clock(struct nvkm_ior *sor) 30{ 31 struct nvkm_device *device = sor->disp->engine.subdev.device; 32 const int div = sor->asy.link == 3; 33 const u32 soff = nv50_ior_base(sor); 34 nvkm_mask(device, 0x614300 + soff, 0x00000707, (div << 8) | div); 35} 36 37static void 38nv50_sor_power_wait(struct nvkm_device *device, u32 soff) 39{ 40 nvkm_msec(device, 2000, 41 if (!(nvkm_rd32(device, 0x61c004 + soff) & 0x80000000)) 42 break; 43 ); 44} 45 46void 47nv50_sor_power(struct nvkm_ior *sor, bool normal, bool pu, 48 bool data, bool vsync, bool hsync) 49{ 50 struct nvkm_device *device = sor->disp->engine.subdev.device; 51 const u32 soff = nv50_ior_base(sor); 52 const u32 shift = normal ? 0 : 16; 53 const u32 state = 0x80000000 | (0x00000001 * !!pu) << shift; 54 const u32 field = 0x80000000 | (0x00000001 << shift); 55 56 nv50_sor_power_wait(device, soff); 57 nvkm_mask(device, 0x61c004 + soff, field, state); 58 nv50_sor_power_wait(device, soff); 59 60 nvkm_msec(device, 2000, 61 if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000)) 62 break; 63 ); 64} 65 66void 67nv50_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state) 68{ 69 struct nvkm_device *device = sor->disp->engine.subdev.device; 70 const u32 coff = sor->id * 8 + (state == &sor->arm) * 4; 71 u32 ctrl = nvkm_rd32(device, 0x610b70 + coff); 72 73 state->proto_evo = (ctrl & 0x00000f00) >> 8; 74 switch (state->proto_evo) { 75 case 0: state->proto = LVDS; state->link = 1; break; 76 case 1: state->proto = TMDS; state->link = 1; break; 77 case 2: state->proto = TMDS; state->link = 2; break; 78 case 5: state->proto = TMDS; state->link = 3; break; 79 default: 80 state->proto = UNKNOWN; 81 break; 82 } 83 84 state->head = ctrl & 0x00000003; 85} 86 87static const struct nvkm_ior_func 88nv50_sor = { 89 .state = nv50_sor_state, 90 .power = nv50_sor_power, 91 .clock = nv50_sor_clock, 92}; 93 94int 95nv50_sor_new(struct nvkm_disp *disp, int id) 96{ 97 return nvkm_ior_new_(&nv50_sor, disp, SOR, id); 98} 99 100int 101nv50_sor_cnt(struct nvkm_disp *disp, unsigned long *pmask) 102{ 103 struct nvkm_device *device = disp->engine.subdev.device; 104 *pmask = (nvkm_rd32(device, 0x610184) & 0x03000000) >> 24; 105 return 2; 106}