channv04.h (1000B)
1/* SPDX-License-Identifier: MIT */ 2#ifndef __NV04_FIFO_CHAN_H__ 3#define __NV04_FIFO_CHAN_H__ 4#define nv04_fifo_chan(p) container_of((p), struct nv04_fifo_chan, base) 5#include "chan.h" 6#include "nv04.h" 7 8struct nv04_fifo_chan { 9 struct nvkm_fifo_chan base; 10 struct nv04_fifo *fifo; 11 u32 ramfc; 12#define NV04_FIFO_ENGN_SW 0 13#define NV04_FIFO_ENGN_GR 1 14#define NV04_FIFO_ENGN_MPEG 2 15#define NV04_FIFO_ENGN_DMA 3 16 struct nvkm_gpuobj *engn[NVKM_FIFO_ENGN_NR]; 17}; 18 19extern const struct nvkm_fifo_chan_func nv04_fifo_dma_func; 20void *nv04_fifo_dma_dtor(struct nvkm_fifo_chan *); 21void nv04_fifo_dma_init(struct nvkm_fifo_chan *); 22void nv04_fifo_dma_fini(struct nvkm_fifo_chan *); 23void nv04_fifo_dma_object_dtor(struct nvkm_fifo_chan *, int); 24 25extern const struct nvkm_fifo_chan_oclass nv04_fifo_dma_oclass; 26extern const struct nvkm_fifo_chan_oclass nv10_fifo_dma_oclass; 27extern const struct nvkm_fifo_chan_oclass nv17_fifo_dma_oclass; 28extern const struct nvkm_fifo_chan_oclass nv40_fifo_dma_oclass; 29#endif